; -------------------------------------------------------------------------------- ; @Title: AM263Px On-Chip Peripherals ; @Props: Released ; @Author: CMO ; @Changelog: 2025-07-14 CMO ; @Manufacturer: TI - Texas Instruments ; @Doc: Generated (TRACE32, build: 181776.), based on: AM263Px.xml (CCS 20.2.0) ; @Core: Cortex-R5F, Cortex-M4 ; @Chip: AM263Px ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peram263px.per 19730 2025-07-14 13:00:36Z cmorgenstern $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (((CORENAME()=="CORTEXM4F")||(CORENAME()=="CORTEXM4"))) tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXR5F") tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end endif tree "ADC" base ad:0x0 tree "ADC0_G0_G5_ADC" tree "ADC0_G0_G5_ADC_CFG" base ad:0x502C0000 group.word 0x0++0x5 line.word 0x0 "ADC_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence.Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC0_G0_G5_ADC_RESULTS" base ad:0x50100000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree "ADC1_G0_G5_ADC" tree "ADC1_G0_G5_ADC_CFG" base ad:0x502C1000 group.word 0x0++0x5 line.word 0x0 "ADC_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence.Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC1_G0_G5_ADC_RESULTS" base ad:0x50101000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree "ADC2_G0_G5_ADC" tree "ADC2_G0_G5_ADC_CFG" base ad:0x502C2000 group.word 0x0++0x5 line.word 0x0 "ADC_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence.Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC2_G0_G5_ADC_RESULTS" base ad:0x50102000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree "ADC3_G0_G5_ADC" tree "ADC3_G0_G5_ADC_CFG" base ad:0x502C3000 group.word 0x0++0x5 line.word 0x0 "ADC_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence.Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC3_G0_G5_ADC_RESULTS" base ad:0x50103000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree "ADC4_G0_G5_ADC" tree "ADC4_G0_G5_ADC_CFG" base ad:0x502C4000 group.word 0x0++0x5 line.word 0x0 "ADC_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence.Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC4_G0_G5_ADC_RESULTS" base ad:0x50104000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree "ADC_R0_ADC_R" tree "ADC_R0_ADC_R_CFG" base ad:0x502C5000 group.word 0x0++0x5 line.word 0x0 "ADC_R_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_R_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_R_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 -.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_R_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_R_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_R_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_R_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_R_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_R_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_R_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_R_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_R_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_R_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_R_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_R_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_R_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_R_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_R_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_R_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_R_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_R_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_R_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_R_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_R_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_R_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_R_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_R_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_R_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_R_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_R_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_R_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_R_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_R_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_R_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_R_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_R_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_R_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_R_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_R_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_R_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_R_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_R_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_R_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_R_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_R_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC_R0_ADC_R_RESULTS" base ad:0x502C6000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_R_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_R_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_R_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_R_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_R_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_R_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_R_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_R_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_R_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_R_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_R_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_R_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_R_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_R_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_R_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_R_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_R_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_R_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_R_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_R_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_R_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree "ADC_R1_ADC_R" tree "ADC_R1_ADC_R_CFG" base ad:0x502C7000 group.word 0x0++0x5 line.word 0x0 "ADC_R_CFG_ADCCTL1,ADC Control 1 Register." bitfld.word 0x0 15. "TDMAEN,Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt.." "0,1" newline bitfld.word 0x0 14. "EXTMUXPRESELECTEN,If th the ADC SOC sequence is deterministic the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the.." "0,1" newline rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY0:holds the value of the last converted SOC When ADCBSY1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted.." newline bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" newline bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "ADC_R_CFG_ADCCTL2,ADC Control 2 Register." bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" newline bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution" "0,1" newline hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK.." line.word 0x4 "ADC_R_CFG_ADCBURSTCTL,ADC Burst Control Register." bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" newline hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." newline hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 -.." rgroup.word 0x6++0x1 line.word 0x0 "ADC_R_CFG_ADCINTFLG,ADC Interrupt Flag Register." bitfld.word 0x0 7. "ADCINT4RESULT,ADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 6. "ADCINT3RESULT,ADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 5. "ADCINT2RESULT,ADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 4. "ADCINT1RESULT,ADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register. 0 Conversion results have not latched 1 Conversion results have latched This.." "0,1" newline bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_R_CFG_ADCINTFLGCLR,ADC Interrupt Flag Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority and the.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "ADC_R_CFG_ADCINTOVF,ADC Interrupt Overflow Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "ADC_R_CFG_ADCINTOVFCLR,ADC Interrupt Overflow Clear Register." bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" newline bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "ADC_R_CFG_ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register." bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" newline hexmask.word.byte 0x2 8.--12. 1. "INT2SEL,ADCINT2 EOC Source Select 00h EOC0 is trigger for ADCINT2 01h EOC1 is trigger for ADCINT2 02h EOC2 is trigger for ADCINT2 03h EOC3 is trigger for ADCINT2 04h EOC4 is trigger for ADCINT2 05h EOC5 is trigger for ADCINT2 06h EOC6 is trigger.." newline bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" newline hexmask.word.byte 0x2 0.--4. 1. "INT1SEL,ADCINT1 EOC Source Select 00h EOC0 is trigger for ADCINT1 01h EOC1 is trigger for ADCINT1 02h EOC2 is trigger for ADCINT1 03h EOC3 is trigger for ADCINT1 04h EOC4 is trigger for ADCINT1 05h EOC5 is trigger for ADCINT1 06h EOC6 is trigger.." line.word 0x4 "ADC_R_CFG_ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register." bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" newline hexmask.word.byte 0x4 8.--12. 1. "INT4SEL,ADCINT4 EOC Source Select 00h EOC0 is trigger for ADCINT4 01h EOC1 is trigger for ADCINT4 02h EOC2 is trigger for ADCINT4 03h EOC3 is trigger for ADCINT4 04h EOC4 is trigger for ADCINT4 05h EOC5 is trigger for ADCINT4 06h EOC6 is trigger.." newline bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag [in ADCINTFLG register] is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" newline hexmask.word.byte 0x4 0.--4. 1. "INT3SEL,ADCINT3 EOC Source Select 00h EOC0 is trigger for ADCINT3 01h EOC1 is trigger for ADCINT3 02h EOC2 is trigger for ADCINT3 03h EOC3 is trigger for ADCINT3 04h EOC4 is trigger for ADCINT3 05h EOC5 is trigger for ADCINT3 06h EOC6 is trigger.." line.word 0x6 "ADC_R_CFG_ADCSOCPRICTL,ADC SOC Priority Control Register." hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h SOC1.." newline hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "ADC_R_CFG_ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register." bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "ADC_R_CFG_ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register." bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCFLG1,ADC SOC Flag 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is started." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is started." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is started." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is started." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is started." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is started." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCFRC1,ADC SOC Force 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCOVF1,ADC SOC Overflow 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15 events.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14 events.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13 events.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12 events.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11 events.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10 events.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "ADC_R_CFG_ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register." bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "ADC_R_CFG_ADCSOC0CTL,ADC SOC0 Control Register." hexmask.long.byte 0x0 28.--31. 1. "EXTCHSEL,SOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x0 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x4 "ADC_R_CFG_ADCSOC1CTL,ADC SOC1 Control Register." hexmask.long.byte 0x4 28.--31. 1. "EXTCHSEL,SOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x4 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x8 "ADC_R_CFG_ADCSOC2CTL,ADC SOC2 Control Register." hexmask.long.byte 0x8 28.--31. 1. "EXTCHSEL,SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x8 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0xC "ADC_R_CFG_ADCSOC3CTL,ADC SOC3 Control Register." hexmask.long.byte 0xC 28.--31. 1. "EXTCHSEL,SOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0xC 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x10 "ADC_R_CFG_ADCSOC4CTL,ADC SOC4 Control Register." hexmask.long.byte 0x10 28.--31. 1. "EXTCHSEL,SOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x10 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x14 "ADC_R_CFG_ADCSOC5CTL,ADC SOC5 Control Register." hexmask.long.byte 0x14 28.--31. 1. "EXTCHSEL,SOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x14 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x18 "ADC_R_CFG_ADCSOC6CTL,ADC SOC6 Control Register." hexmask.long.byte 0x18 28.--31. 1. "EXTCHSEL,SOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x18 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x1C "ADC_R_CFG_ADCSOC7CTL,ADC SOC7 Control Register." hexmask.long.byte 0x1C 28.--31. 1. "EXTCHSEL,SOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x1C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x20 "ADC_R_CFG_ADCSOC8CTL,ADC SOC8 Control Register." hexmask.long.byte 0x20 28.--31. 1. "EXTCHSEL,SOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x20 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x24 "ADC_R_CFG_ADCSOC9CTL,ADC SOC9 Control Register." hexmask.long.byte 0x24 28.--31. 1. "EXTCHSEL,SOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note:.." newline hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential.." newline rbitfld.long 0x24 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x28 "ADC_R_CFG_ADCSOC10CTL,ADC SOC10 Control Register." hexmask.long.byte 0x28 28.--31. 1. "EXTCHSEL,SOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x28 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x2C "ADC_R_CFG_ADCSOC11CTL,ADC SOC11 Control Register." hexmask.long.byte 0x2C 28.--31. 1. "EXTCHSEL,SOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x2C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x30 "ADC_R_CFG_ADCSOC12CTL,ADC SOC12 Control Register." hexmask.long.byte 0x30 28.--31. 1. "EXTCHSEL,SOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x30 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x34 "ADC_R_CFG_ADCSOC13CTL,ADC SOC13 Control Register." hexmask.long.byte 0x34 28.--31. 1. "EXTCHSEL,SOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x34 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x38 "ADC_R_CFG_ADCSOC14CTL,ADC SOC14 Control Register." hexmask.long.byte 0x38 28.--31. 1. "EXTCHSEL,SOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x38 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." line.long 0x3C "ADC_R_CFG_ADCSOC15CTL,ADC SOC15 Control Register." hexmask.long.byte 0x3C 28.--31. 1. "EXTCHSEL,SOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux. 0h.." newline hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." newline hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31.." newline rbitfld.long 0x3C 12.--14. "RESOLUTION,Placeholder for per-SOC resolution" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 10.--11. "SIGNALMODE,Placeholder for per-SOC signal mode" "0,1,2,3" newline hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512.." rgroup.word 0x60++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTSTAT,ADC Event Status Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine both.." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred. Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this an ISR may need to examine.." "0,1" group.word 0x64++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTCLR,ADC Event Clear Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has priority" "0,1" group.word 0x68++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTSEL,ADC Event Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "ADC_R_CFG_ADCEVTINTSEL,ADC Event Interrupt Selection Register." bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" newline bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" rgroup.word 0x72++0x3 line.word 0x0 "ADC_R_CFG_ADCCOUNTER,ADC Counter Register." hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "ADC_R_CFG_ADCREV,ADC Revision Register." hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x80++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1CONFIG,ADC PPB1 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x82++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB1OFFREF,ADC PPB1 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB1TRIPHI,ADC PPB1 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM 1 = Low limit set by ADCPPB1TRIPLO2 register" "0: Low limit set by ADCPPB1TRIPLO register,1: Low limit set by ADCPPB1TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2CONFIG,ADC PPB2 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0x92++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB2OFFREF,ADC PPB2 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB2TRIPHI,ADC PPB2 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM 1 = Low limit set by ADCPPB2TRIPLO2 register" "0: Low limit set by ADCPPB2TRIPLO register,1: Low limit set by ADCPPB2TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3CONFIG,ADC PPB3 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xA2++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB3OFFREF,ADC PPB3 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB3TRIPHI,ADC PPB3 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM 1 = Low limit set by ADCPPB3TRIPLO2 register" "0: Low limit set by ADCPPB3TRIPLO register,1: Low limit set by ADCPPB3TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4CONFIG,ADC PPB4 Config Register." bitfld.word 0x0 6. "ABSEN,ADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4. This occurs before the TWOSCOMPEN logic is evaluated [so enabling both TWOSCOMPEN and ABSEN will.." "0,1" newline bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" newline bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated with.." rgroup.word 0xB2++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register." hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "ADC_R_CFG_ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register." hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "ADC_R_CFG_ADCPPB4OFFREF,ADC PPB4 Offset Reference Register." hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0xB line.long 0x0 "ADC_R_CFG_ADCPPB4TRIPHI,ADC PPB4 Trip High Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPHI[23:17] will be ignored in 16 bit mode - TRIPHI[23:13] will.." line.long 0x4 "ADC_R_CFG_ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register." hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." newline bitfld.long 0x4 19. "LIMITLO2EN,Extended Low Limit 2 Enable. 0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM 1 = Low limit set by ADCPPB4TRIPLO2 register" "0: Low limit set by ADCPPB4TRIPLO register,1: Low limit set by ADCPPB4TRIPLO2 register" newline bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit [17th bit] to the LIMITLO bit field when in 16-bit ADC mode." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." line.long 0x8 "ADC_R_CFG_ADCSAFECHECKRESEN,ADC Safe Check Result Enable Register." bitfld.long 0x8 30.--31. "SOC15CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 28.--29. "SOC14CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "SOC13CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 24.--25. "SOC12CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "SOC11CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 20.--21. "SOC10CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "SOC9CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 16.--17. "SOC8CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 14.--15. "SOC7CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 12.--13. "SOC6CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 10.--11. "SOC5CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 8.--9. "SOC4CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 6.--7. "SOC3CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 4.--5. "SOC2CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "SOC1CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" newline bitfld.long 0x8 0.--1. "SOC0CHKEN,Determine which result will be passed to the safety result checker. Only one of the raw ADC result the PPB result or the final PPB accumulated SUM can be passed on to the checker for each conversion. 00 No result passed to safety checker.." "0,1,2,3" group.word 0xDE++0x1 line.word 0x0 "ADC_R_CFG_ADCINTCYCLE,ADC Early Interrupt Generation Cycle." hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." rgroup.word 0xFA++0x1 line.word 0x0 "ADC_R_CFG_ADCREV2,ADC Wrapper Revision Register." hexmask.word.byte 0x0 8.--15. 1. "WRAPPERREV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as00h" newline hexmask.word.byte 0x0 0.--7. 1. "WRAPPERTYPE,ADC Wrapper Type. Always set to 4 for this ADC." group.long 0xFC++0x13 line.long 0x0 "ADC_R_CFG_ADCINLTRIMCTL,ADC Linearity Trim Control Register." hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." newline hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." newline bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" line.long 0x4 "ADC_R_CFG_REP1CTL,ADC Trigger Repeater 1 Control Register." bitfld.long 0x4 23. "SWSYNC,Trigger repeater 1 software force sync. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "SYNCINSEL,Trigger repeater 1 sync. input select. On a sync. event all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared." newline hexmask.long.byte 0x4 8.--14. 1. "TRIGGER,ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x4 7. "TRIGGEROVF,ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were.." "0,1" newline bitfld.long 0x4 6. "PHASEOVF,ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x4 4. "SOCBUSY,ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x4 3. "MODULEBUSY,ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 1 is idle and can accept a new repeated..,1: Repeater 1 still has repeated triggers remaining.." newline rbitfld.long 0x4 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x4 0. "MODE,ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP1CTL.TRIGSEL is received the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x8 "ADC_R_CFG_REP1N,ADC Trigger Repeater 1 N Select Register." hexmask.long.byte 0x8 16.--22. 1. "NCOUNT,ADC trigger repeater 1 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x8 0.--6. 1. "NSEL,ADC Trigger Repeater 1 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0xC "ADC_R_CFG_REP1PHASE,ADC Trigger Repeater 1 Phase Select Register." hexmask.long.word 0xC 16.--31. 1. "PHASECOUNT,ADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0xC 0.--15. 1. "PHASE,ADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0x10 "ADC_R_CFG_REP1SPREAD,ADC Trigger Repeater 1 Spread Select Register." hexmask.long.word 0x10 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0x10 0.--15. 1. "SPREAD,ADC trigger repeater 1 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x110++0x1 line.word 0x0 "ADC_R_CFG_REP1FRC,ADC Trigger Repeater 1 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.long 0x120++0xF line.long 0x0 "ADC_R_CFG_REP2CTL,ADC Trigger Repeater 2 Control Register." bitfld.long 0x0 23. "SWSYNC,Trigger repeater 2 software force sync. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "SYNCINSEL,Trigger repeater 2 sync. input select. On a sync. event all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL PHASE and MODE are preserved. Note: SOCs associated with repeater 2 are not cleared." newline hexmask.long.byte 0x0 8.--14. 1. "TRIGGER,ADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h.." newline bitfld.long 0x0 7. "TRIGGEROVF,ADC Trigger Repeater 2 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 2 were.." "0,1" newline bitfld.long 0x0 6. "PHASEOVF,ADC Trigger Repeater 2 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag." "0,1" newline rbitfld.long 0x0 4. "SOCBUSY,ADC Trigger Repeater 2 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode.." "0: no SOCs associated with this repeater are pending,1: SOCs associated with this repeater are still.." newline rbitfld.long 0x0 3. "MODULEBUSY,ADC Trigger Repeater 2 Module Busy indicator. In oversampling mode: 0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 2 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are.." "0: Repeater 2 is idle and can accept a new repeated..,1: Repeater 2 still has repeated triggers remaining.." newline rbitfld.long 0x0 1. "ACTIVEMODE,When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't.." "0: module is oversampling,1: module is undersampling" newline bitfld.long 0x0 0. "MODE,ADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode. In oversampling mode when the trigger selected by REP2CTL.TRIGSEL is received the repeater will repeat the trigger REP2N.NSEL + 1 times. In undersampling.." "0: oversampling,1: undersampling" line.long 0x4 "ADC_R_CFG_REP2N,ADC Trigger Repeater 2 N Select Register." hexmask.long.byte 0x4 16.--22. 1. "NCOUNT,ADC trigger repeater 2 trigger count. In oversampling mode indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 [the repeater is still busy generating the.." newline hexmask.long.byte 0x4 0.--6. 1. "NSEL,ADC Trigger Repeater 2 selection of number of triggers. In oversampling mode selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL NSEL + 1 triggers will be generated. 0 = 1 trigger is generated.." line.long 0x8 "ADC_R_CFG_REP2PHASE,ADC Trigger Repeater 2 Phase Select Register." hexmask.long.word 0x8 16.--31. 1. "PHASECOUNT,ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received this register will start counting down from PHASECOUNT until the counter reaches 0 at which point the trigger will be passed on to the.." newline hexmask.long.word 0x8 0.--15. 1. "PHASE,ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 =.." line.long 0xC "ADC_R_CFG_REP2SPREAD,ADC Trigger Repeater 2 Spread Select Register." hexmask.long.word 0xC 16.--31. 1. "SPREADCOUNT,ADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode this register will start counting down from SPREAD until SPREADCOUNT equals 0. The next repeated trigger to the ADC in oversampling mode will not.." newline hexmask.long.word 0xC 0.--15. 1. "SPREAD,ADC trigger repeater 2 spread delay configuration. In oversampling mode defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC. If SPREAD is less than the time needed for all SOCs associated with.." group.word 0x130++0x1 line.word 0x0 "ADC_R_CFG_REP2FRC,ADC Trigger Repeater 2 Software Force Register." bitfld.word 0x0 0. "SWFRC,Write 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER. Always reads 0." "0,1" group.word 0x140++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1LIMIT,ADC PPB1Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x144++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP1PCOUNT,ADC PPB1 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1. This register is reset when either a count-match event.." group.word 0x148++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1CONFIG2,ADC PPB1 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT ADCPPB1PSUM or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB1RESULT is used for compare logic 01 =.." "0: ADCPPB1RESULT is used for compare logic,1: ADCPPB1PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 1 Interrupt Source Select. OSINT1 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to.." "0: OSINT1 will be generated from PCOUNT = LIMIT only,1: OSTIN1 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 1 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 1 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x14C++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB1PSUM,ADC PPB1 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB1PMAX,ADC PPB1 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x154++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1PMAXI,ADC PPB1 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x158++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB1PMIN,ADC PPB1 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x15C++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB1PMINI,ADC PPB1 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x160++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB1TRIPLO2,ADC PPB1 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x174++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2LIMIT,ADC PPB2Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x178++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP2PCOUNT,ADC PPB2 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x17C++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2CONFIG2,ADC PPB2 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT ADCPPB2PSUM or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB2RESULT is used for compare logic 01 =.." "0: ADCPPB2RESULT is used for compare logic,1: ADCPPB2PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 2 Interrupt Source Select. OSINT2 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to.." "0: OSINT2 will be generated from PCOUNT = LIMIT only,1: OSTIN2 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 2 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 2 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x180++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB2PSUM,ADC PPB2 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB2PMAX,ADC PPB2 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x188++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2PMAXI,ADC PPB2 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x18C++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB2PMIN,ADC PPB2 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x190++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB2PMINI,ADC PPB2 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x194++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB2TRIPLO2,ADC PPB2 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1A8++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3LIMIT,ADC PPB3Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1AC++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP3PCOUNT,ADC PPB3 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1B0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3CONFIG2,ADC PPB3 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT ADCPPB3PSUM or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB3RESULT is used for compare logic 01 =.." "0: ADCPPB3RESULT is used for compare logic,1: ADCPPB3PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 3 Interrupt Source Select. OSINT3 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to.." "0: OSINT3 will be generated from PCOUNT = LIMIT only,1: OSTIN3 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 3 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 3 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1B4++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB3PSUM,ADC PPB3 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB3PMAX,ADC PPB3 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1BC++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3PMAXI,ADC PPB3 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1C0++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB3PMIN,ADC PPB3 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1C4++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB3PMINI,ADC PPB3 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1C8++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB3TRIPLO2,ADC PPB3 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." group.word 0x1DC++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4LIMIT,ADC PPB4Conversion Count Limit Register." hexmask.word 0x0 0.--9. 1. "LIMIT,Post Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM. To prevent PSUM from overflowing do not write a value larger than 128 when the ADC is operating in 16-bit.." rgroup.word 0x1E0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPBP4PCOUNT,ADC PPB4 Partial Conversion Count Register." hexmask.word 0x0 0.--9. 1. "PCOUNT,Post Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1. This register is reset when either a count-match event occurs.." group.word 0x1E4++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4CONFIG2,ADC PPB4 Sum Shift Register." bitfld.word 0x0 14.--15. "COMPSEL,Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT ADCPPB4PSUM or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 =.." "0: ADCPPB4RESULT is used for compare logic,1: ADCPPB4PSUM is used for compare logic,?,?" newline bitfld.word 0x0 12. "OSINTSEL,Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to.." "0: OSINT4 will be generated from PCOUNT = LIMIT only,1: OSTIN4 will be generated form PCOUNT = LIMIT or.." newline bitfld.word 0x0 11. "SWSYNC,PPB 4 software force sync. On a sync. event all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is.." "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "SYNCINSEL,PPB 4 sync. input select. On a sync. event all partial registers transfer to the final registers and are then reset. Refer to SOC spec for details" newline hexmask.word.byte 0x0 0.--3. 1. "SHIFT,Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 -15 : Reserved" rgroup.long 0x1E8++0x7 line.long 0x0 "ADC_R_CFG_ADCPPB4PSUM,ADC PPB4 Partial Sum Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." newline hexmask.long.tbyte 0x0 0.--23. 1. "PSUM,Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a.." line.long 0x4 "ADC_R_CFG_ADCPPB4PMAX,ADC PPB4 Partial Max Register." hexmask.long.word 0x4 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x4 0.--16. 1. "PMAX,Post Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger. This register is reset when either a count-match.." rgroup.word 0x1F0++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4PMAXI,ADC PPB4 Partial Max Index Register." hexmask.word 0x0 0.--9. 1. "PMAXI,Post Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT. This.." rgroup.long 0x1F4++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB4PMIN,ADC PPB4 Partial MIN Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." newline hexmask.long.tbyte 0x0 0.--16. 1. "PMIN,Post Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller. This register is reset when either a count-match.." rgroup.word 0x1F8++0x1 line.word 0x0 "ADC_R_CFG_ADCPPB4PMINI,ADC PPB4 Partial Min Index Register." hexmask.word 0x0 0.--9. 1. "PMINI,Post Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT. This.." group.long 0x1FC++0x3 line.long 0x0 "ADC_R_CFG_ADCPPB4TRIPLO2,ADC PPB4 Extended Trip Low Register." hexmask.long.tbyte 0x0 0.--23. 1. "LIMITLO,ADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1. When comparing to an ADCPPBxRESULT register the upper bits will be ignored: - TRIPLO2[23:17] will be ignored.." tree.end tree "ADC_R1_ADC_R_RESULTS" base ad:0x502C8000 rgroup.word 0x0++0x1F line.word 0x0 "ADC_R_RESULTS_ADCRESULT0,ADC Result 0 Register." hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "ADC_R_RESULTS_ADCRESULT1,ADC Result 1 Register." hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "ADC_R_RESULTS_ADCRESULT2,ADC Result 2 Register." hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "ADC_R_RESULTS_ADCRESULT3,ADC Result 3 Register." hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "ADC_R_RESULTS_ADCRESULT4,ADC Result 4 Register." hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "ADC_R_RESULTS_ADCRESULT5,ADC Result 5 Register." hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "ADC_R_RESULTS_ADCRESULT6,ADC Result 6 Register." hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "ADC_R_RESULTS_ADCRESULT7,ADC Result 7 Register." hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "ADC_R_RESULTS_ADCRESULT8,ADC Result 8 Register." hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "ADC_R_RESULTS_ADCRESULT9,ADC Result 9 Register." hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "ADC_R_RESULTS_ADCRESULT10,ADC Result 10 Register." hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "ADC_R_RESULTS_ADCRESULT11,ADC Result 11 Register." hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "ADC_R_RESULTS_ADCRESULT12,ADC Result 12 Register." hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "ADC_R_RESULTS_ADCRESULT13,ADC Result 13 Register." hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "ADC_R_RESULTS_ADCRESULT14,ADC Result 14 Register." hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "ADC_R_RESULTS_ADCRESULT15,ADC Result 15 Register." hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0x13 line.long 0x0 "ADC_R_RESULTS_ADCPPB1RESULT,ADC Post Processing Block 1 Result Register." hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x4 "ADC_R_RESULTS_ADCPPB2RESULT,ADC Post Processing Block 2 Result Register." hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x8 "ADC_R_RESULTS_ADCPPB3RESULT,ADC Post Processing Block 3 Result Register." hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0xC "ADC_R_RESULTS_ADCPPB4RESULT,ADC Post Processing Block 4 Result Register." hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available unless multiple.." line.long 0x10 "ADC_R_RESULTS_ADCPPB1SUM,ADC PPB 1 Final Sum Result Register." hexmask.long.byte 0x10 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x10 0.--23. 1. "SUM,Post Processing Block 1 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x34++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB1COUNT,ADC PPB1 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 1 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x38++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB2SUM,ADC PPB 2 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 2 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x3C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB2COUNT,ADC PPB2 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 2 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x40++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB3SUM,ADC PPB 3 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 3 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x44++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB3COUNT,ADC PPB3 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 3 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x48++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB4SUM,ADC PPB 4 Final Sum Result Register." hexmask.long.byte 0x0 24.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 23." hexmask.long.tbyte 0x0 0.--23. 1. "SUM,Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PSUM is loaded into this register. In the case of a count-match event the sum loaded into this.." rgroup.word 0x4C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB4COUNT,ADC PPB4 Final Conversion Count Register." hexmask.word 0x0 0.--9. 1. "COUNT,Post Processing Block 4 Oversampling Final Count. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PCOUNT is loaded into this register. This result is available 1 SYSCLK cycle after the.." rgroup.long 0x50++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB1MAX,ADC PPB 1 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 1 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x54++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB1MAXI,ADC PPB 1 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 1 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x58++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB1MIN,ADC PPB 1 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 1 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x5C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB1MINI,ADC PPB 1 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 1 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB1 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x60++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB2MAX,ADC PPB 2 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 2 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x64++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB2MAXI,ADC PPB 2 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 2 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x68++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB2MIN,ADC PPB 2 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 2 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x6C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB2MINI,ADC PPB 2 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 2 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB2 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x70++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB3MAX,ADC PPB 3 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 3 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x74++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB3MAXI,ADC PPB 3 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 3 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x78++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB3MIN,ADC PPB 3 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 3 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x7C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB3MINI,ADC PPB 3 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 3 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB3 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." rgroup.long 0x80++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB4MAX,ADC PPB 4 Final Max Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MAX,Post Processing Block 4 Oversampling Final Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAX is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x84++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB4MAXI,ADC PPB 4 Final Max Index Result Register." hexmask.word 0x0 0.--9. 1. "MAXI,Post Processing Block 4 Oversampling Final Index of the Max. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMAXI is loaded into this register. In the case of a count-match event the max index.." rgroup.long 0x88++0x3 line.long 0x0 "ADC_R_RESULTS_ADCPPB4MIN,ADC PPB 4 Final Min Result Register." hexmask.long.word 0x0 17.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16." hexmask.long.tbyte 0x0 0.--16. 1. "MIN,Post Processing Block 4 Oversampling Final Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMIN is loaded into this register. In the case of a count-match event the max loaded into this.." rgroup.word 0x8C++0x1 line.word 0x0 "ADC_R_RESULTS_ADCPPB4MINI,ADC PPB 4 Final Min Index Result Register." hexmask.word 0x0 0.--9. 1. "MINI,Post Processing Block 4 Oversampling Final Index of the Min. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event the value of PMINI is loaded into this register. In the case of a count-match event the min index.." tree.end tree.end tree.end tree "ADCSAFE" base ad:0x0 tree "ADCSAFE_00" tree "ADCSAFE_00_ADC_SAFETY" base ad:0x502CB400 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_00_ADC_SAFETY_AGGR" base ad:0x502CEC00 rgroup.long 0x0++0x3 line.long 0x0 "ADC_SAFETY_AGGR_OOTFLG,Checker Out-of-Tolerance Flag Register." bitfld.long 0x0 11. "OOT12,ADC results safety checker 12 out-of-tolerance flag. Set when CHECK12 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 10. "OOT11,ADC results safety checker 11 out-of-tolerance flag. Set when CHECK11 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 9. "OOT10,ADC results safety checker 10 out-of-tolerance flag. Set when CHECK10 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 8. "OOT9,ADC results safety checker 1 out-of-tolerance flag. Set when CHECK9 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 7. "OOT8,ADC results safety checker 8 out-of-tolerance flag. Set when CHECK8 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 6. "OOT7,ADC results safety checker 7 out-of-tolerance flag. Set when CHECK7 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 5. "OOT6,ADC results safety checker 6 out-of-tolerance flag. Set when CHECK6 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" newline bitfld.long 0x0 4. "OOT5,ADC results safety checker 5 out-of-tolerance flag. Set when CHECK5 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 3. "OOT4,ADC results safety checker 4 out-of-tolerance flag. Set when CHECK4 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 2. "OOT3,ADC results safety checker 3 out-of-tolerance flag. Set when CHECK3 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 1. "OOT2,ADC results safety checker 2 out-of-tolerance flag. Set when CHECK2 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 0. "OOT1,ADC results safety checker 1 out-of-tolerance flag. Set when CHECK1 detects a difference between configured conversion results greater than the configured tolerance. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" group.long 0x4++0x3 line.long 0x0 "ADC_SAFETY_AGGR_OOTFLGCLR,Checker Out-of-Tolerance Flag Clear Register." bitfld.long 0x0 11. "OOT12,ADC results safety checker 12 out-of-tolerance flag clear. Used to clear OOT status from CHECK12. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 10. "OOT11,ADC results safety checker 11 out-of-tolerance flag clear. Used to clear OOT status from CHECK11. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 9. "OOT10,ADC results safety checker 10 out-of-tolerance flag clear. Used to clear OOT status from CHECK10. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 8. "OOT9,ADC results safety checker 9 out-of-tolerance flag clear. Used to clear OOT status from CHECK9. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 7. "OOT8,ADC results safety checker 8 out-of-tolerance flag clear. Used to clear OOT status from CHECK8. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 6. "OOT7,ADC results safety checker 7 out-of-tolerance flag clear. Used to clear OOT status from CHECK7. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 5. "OOT6,ADC results safety checker 6 out-of-tolerance flag clear. Used to clear OOT status from CHECK6. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" newline bitfld.long 0x0 4. "OOT5,ADC results safety checker 5 out-of-tolerance flag clear. Used to clear OOT status from CHECK5. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 3. "OOT4,ADC results safety checker 4 out-of-tolerance flag clear. Used to clear OOT status from CHECK4. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 2. "OOT3,ADC results safety checker 3 out-of-tolerance flag clear. Used to clear OOT status from CHECK3. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 1. "OOT2,ADC results safety checker 2 out-of-tolerance flag clear. Used to clear OOT status from CHECK2. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" bitfld.long 0x0 0. "OOT1,ADC results safety checker 1 out-of-tolerance flag clear. Used to clear OOT status from CHECK1. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHKINTFLG.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "ADC_SAFETY_AGGR_RES1OVF,Checker Overflow Result 1 Flag Register." bitfld.long 0x0 11. "RES1OVF12,ADC results safety checker 12 overflow flag for result 1. Set when CHECK12 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 10. "RES1OVF11,ADC results safety checker 11 overflow flag for result 1. Set when CHECK11 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 9. "RES1OVF10,ADC results safety checker 10 overflow flag for result 1. Set when CHECK10 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 8. "RES1OVF9,ADC results safety checker 9 overflow flag for result 1. Set when CHECK9 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 7. "RES1OVF8,ADC results safety checker 8 overflow flag for result 1. Set when CHECK8 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 6. "RES1OVF7,ADC results safety checker 7 overflow flag for result 1. Set when CHECK7 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 5. "RES1OVF6,ADC results safety checker 6 overflow flag for result 1. Set when CHECK6 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" newline bitfld.long 0x0 4. "RES1OVF5,ADC results safety checker 5 overflow flag for result 1. Set when CHECK5 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 3. "RES1OVF4,ADC results safety checker 4 overflow flag for result 1. Set when CHECK4 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 2. "RES1OVF3,ADC results safety checker 3 overflow flag for result 1. Set when CHECK3 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 1. "RES1OVF2,ADC results safety checker 2 overflow flag for result 1. Set when CHECK2 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 0. "RES1OVF1,ADC results safety checker 1 overflow flag for result 1. Set when CHECK1 detects that conversion result 1 has arrived more than once before result 2 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" group.long 0xC++0x3 line.long 0x0 "ADC_SAFETY_AGGR_RES1OVFCLR,Checker Overflow Result 1 Flag Clear Register." bitfld.long 0x0 11. "RES1OVF12,ADC results safety checker 12 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK12. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 10. "RES1OVF11,ADC results safety checker 11 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK11. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 9. "RES1OVF10,ADC results safety checker 10 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK10. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 8. "RES1OVF9,ADC results safety checker 9 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK9. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 7. "RES1OVF8,ADC results safety checker 8 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK8. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 6. "RES1OVF7,ADC results safety checker 7 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK7. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 5. "RES1OVF6,ADC results safety checker 6 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK6. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" newline bitfld.long 0x0 4. "RES1OVF5,ADC results safety checker 5 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK5. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 3. "RES1OVF4,ADC results safety checker 4 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK4. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 2. "RES1OVF3,ADC results safety checker 3 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK3. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 1. "RES1OVF2,ADC results safety checker 2 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK2. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" bitfld.long 0x0 0. "RES1OVF1,ADC results safety checker 1 result 1 overflow flag clear. Used to clear RES1OVF status from CHECK1. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the.." "0,1" rgroup.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_AGGR_RES2OVF,Checker Overflow Result 2 Flag Register." bitfld.long 0x0 11. "RES2OVF12,ADC results safety checker 12 overflow flag for result 2. Set when CHECK12 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 10. "RES2OVF11,ADC results safety checker 11 overflow flag for result 2. Set when CHECK11 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 9. "RES2OVF10,ADC results safety checker 10 overflow flag for result 2. Set when CHECK10 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 .." "0,1" bitfld.long 0x0 8. "RES2OVF9,ADC results safety checker 9 overflow flag for result 2. Set when CHECK9 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 7. "RES2OVF8,ADC results safety checker 8 overflow flag for result 2. Set when CHECK8 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 6. "RES2OVF7,ADC results safety checker 7 overflow flag for result 2. Set when CHECK7 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 5. "RES2OVF6,ADC results safety checker 6 overflow flag for result 2. Set when CHECK6 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" newline bitfld.long 0x0 4. "RES2OVF5,ADC results safety checker 5 overflow flag for result 2. Set when CHECK5 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 3. "RES2OVF4,ADC results safety checker 4 overflow flag for result 2. Set when CHECK4 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 2. "RES2OVF3,ADC results safety checker 3 overflow flag for result 2. Set when CHECK3 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 1. "RES2OVF2,ADC results safety checker 2 overflow flag for result 2. Set when CHECK2 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" bitfld.long 0x0 0. "RES2OVF1,ADC results safety checker 1 overflow flag for result 2. Set when CHECK1 detects that conversion result 2 has arrived more than once before result 1 has arrived. Use the CHECKINTSEL1 CHECKINTSEL2 CHECKINTSEL3 CHECKEVTxSEL1 CHECKEVTxSEL2 .." "0,1" group.long 0x14++0x3 line.long 0x0 "ADC_SAFETY_AGGR_RES2OVFCLR,Checker Overflow Result 2 Flag Clear Register." bitfld.long 0x0 11. "RES2OVF12,ADC results safety checker 12 result overflow flag clear. Used to clear OVF status from CHECK12. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 10. "RES2OVF11,ADC results safety checker 11 result overflow flag clear. Used to clear OVF status from CHECK11. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 9. "RES2OVF10,ADC results safety checker 10 result overflow flag clear. Used to clear OVF status from CHECK10. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 8. "RES2OVF9,ADC results safety checker 9 result overflow flag clear. Used to clear OVF status from CHECK9. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 7. "RES2OVF8,ADC results safety checker 8 result overflow flag clear. Used to clear OVF status from CHECK8. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 6. "RES2OVF7,ADC results safety checker 7 result overflow flag clear. Used to clear OVF status from CHECK7. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 5. "RES2OVF6,ADC results safety checker 6 result overflow flag clear. Used to clear OVF status from CHECK6. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" newline bitfld.long 0x0 4. "RES2OVF5,ADC results safety checker 5 result overflow flag clear. Used to clear OVF status from CHECK5. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 3. "RES2OVF4,ADC results safety checker 4 result overflow flag clear. Used to clear OVF status from CHECK4. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 2. "RES2OVF3,ADC results safety checker 3 result overflow flag clear. Used to clear OVF status from CHECK3. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 1. "RES2OVF2,ADC results safety checker 2 result overflow flag clear. Used to clear OVF status from CHECK2. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" bitfld.long 0x0 0. "RES2OVF1,ADC results safety checker 1 result overflow flag clear. Used to clear OVF status from CHECK1. In the case of a safety checker interrupt clear all serviced OOT or OVF flags first then clear the global interrupt flag [in the CHECKINTFLG.." "0,1" rgroup.word 0x18++0x1 line.word 0x0 "ADC_SAFETY_AGGR_CHECKINTFLG,Checker Interrupt Flag Register." bitfld.word 0x0 0. "CHECKINT,ADC results safety checker subsytem interrupt flag. Indicates that one or more configured OOT or OVF conditions have occurred in the individual safety checker modules. In the ISR clear all serviced OOT or OVF flags first [using the.." "0,1" group.word 0x1C++0x1 line.word 0x0 "ADC_SAFETY_AGGR_CHECKINTFLGCLR,Checker Interrupt Flag Clear Register." bitfld.word 0x0 0. "CHECKINTCLR,ADC results safety checker subsytem interrupt flag clear. Used to clear the global safety checker subsystem interrupt flag. In the ISR clear all serviced OOT or OVF flags first [using the OOTFLGCLR and OVFFLGCLR registers] then clear the.." "0,1" group.long 0x20++0xB line.long 0x0 "ADC_SAFETY_AGGR_CHECKINTSEL1,Checker Interrupt Source Select Register 1" bitfld.long 0x0 11. "RES1OVF12EN,Enable CHECK12 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 10. "RES1OVF11EN,Enable CHECK11 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 9. "RES1OVF10EN,Enable CHECK10 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 8. "RES1OVF9EN,Enable CHECK9 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 7. "RES1OVF8EN,Enable CHECK8 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 6. "RES1OVF7EN,Enable CHECK7 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 5. "RES1OVF6EN,Enable CHECK6 RES1OVF as a source for CHECKINT." "0,1" newline bitfld.long 0x0 4. "RES1OVF5EN,Enable CHECK5 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 3. "RES1OVF4EN,Enable CHECK4 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 2. "RES1OVF3EN,Enable CHECK3 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 1. "RES1OVF2EN,Enable CHECK2 RES1OVF as a source for CHECKINT." "0,1" bitfld.long 0x0 0. "RES1OVF1EN,Enable CHECK1 RES1OVF as a source for CHECKINT." "0,1" line.long 0x4 "ADC_SAFETY_AGGR_CHECKINTSEL2,Checker Interrupt Source Select Register 2" bitfld.long 0x4 11. "RES2OVF12EN,Enable CHECK12 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 10. "RES2OVF11EN,Enable CHECK11 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 9. "RES2OVF10EN,Enable CHECK10 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 8. "RES2OVF9EN,Enable CHECK9 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 7. "RES2OVF8EN,Enable CHECK8 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 6. "RES2OVF7EN,Enable CHECK7 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 5. "RES2OVF6EN,Enable CHECK6 RES2OVF as a source for CHECKINT." "0,1" newline bitfld.long 0x4 4. "RES2OVF5EN,Enable CHECK5 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 3. "RES2OVF4EN,Enable CHECK4 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 2. "RES2OVF3EN,Enable CHECK3 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 1. "RES2OVF2EN,Enable CHECK2 RES2OVF as a source for CHECKINT." "0,1" bitfld.long 0x4 0. "RES2OVF1EN,Enable CHECK1 RES2OVF as a source for CHECKINT." "0,1" line.long 0x8 "ADC_SAFETY_AGGR_CHECKINTSEL3,Checker Interrupt Source Select Register 3" bitfld.long 0x8 11. "OOT12EN,Enable CHECK12 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 10. "OOT11EN,Enable CHECK11 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 9. "OOT10EN,Enable CHECK10 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 8. "OOT9EN,Enable CHECK9 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 7. "OOT8EN,Enable CHECK8 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 6. "OOT7EN,Enable CHECK7 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 5. "OOT6EN,Enable CHECK6 OOT as a source for CHECKINT." "0,1" newline bitfld.long 0x8 4. "OOT5EN,Enable CHECK5 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 3. "OOT4EN,Enable CHECK4 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 2. "OOT3EN,Enable CHECK3 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 1. "OOT2EN,Enable CHECK2 OOT as a source for CHECKINT." "0,1" bitfld.long 0x8 0. "OOT1EN,Enable CHECK1 OOT as a source for CHECKINT." "0,1" group.long 0x30++0xB line.long 0x0 "ADC_SAFETY_AGGR_CHECKEVT1SEL1,Checker X-Bar EVT1 Source Select Register 1" bitfld.long 0x0 11. "RES1OVF12EN,Enable CHECK12 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 10. "RES1OVF11EN,Enable CHECK11 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 9. "RES1OVF10EN,Enable CHECK10 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 8. "RES1OVF9EN,Enable CHECK9 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 7. "RES1OVF8EN,Enable CHECK8 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 6. "RES1OVF7EN,Enable CHECK7 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 5. "RES1OVF6EN,Enable CHECK6 RES1OVF as a source for CHECKEVT1." "0,1" newline bitfld.long 0x0 4. "RES1OVF5EN,Enable CHECK5 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 3. "RES1OVF4EN,Enable CHECK4 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 2. "RES1OVF3EN,Enable CHECK3 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 1. "RES1OVF2EN,Enable CHECK2 RES1OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x0 0. "RES1OVF1EN,Enable CHECK1 RES1OVF as a source for CHECKEVT1." "0,1" line.long 0x4 "ADC_SAFETY_AGGR_CHECKEVT1SEL2,Checker X-Bar EVT1 Source Select Register 2" bitfld.long 0x4 11. "RES2OVF12EN,Enable CHECK12 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 10. "RES2OVF11EN,Enable CHECK11 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 9. "RES2OVF10EN,Enable CHECK10 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 8. "RES2OVF9EN,Enable CHECK9 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 7. "RES2OVF8EN,Enable CHECK8 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 6. "RES2OVF7EN,Enable CHECK7 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 5. "RES2OVF6EN,Enable CHECK6 RES2OVF as a source for CHECKEVT1." "0,1" newline bitfld.long 0x4 4. "RES2OVF5EN,Enable CHECK5 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 3. "RES2OVF4EN,Enable CHECK4 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 2. "RES2OVF3EN,Enable CHECK3 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 1. "RES2OVF2EN,Enable CHECK2 RES2OVF as a source for CHECKEVT1." "0,1" bitfld.long 0x4 0. "RES2OVF1EN,Enable CHECK1 RES2OVF as a source for CHECKEVT1." "0,1" line.long 0x8 "ADC_SAFETY_AGGR_CHECKEVT1SEL3,Checker X-Bar EVT1 Source Select Register 3" bitfld.long 0x8 11. "OOT12EN,Enable CHECK12 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 10. "OOT11EN,Enable CHECK11 OOTas a source for CHECKEVT1." "0,1" bitfld.long 0x8 9. "OOT10EN,Enable CHECK10 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 8. "OOT9EN,Enable CHECK9 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 7. "OOT8EN,Enable CHECK8 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 6. "OOT7EN,Enable CHECK7 OOTas a source for CHECKEVT1." "0,1" bitfld.long 0x8 5. "OOT6EN,Enable CHECK6 OOT as a source for CHECKEVT1." "0,1" newline bitfld.long 0x8 4. "OOT5EN,Enable CHECK5 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 3. "OOT4EN,Enable CHECK4 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 2. "OOT3EN,Enable CHECK3 OOTas a source for CHECKEVT1." "0,1" bitfld.long 0x8 1. "OOT2EN,Enable CHECK2 OOT as a source for CHECKEVT1." "0,1" bitfld.long 0x8 0. "OOT1EN,Enable CHECK1 OOT as a source for CHECKEVT1." "0,1" group.long 0x40++0xB line.long 0x0 "ADC_SAFETY_AGGR_CHECKEVT2SEL1,Checker X-Bar EVT2 Source Select Register 1" bitfld.long 0x0 11. "RES1OVF12EN,Enable CHECK12 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 10. "RES1OVF11EN,Enable CHECK11 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 9. "RES1OVF10EN,Enable CHECK10 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 8. "RES1OVF9EN,Enable CHECK9 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 7. "RES1OVF8EN,Enable CHECK8 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 6. "RES1OVF7EN,Enable CHECK7 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 5. "RES1OVF6EN,Enable CHECK6 RES1OVF as a source for CHECKEVT2." "0,1" newline bitfld.long 0x0 4. "RES1OVF5EN,Enable CHECK5 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 3. "RES1OVF4EN,Enable CHECK4 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 2. "RES1OVF3EN,Enable CHECK3 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 1. "RES1OVF2EN,Enable CHECK2 RES1OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x0 0. "RES1OVF1EN,Enable CHECK1 RES1OVF as a source for CHECKEVT2." "0,1" line.long 0x4 "ADC_SAFETY_AGGR_CHECKEVT2SEL2,Checker X-Bar EVT2 Source Select Register 2" bitfld.long 0x4 11. "RES2OVF12EN,Enable CHECK12 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 10. "RES2OVF11EN,Enable CHECK11 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 9. "RES2OVF10EN,Enable CHECK10 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 8. "RES2OVF9EN,Enable CHECK9 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 7. "RES2OVF8EN,Enable CHECK8 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 6. "RES2OVF7EN,Enable CHECK7 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 5. "RES2OVF6EN,Enable CHECK6 RES2OVF as a source for CHECKEVT2." "0,1" newline bitfld.long 0x4 4. "RES2OVF5EN,Enable CHECK5 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 3. "RES2OVF4EN,Enable CHECK4 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 2. "RES2OVF3EN,Enable CHECK3 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 1. "RES2OVF2EN,Enable CHECK2 RES2OVF as a source for CHECKEVT2." "0,1" bitfld.long 0x4 0. "RES2OVF1EN,Enable CHECK1 RES2OVF as a source for CHECKEVT2." "0,1" line.long 0x8 "ADC_SAFETY_AGGR_CHECKEVT2SEL3,Checker X-Bar EVT2 Source Select Register 3" bitfld.long 0x8 11. "OOT12EN,Enable CHECK12 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 10. "OOT11EN,Enable CHECK11 OOTas a source for CHECKEVT2." "0,1" bitfld.long 0x8 9. "OOT10EN,Enable CHECK10 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 8. "OOT9EN,Enable CHECK9 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 7. "OOT8EN,Enable CHECK8 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 6. "OOT7EN,Enable CHECK7 OOTas a source for CHECKEVT2." "0,1" bitfld.long 0x8 5. "OOT6EN,Enable CHECK6 OOT as a source for CHECKEVT2." "0,1" newline bitfld.long 0x8 4. "OOT5EN,Enable CHECK5 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 3. "OOT4EN,Enable CHECK4 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 2. "OOT3EN,Enable CHECK3 OOTas a source for CHECKEVT2." "0,1" bitfld.long 0x8 1. "OOT2EN,Enable CHECK2 OOT as a source for CHECKEVT2." "0,1" bitfld.long 0x8 0. "OOT1EN,Enable CHECK1 OOT as a source for CHECKEVT2." "0,1" group.long 0x50++0xB line.long 0x0 "ADC_SAFETY_AGGR_CHECKEVT3SEL1,Checker X-Bar EVT3 Source Select Register 1" bitfld.long 0x0 11. "RES1OVF12EN,Enable CHECK12 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 10. "RES1OVF11EN,Enable CHECK11 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 9. "RES1OVF10EN,Enable CHECK10 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 8. "RES1OVF9EN,Enable CHECK9 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 7. "RES1OVF8EN,Enable CHECK8 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 6. "RES1OVF7EN,Enable CHECK7 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 5. "RES1OVF6EN,Enable CHECK6 RES1OVF as a source for CHECKEVT3." "0,1" newline bitfld.long 0x0 4. "RES1OVF5EN,Enable CHECK5 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 3. "RES1OVF4EN,Enable CHECK4 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 2. "RES1OVF3EN,Enable CHECK3 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 1. "RES1OVF2EN,Enable CHECK2 RES1OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x0 0. "RES1OVF1EN,Enable CHECK1 RES1OVF as a source for CHECKEVT3." "0,1" line.long 0x4 "ADC_SAFETY_AGGR_CHECKEVT3SEL2,Checker X-Bar EVT3 Source Select Register 2" bitfld.long 0x4 11. "RES2OVF12EN,Enable CHECK12 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 10. "RES2OVF11EN,Enable CHECK11 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 9. "RES2OVF10EN,Enable CHECK10 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 8. "RES2OVF9EN,Enable CHECK9 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 7. "RES2OVF8EN,Enable CHECK8 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 6. "RES2OVF7EN,Enable CHECK7 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 5. "RES2OVF6EN,Enable CHECK6 RES2OVF as a source for CHECKEVT3." "0,1" newline bitfld.long 0x4 4. "RES2OVF5EN,Enable CHECK5 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 3. "RES2OVF4EN,Enable CHECK4 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 2. "RES2OVF3EN,Enable CHECK3 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 1. "RES2OVF2EN,Enable CHECK2 RES2OVF as a source for CHECKEVT3." "0,1" bitfld.long 0x4 0. "RES2OVF1EN,Enable CHECK1 RES2OVF as a source for CHECKEVT3." "0,1" line.long 0x8 "ADC_SAFETY_AGGR_CHECKEVT3SEL3,Checker X-Bar EVT3 Source Select Register 3" bitfld.long 0x8 11. "OOT12EN,Enable CHECK12 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 10. "OOT11EN,Enable CHECK11 OOTas a source for CHECKEVT3." "0,1" bitfld.long 0x8 9. "OOT10EN,Enable CHECK10 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 8. "OOT9EN,Enable CHECK9 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 7. "OOT8EN,Enable CHECK8 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 6. "OOT7EN,Enable CHECK7 OOTas a source for CHECKEVT3." "0,1" bitfld.long 0x8 5. "OOT6EN,Enable CHECK6 OOT as a source for CHECKEVT3." "0,1" newline bitfld.long 0x8 4. "OOT5EN,Enable CHECK5 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 3. "OOT4EN,Enable CHECK4 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 2. "OOT3EN,Enable CHECK3 OOTas a source for CHECKEVT3." "0,1" bitfld.long 0x8 1. "OOT2EN,Enable CHECK2 OOT as a source for CHECKEVT3." "0,1" bitfld.long 0x8 0. "OOT1EN,Enable CHECK1 OOT as a source for CHECKEVT3." "0,1" group.long 0x60++0xB line.long 0x0 "ADC_SAFETY_AGGR_CHECKEVT4SEL1,Checker X-Bar EVT4 Source Select Register 1" bitfld.long 0x0 11. "RES1OVF12EN,Enable CHECK12 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 10. "RES1OVF11EN,Enable CHECK11 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 9. "RES1OVF10EN,Enable CHECK10 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 8. "RES1OVF9EN,Enable CHECK9 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 7. "RES1OVF8EN,Enable CHECK8 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 6. "RES1OVF7EN,Enable CHECK7 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 5. "RES1OVF6EN,Enable CHECK6 RES1OVF as a source for CHECKEVT4." "0,1" newline bitfld.long 0x0 4. "RES1OVF5EN,Enable CHECK5 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 3. "RES1OVF4EN,Enable CHECK4 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 2. "RES1OVF3EN,Enable CHECK3 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 1. "RES1OVF2EN,Enable CHECK2 RES1OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x0 0. "RES1OVF1EN,Enable CHECK1 RES1OVF as a source for CHECKEVT4." "0,1" line.long 0x4 "ADC_SAFETY_AGGR_CHECKEVT4SEL2,Checker X-Bar EVT4 Source Select Register 2" bitfld.long 0x4 11. "RES2OVF12EN,Enable CHECK12 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 10. "RES2OVF11EN,Enable CHECK11 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 9. "RES2OVF10EN,Enable CHECK10 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 8. "RES2OVF9EN,Enable CHECK9 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 7. "RES2OVF8EN,Enable CHECK8 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 6. "RES2OVF7EN,Enable CHECK7 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 5. "RES2OVF6EN,Enable CHECK6 RES2OVF as a source for CHECKEVT4." "0,1" newline bitfld.long 0x4 4. "RES2OVF5EN,Enable CHECK5 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 3. "RES2OVF4EN,Enable CHECK4 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 2. "RES2OVF3EN,Enable CHECK3 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 1. "RES2OVF2EN,Enable CHECK2 RES2OVF as a source for CHECKEVT4." "0,1" bitfld.long 0x4 0. "RES2OVF1EN,Enable CHECK1 RES2OVF as a source for CHECKEVT4." "0,1" line.long 0x8 "ADC_SAFETY_AGGR_CHECKEVT4SEL3,Checker X-Bar EVT4 Source Select Register 3" bitfld.long 0x8 11. "OOT12EN,Enable CHECK12 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 10. "OOT11EN,Enable CHECK11 OOTas a source for CHECKEVT4." "0,1" bitfld.long 0x8 9. "OOT10EN,Enable CHECK10 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 8. "OOT9EN,Enable CHECK9 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 7. "OOT8EN,Enable CHECK8 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 6. "OOT7EN,Enable CHECK7 OOTas a source for CHECKEVT4." "0,1" bitfld.long 0x8 5. "OOT6EN,Enable CHECK6 OOT as a source for CHECKEVT4." "0,1" newline bitfld.long 0x8 4. "OOT5EN,Enable CHECK5 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 3. "OOT4EN,Enable CHECK4 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 2. "OOT3EN,Enable CHECK3 OOTas a source for CHECKEVT4." "0,1" bitfld.long 0x8 1. "OOT2EN,Enable CHECK2 OOT as a source for CHECKEVT4." "0,1" bitfld.long 0x8 0. "OOT1EN,Enable CHECK1 OOT as a source for CHECKEVT4." "0,1" tree.end tree.end tree "ADCSAFE_01_ADC_SAFETY" base ad:0x502CB800 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_02_ADC_SAFETY" base ad:0x502CBC00 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_03_ADC_SAFETY" base ad:0x502CC000 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_04_ADC_SAFETY" base ad:0x502CC400 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_05_ADC_SAFETY" base ad:0x502CC800 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_06_ADC_SAFETY" base ad:0x502CCC00 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_07_ADC_SAFETY" base ad:0x502CD000 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_08_ADC_SAFETY" base ad:0x502CD400 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_09_ADC_SAFETY" base ad:0x502CD800 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_10_ADC_SAFETY" base ad:0x502CDC00 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree "ADCSAFE_11_ADC_SAFETY" base ad:0x502CE000 group.word 0x0++0x1 line.word 0x0 "ADC_SAFETY_CHECKCONFIG,ADC Check Configuration Register." bitfld.word 0x0 15. "CHKEN,Result Safe Check Module enable" "0,1" bitfld.word 0x0 6. "SWSYNC,Result Safe Check SW Force Sync." "0,1" hexmask.word.byte 0x0 0.--4. 1. "SYNCINSEL,Result Safe Check Sync. In sel" rgroup.word 0x4++0x1 line.word 0x0 "ADC_SAFETY_CHECKSTATUS,ADC Check Status Register." bitfld.word 0x0 2. "OOT,Set when the difference between CHECKRESULT1 and CHECKRESULT2 is greater than TOLERANCE after both results have arrived. When set further results will not be captured into the safety checker module CHECKRESULT1 or CHECKRESULT2 registers and.." "0,1" bitfld.word 0x0 1. "RES2READY,Result Safe Check Result 2 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" bitfld.word 0x0 0. "RES1READY,Result Safe Check Result 1 arrived. Cleared automatically when both results have arrived and the comparison occurs. Can also be cleared by issuing a software sync to the tile via the CHECKCONFIG.SWSYNC field." "0,1" group.word 0x8++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL1,ADC Check 1 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 1 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 1 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-45 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-45,?,?,7: Reserved" group.word 0xC++0x1 line.word 0x0 "ADC_SAFETY_ADCRESSEL2,ADC Check 2 Select Register." hexmask.word.byte 0x0 4.--9. 1. "ADCRESULTSEL,ADC Result Safety Checker Result Select 2 0 = ADCRESULT0 1 = ADCRESULT1 2= ADCRESULT2 3 = ADCRESULT3 4 = ADCRESULT4 5 = ADCRESULT5 6 = ADCRESULT6 7 = ADCRESULT7 8 = ADCRESULT8 9 = ADCRESULT9 10 = ADCRESULT10 11 = ADCRESULT11 12 =.." bitfld.word 0x0 0.--2. "ADCSEL,ADC Result Safety Checker ADC Select 2 0 = ADC-0 1 = ADC-1 2 = ADC-2 3 = ADC-3 4 = ADC-4 5 - 7 = Reserved" "0: ADC-0,1: ADC-1,2: ADC-2,3: ADC-3,4: ADC-4 5,?,?,7: Reserved" group.long 0x10++0x3 line.long 0x0 "ADC_SAFETY_TOLERANCE,ADC Check Tolerance Register." hexmask.long.tbyte 0x0 0.--23. 1. "TOLERANCE,Tolerance for the difference between CHECKRESULT1 and CHECKRESULT2. If the difference is greater than [but not equal to] the tolerance an out-of-tolerance event will be generated indicated the compared ADC results are not within expected.." rgroup.long 0x18++0x7 line.long 0x0 "ADC_SAFETY_CHECKRESULT1,ADC Check Captured Result 1 ." hexmask.long.tbyte 0x0 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES1OVF flag in CHECKSTATUS will be set. This.." line.long 0x4 "ADC_SAFETY_CHECKRESULT2,ADC Check Captured Result 2 ." hexmask.long.tbyte 0x4 0.--23. 1. "RESULT,ADC Result Safety Checker Captured Result Result that was captured In the case that multiple results arrive for one selected result before one result arrives for the other result for comparison the RES2OVF flag in CHECKSTATUS will be set. This.." tree.end tree.end tree "CMPSS" base ad:0x0 tree "CMPSSA" tree "CMPSSA0" base ad:0x50200000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA1" base ad:0x50201000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA2" base ad:0x50202000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA3" base ad:0x50203000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA4" base ad:0x50204000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA5" base ad:0x50205000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA6" base ad:0x50206000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA7" base ad:0x50207000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA8" base ad:0x50208000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSA9" base ad:0x50209000 group.word 0x0++0x1 line.word 0x0 "CMPSSA_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage [default]1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage [default]1 negative mux selects INL_3p3v" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSA_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSA_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSA_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM0BLANK 1 EPWM1BLANK 2 EPWM2BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSA_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0 : EPWM0.DEACTIVE 1 : EPWM1.DEACTIVE 2 : EPWM2.DEACTIVE 3 : EPWM3.DEACTIVE . . 31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSA_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSA_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSA_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSA_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSA_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSA_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSA_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSA_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSA_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSA_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSA_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSA_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSA_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSA_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSA_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSA_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSA_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSA_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSA_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree.end tree "CMPSSB" tree "CMPSSB0" base ad:0x50220000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB1" base ad:0x50221000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB2" base ad:0x50222000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB3" base ad:0x50223000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB4" base ad:0x50224000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB5" base ad:0x50225000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB6" base ad:0x50226000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB7" base ad:0x50227000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB8" base ad:0x50228000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree "CMPSSB9" base ad:0x50229000 group.word 0x0++0x1 line.word 0x0 "CMPSSB_COMPCTL,CMPSS Comparator Control Register." bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED_3,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" newline bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 0. "RESERVED_1,Reserved for CMPSSB" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CMPSSB_COMPSTS,CMPSS Comparator Status Register." bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" newline bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CMPSSB_COMPSTSCLR,CMPSS Comparator Status Clear Register." bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" newline bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CMPSSB_COMPDACCTL,CMPSS DAC Control Register." bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." newline bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage [default]1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CMPSSB_COMPDACCTL2,CMPSS DAC Control Register 2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1:Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1:Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM0.DEACTIVE 0x1 : EPWM1.DEACTIVE 0x2 : EPWM2.DEACTIVE 0x3 : EPWM3.DEACTIVE . . 0x31 : EPWM31.DEACTIVE" newline bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CMPSSB_DACHVALS,CMPSS High DAC Value Shadow Register." hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CMPSSB_DACHVALA,CMPSS High DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CMPSSB_RAMPMAXREFA,CMPSS Ramp Max Reference Active Register." hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CMPSSB_RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CMPSSB_RAMPDECVALA,CMPSS Ramp Decrement Value Active Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CMPSSB_RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register." hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CMPSSB_RAMPSTS,CMPSS Ramp Status Register." hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CMPSSB_DACLVALS,CMPSS Low DAC Value Shadow Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CMPSSB_DACLVALA,CMPSS Low DAC Value Active Register." hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CMPSSB_RAMPDLYA,CMPSS Ramp Delay Active Register." hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CMPSSB_RAMPDLYS,CMPSS Ramp Delay Shadow Register." hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CMPSSB_CTRIPLFILCTL,CTRIPL Filter Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CMPSSB_CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register." hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CMPSSB_CTRIPHFILCTL,CTRIPH Filter Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CMPSSB_CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register." hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CMPSSB_COMPLOCK,CMPSS Lock Register." bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CMPSSB_DACHVALS2,CMPSS High DAC Value Shadow Register 2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CMPSSB_DACLVALS2,CMPSS Low DAC Value Shadow Register 2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CMPSSB_CONFIG1,CMPSS Config1 Register." hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,CompL HysteresisCOMPLHYS[3] : reservedCOMPLHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH HysteresisCOMPHHYS[3] : reservedCOMPHHYS[2] : Controls which comparator output value hysteresis is applied to. 1'b0 : Hysteresis is applied when the comparator output is 1'b11'b1 : Hysteresis is applied when the comparator output is.." tree.end tree.end tree.end tree "CONTROLSS" base ad:0x0 tree "CONTROLSS_DMAXBAR" base ad:0x502D6000 group.long 0x100++0x1F line.long 0x0 "CONTROLSS_DMAXBAR0_GSEL,DMA XBAR0 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR0_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR0_G0,DMA XBAR0 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR0_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR0_G1,DMA XBAR0 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR0_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR0_G2,DMA XBAR0 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR0_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR0_G3,DMA XBAR0 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR0_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR0_G4,DMA XBAR0 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR0_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR0_G5,DMA XBAR0 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR0_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR0_G6,DMA XBAR0 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR0_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x140++0x1F line.long 0x0 "CONTROLSS_DMAXBAR1_GSEL,DMA XBAR1 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR1_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR1_G0,DMA XBAR1 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR1_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR1_G1,DMA XBAR1 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR1_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR1_G2,DMA XBAR1 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR1_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR1_G3,DMA XBAR1 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR1_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR1_G4,DMA XBAR1 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR1_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR1_G5,DMA XBAR1 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR1_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR1_G6,DMA XBAR1 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR1_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x180++0x1F line.long 0x0 "CONTROLSS_DMAXBAR2_GSEL,DMA XBAR2 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR2_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR2_G0,DMA XBAR2 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR2_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR2_G1,DMA XBAR2 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR2_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR2_G2,DMA XBAR2 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR2_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR2_G3,DMA XBAR2 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR2_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR2_G4,DMA XBAR2 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR2_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR2_G5,DMA XBAR2 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR2_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR2_G6,DMA XBAR2 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR2_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x1C0++0x1F line.long 0x0 "CONTROLSS_DMAXBAR3_GSEL,DMA XBAR3 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR3_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR3_G0,DMA XBAR3 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR3_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR3_G1,DMA XBAR3 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR3_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR3_G2,DMA XBAR3 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR3_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR3_G3,DMA XBAR3 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR3_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR3_G4,DMA XBAR3 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR3_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR3_G5,DMA XBAR3 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR3_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR3_G6,DMA XBAR3 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR3_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x200++0x1F line.long 0x0 "CONTROLSS_DMAXBAR4_GSEL,DMA XBAR4 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR4_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR4_G0,DMA XBAR4 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR4_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR4_G1,DMA XBAR4 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR4_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR4_G2,DMA XBAR4 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR4_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR4_G3,DMA XBAR4 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR4_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR4_G4,DMA XBAR4 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR4_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR4_G5,DMA XBAR4 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR4_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR4_G6,DMA XBAR4 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR4_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x240++0x1F line.long 0x0 "CONTROLSS_DMAXBAR5_GSEL,DMA XBAR5 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR5_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR5_G0,DMA XBAR5 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR5_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR5_G1,DMA XBAR5 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR5_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR5_G2,DMA XBAR5 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR5_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR5_G3,DMA XBAR5 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR5_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR5_G4,DMA XBAR5 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR5_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR5_G5,DMA XBAR5 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR5_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR5_G6,DMA XBAR5 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR5_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x280++0x1F line.long 0x0 "CONTROLSS_DMAXBAR6_GSEL,DMA XBAR6 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR6_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR6_G0,DMA XBAR6 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR6_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR6_G1,DMA XBAR6 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR6_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR6_G2,DMA XBAR6 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR6_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR6_G3,DMA XBAR6 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR6_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR6_G4,DMA XBAR6 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR6_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR6_G5,DMA XBAR6 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR6_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR6_G6,DMA XBAR6 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR6_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x2C0++0x1F line.long 0x0 "CONTROLSS_DMAXBAR7_GSEL,DMA XBAR7 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR7_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR7_G0,DMA XBAR7 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR7_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR7_G1,DMA XBAR7 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR7_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR7_G2,DMA XBAR7 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR7_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR7_G3,DMA XBAR7 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR7_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR7_G4,DMA XBAR7 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR7_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR7_G5,DMA XBAR7 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR7_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR7_G6,DMA XBAR7 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR7_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x300++0x1F line.long 0x0 "CONTROLSS_DMAXBAR8_GSEL,DMA XBAR8 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR8_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR8_G0,DMA XBAR8 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR8_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR8_G1,DMA XBAR8 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR8_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR8_G2,DMA XBAR8 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR8_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR8_G3,DMA XBAR8 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR8_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR8_G4,DMA XBAR8 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR8_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR8_G5,DMA XBAR8 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR8_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR8_G6,DMA XBAR8 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR8_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x340++0x1F line.long 0x0 "CONTROLSS_DMAXBAR9_GSEL,DMA XBAR9 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR9_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR9_G0,DMA XBAR9 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR9_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR9_G1,DMA XBAR9 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR9_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR9_G2,DMA XBAR9 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR9_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR9_G3,DMA XBAR9 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR9_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR9_G4,DMA XBAR9 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR9_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR9_G5,DMA XBAR9 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR9_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR9_G6,DMA XBAR9 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR9_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x380++0x1F line.long 0x0 "CONTROLSS_DMAXBAR10_GSEL,DMA XBAR10 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR10_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR10_G0,DMA XBAR10 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR10_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR10_G1,DMA XBAR10 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR10_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR10_G2,DMA XBAR10 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR10_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR10_G3,DMA XBAR10 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR10_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR10_G4,DMA XBAR10 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR10_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR10_G5,DMA XBAR10 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR10_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR10_G6,DMA XBAR10 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR10_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x3C0++0x1F line.long 0x0 "CONTROLSS_DMAXBAR11_GSEL,DMA XBAR11 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR11_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR11_G0,DMA XBAR11 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR11_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR11_G1,DMA XBAR11 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR11_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR11_G2,DMA XBAR11 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR11_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR11_G3,DMA XBAR11 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR11_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR11_G4,DMA XBAR11 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR11_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR11_G5,DMA XBAR11 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR11_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR11_G6,DMA XBAR11 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR11_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x400++0x1F line.long 0x0 "CONTROLSS_DMAXBAR12_GSEL,DMA XBAR12 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR12_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR12_G0,DMA XBAR12 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR12_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR12_G1,DMA XBAR12 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR12_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR12_G2,DMA XBAR12 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR12_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR12_G3,DMA XBAR12 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR12_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR12_G4,DMA XBAR12 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR12_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR12_G5,DMA XBAR12 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR12_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR12_G6,DMA XBAR12 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR12_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x440++0x1F line.long 0x0 "CONTROLSS_DMAXBAR13_GSEL,DMA XBAR13 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR13_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR13_G0,DMA XBAR13 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR13_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR13_G1,DMA XBAR13 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR13_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR13_G2,DMA XBAR13 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR13_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR13_G3,DMA XBAR13 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR13_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR13_G4,DMA XBAR13 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR13_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR13_G5,DMA XBAR13 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR13_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR13_G6,DMA XBAR13 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR13_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x480++0x1F line.long 0x0 "CONTROLSS_DMAXBAR14_GSEL,DMA XBAR14 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR14_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR14_G0,DMA XBAR14 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR14_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR14_G1,DMA XBAR14 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR14_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR14_G2,DMA XBAR14 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR14_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR14_G3,DMA XBAR14 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR14_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR14_G4,DMA XBAR14 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR14_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR14_G5,DMA XBAR14 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR14_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR14_G6,DMA XBAR14 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR14_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" group.long 0x4C0++0x1F line.long 0x0 "CONTROLSS_DMAXBAR15_GSEL,DMA XBAR15 Input Select." bitfld.long 0x0 0.--2. "DMAXBAR15_GSEL_GSEL,Select input source:0:G0 selected..6:G6 selected" "0: G0 selected,?,?,?,?,?,6: G6 selected,?" line.long 0x4 "CONTROLSS_DMAXBAR15_G0,DMA XBAR15 Input Select." hexmask.long.byte 0x4 0.--4. 1. "DMAXBAR15_G0_SEL,EPWM SOCA to corresponding XBAR0:PWM0.SOCA is selected 1:PWM1.SOCA is selected . . 31:PWM31.SOCA is selected" line.long 0x8 "CONTROLSS_DMAXBAR15_G1,DMA XBAR15 Input Select." hexmask.long.byte 0x8 0.--4. 1. "DMAXBAR15_G1_SEL,EPWM SOCB to corresponding XBAR0:PWM0.SOCB is selected 1:PWM1.SOCB is selected . . 31:PWM31.SOCB is selected" line.long 0xC "CONTROLSS_DMAXBAR15_G2,DMA XBAR15 Input Select." hexmask.long.byte 0xC 0.--4. 1. "DMAXBAR15_G2_SEL,ADC DMA requests to corresponding.." line.long 0x10 "CONTROLSS_DMAXBAR15_G3,DMA XBAR15 Input Select." hexmask.long.byte 0x10 0.--3. 1. "DMAXBAR15_G3_SEL,FSI DMA requests to corresponding XBAR0:FSIRX0.RX_DMA_EVT1; FSIRX0_RX_data_tag_match2:FSIRX0_RX_ping_tag_match3:FSIRX1.RX_DMA_EVT4; FSIRX1_RX_data_tag_match5:FSIRX1_RX_ping_tag_match6:FSIRX2.RX_DMA_EVT7;.." line.long 0x14 "CONTROLSS_DMAXBAR15_G4,DMA XBAR15 Input Select." bitfld.long 0x14 0.--2. "DMAXBAR15_G4_SEL,SDFM DMA requests to corresponding XBAR0:SD0.FILT1.DRINT1:SD0.FILT2.DRINT2:SD0.FILT3.DRINT3:SD0.FILT4.DRINT4:SD1.FILT1.DRINT5:SD1.FILT2.DRINT6:SD1.FILT3.DRINT7:SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_DMAXBAR15_G5,DMA XBAR15 Input Select." hexmask.long.byte 0x18 0.--3. 1. "DMAXBAR15_G5_SEL,ECAP DMA requests to corresponding XBAR0:ECAP0.DMA_INT1:ECAP1.DMA_INT2:ECAP2.DMA_INT3:ECAP3.DMA_INT4:ECAP4.DMA_INT5:ECAP5.DMA_INT6:ECAP6.DMA_INT7:ECAP7.DMA_INT8:ECAP8.DMA_INT9:ECAP9.DMA_INT10:ECAP10.DMA_INT.." line.long 0x1C "CONTROLSS_DMAXBAR15_G6,DMA XBAR15 Input Select." hexmask.long.byte 0x1C 0.--3. 1. "DMAXBAR15_G6_SEL,ADC_R DMA requests to corresponding XBAR0:ADCR0.INT11:ADCR0.INT22:ADCR0.INT33:ADCR0.INT44:ADCR0.EVTINT5:ADCR1.INT16:ADCR1.INT27:ADCR1.INT38:ADCR1.INT49:ADCR1.EVTINT" tree.end tree "CONTROLSS_GLOBAL_CTRL" base ad:0x502F0000 group.long 0x4++0x7 line.long 0x0 "CONTROLSS_CTRL_EPWM_STATICXBAR_SEL0,Static crossbar for epwm select." bitfld.long 0x0 30.--31. "EPWM_STATICXBAR_SEL0_EPWM15,EPWM15 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 28.--29. "EPWM_STATICXBAR_SEL0_EPWM14,EPWM14 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 26.--27. "EPWM_STATICXBAR_SEL0_EPWM13,EPWM13 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 24.--25. "EPWM_STATICXBAR_SEL0_EPWM12,EPWM12 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 22.--23. "EPWM_STATICXBAR_SEL0_EPWM11,EPWM11 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 20.--21. "EPWM_STATICXBAR_SEL0_EPWM10,EPWM10 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 18.--19. "EPWM_STATICXBAR_SEL0_EPWM9,EPWM9 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 16.--17. "EPWM_STATICXBAR_SEL0_EPWM8,EPWM8 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 14.--15. "EPWM_STATICXBAR_SEL0_EPWM7,EPWM7 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 12.--13. "EPWM_STATICXBAR_SEL0_EPWM6,EPWM6 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 10.--11. "EPWM_STATICXBAR_SEL0_EPWM5,EPWM5 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "EPWM_STATICXBAR_SEL0_EPWM4,EPWM4 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 6.--7. "EPWM_STATICXBAR_SEL0_EPWM3,EPWM3 access from PCR grouping. Write the following value to access groups - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "EPWM_STATICXBAR_SEL0_EPWM2,EPWM2 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 2.--3. "EPWM_STATICXBAR_SEL0_EPWM1,EPWM1 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EPWM_STATICXBAR_SEL0_EPWM0,EPWM0 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" line.long 0x4 "CONTROLSS_CTRL_EPWM_STATICXBAR_SEL1,Static crossbar for epwm select." bitfld.long 0x4 30.--31. "EPWM_STATICXBAR_SEL1_EPWM31,EPWM31 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 28.--29. "EPWM_STATICXBAR_SEL1_EPWM30,EPWM30 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 26.--27. "EPWM_STATICXBAR_SEL1_EPWM29,EPWM29 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 24.--25. "EPWM_STATICXBAR_SEL1_EPWM28,EPWM28 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 22.--23. "EPWM_STATICXBAR_SEL1_EPWM27,EPWM27 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 20.--21. "EPWM_STATICXBAR_SEL1_EPWM26,EPWM26 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 18.--19. "EPWM_STATICXBAR_SEL1_EPWM25,EPWM25 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 16.--17. "EPWM_STATICXBAR_SEL1_EPWM24,EPWM24 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 14.--15. "EPWM_STATICXBAR_SEL1_EPWM23,EPWM23 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 12.--13. "EPWM_STATICXBAR_SEL1_EPWM22,EPWM22 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 10.--11. "EPWM_STATICXBAR_SEL1_EPWM21,EPWM21 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 8.--9. "EPWM_STATICXBAR_SEL1_EPWM20,EPWM20 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 6.--7. "EPWM_STATICXBAR_SEL1_EPWM19,EPWM19 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 4.--5. "EPWM_STATICXBAR_SEL1_EPWM18,EPWM18 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 2.--3. "EPWM_STATICXBAR_SEL1_EPWM17,EPWM17 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" newline bitfld.long 0x4 0.--1. "EPWM_STATICXBAR_SEL1_EPWM16,EPWM16 access from PCR grouping. Write the following value to access groups - - 2'b00 = G0 2'b01 =G1 2'b10 =G2 2'b11 =G3" "0,1,2,3" group.long 0x10++0x3 line.long 0x0 "CONTROLSS_CTRL_EPWM_CLKSYNC,Epwm clock sync." hexmask.long 0x0 0.--31. 1. "EPWM_CLKSYNC_BIT,EPWM clock sync for each EPWM instance. Set the bit corresponding to the instance number to enable that EPWM instance. When set all enabled EPWM module clocks are started with the first rising edge of TBCLK aligned.Refer to TRM for more.." group.long 0x18++0x3 line.long 0x0 "CONTROLSS_CTRL_SDFM1_CLK0_SEL,Sdfm1 clock select." bitfld.long 0x0 0. "SDFM1_CLK0_SEL_SEL,SDFM1 clock CK0 selectWrite 1'b0: source is SDFM1 CK0 from PinmuxWrite 1'b1: source is SDFM0 CK0 from Pinmux" "0: source is SDFM1 CK0 from PinmuxWrite,1: source is SDFM0 CK0 from Pinmux" group.long 0x20++0x3 line.long 0x0 "CONTROLSS_CTRL_EMUSTOPN_MASK,Bit-mask for debug suspend cpu cores to EPWM." bitfld.long 0x0 3. "EMUSTOPN_MASK_CR5B1,Bit-mask for debug suspend cpu cores to EPWM1'b0 : R5FSS1_CORE1 enabled to control EMUSTOPn1'b1 : R5FSS1_CORE1 disabled to control EMUSTOPn" "0,1" newline bitfld.long 0x0 2. "EMUSTOPN_MASK_CR5A1,Bit-mask for debug suspend cpu cores to EPWM1'b0 : R5FSS1_CORE0 enabled to control EMUSTOPn1'b1 : R5FSS1_CORE0 disabled to control EMUSTOPn" "0,1" newline bitfld.long 0x0 1. "EMUSTOPN_MASK_CR5B0,Bit-mask for debug suspend cpu cores to EPWM1'b0 : R5FSS0_CORE1 enabled to control EMUSTOPn1'b1 : R5FSS0_CORE1 disabled to control EMUSTOPn" "0,1" newline bitfld.long 0x0 0. "EMUSTOPN_MASK_CR5A0,Bit-mask for debug suspend cpu cores to EPWM1'b0 : R5FSS0_CORE0 enabled to control EMUSTOPn1'b1 : R5FSS0_CORE0 disabled to control EMUSTOPn" "0,1" group.long 0x28++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_AQ_EN0,clb_aq_en0." hexmask.long 0x0 0.--31. 1. "CLB_AQ_EN0_ENABLE,Enable ICCS control to CLB_AQ signal of PWM[15:0]. Set Bitx to 1'b1 to enable it for PWMx. Here x varies from 0-15." group.long 0x30++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_AQ_EN1,clb_aq_en1." hexmask.long 0x0 0.--31. 1. "CLB_AQ_EN1_ENABLE,Enable ICCS control to CLB_AQ signal of PWM[31:16].Set Bitx to 1'b1 to enable it for PWMx. Here x varies from 16-31." group.long 0x38++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_DB_EN0,clb_db_en0." hexmask.long 0x0 0.--31. 1. "CLB_DB_EN0_ENABLE,Enable ICCS control to CLB_DB signal of PWM[15:0]. Set Bitx to 1'b1 to enable it for PWMx. Here x varies from 0-15." group.long 0x40++0x13 line.long 0x0 "CONTROLSS_CTRL_CLB_DB_EN1,clb_db_en1." hexmask.long 0x0 0.--31. 1. "CLB_DB_EN1_ENABLE,Enable ICCS control to CLB_DB signal of PWM[31:16].Set Bitx to 1'b1 to enable it for PWMx. Here x varies from 16-31." line.long 0x4 "CONTROLSS_CTRL_ADCSOCFRCGBSEL,ADC Global SoC Force select." hexmask.long.byte 0x4 0.--6. 1. "ADCSOCFRCGBSEL_ENABLE,ADCSOCFRCGBSEL has one bit for each ADCBIT FIELD Descriptionbitx ADCx Indicate if ADCx selected for global SW trigger 1'b0 : Not selected for Global SW Trigger 1'b1 :.." line.long 0x8 "CONTROLSS_CTRL_ADCSOCFRCGB,ADC Global SOC Force." hexmask.long.word 0x8 0.--15. 1. "ADCSOCFRCGB_TRIG,ADCSOCFRCGB has one bit for each SOC[Start of conversion]BIT FIELD Descriptionbitxx SOCxx Indicate if SOCxx selected for global SW trigger 1'b0 : Not selected for Global SW Trigger.." line.long 0xC "CONTROLSS_CTRL_ADC_EXTCH_DLY_SEL,Mux select to choose delay for adc_extchsel." bitfld.long 0xC 0. "ADC_EXTCH_DLY_SEL_SEL,MUX select to choose delayWrite 1'b0: 3 cycle delay[default]Write 1'b1: 6 cycle delay" "0: 3 cycle delay[default]Write,1: 6 cycle delay" line.long 0x10 "CONTROLSS_CTRL_XBAR_LOOPBACK_CTRL,Mux select to enable Loopback for corresponding outputXBAR." hexmask.long.word 0x10 0.--15. 1. "XBAR_LOOPBACK_CTRL_ENABLE,Mux select to enable Loopback for corresponding outputXBAR signal to the inputXBARWrite 1'b0: Loopback disabled [default]Write 1'b1: Loopback enable**Note: Each Mux select bit corresponds to the corresponding.." group.long 0x60++0x7 line.long 0x0 "CONTROLSS_CTRL_EPWM_SOCA_SEL,Select line to choose EPWM SOC A to EQEPx.SOCA and PWMBAR." hexmask.long 0x0 0.--31. 1. "EPWM_SOCA_SEL_SEL,MUX select to choose EPWM SOC A to EQEPx.SOCA and PWMBAR.Each bit in SOC_A_SEL corresponds to each.." line.long 0x4 "CONTROLSS_CTRL_EPWM_SOCB_SEL,Select line to choose EPWM SOC B to EQEPx.SOCB and PWMBAR." hexmask.long 0x4 0.--31. 1. "EPWM_SOCB_SEL_SEL,MUX select to choose EPWM SOC B to EQEPx.SOCB and PWMBAR.Each bit in SOC_B_SEL corresponds to each.." group.long 0x70++0x27 line.long 0x0 "CONTROLSS_CTRL_ADCEXTCHXBAR0_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x0 0.--3. 1. "ADCEXTCHXBAR0_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x4 "CONTROLSS_CTRL_ADCEXTCHXBAR1_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x4 0.--3. 1. "ADCEXTCHXBAR1_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x8 "CONTROLSS_CTRL_ADCEXTCHXBAR2_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x8 0.--3. 1. "ADCEXTCHXBAR2_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0xC "CONTROLSS_CTRL_ADCEXTCHXBAR3_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0xC 0.--3. 1. "ADCEXTCHXBAR3_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x10 "CONTROLSS_CTRL_ADCEXTCHXBAR4_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x10 0.--3. 1. "ADCEXTCHXBAR4_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x14 "CONTROLSS_CTRL_ADCEXTCHXBAR5_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x14 0.--3. 1. "ADCEXTCHXBAR5_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x18 "CONTROLSS_CTRL_ADCEXTCHXBAR6_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x18 0.--3. 1. "ADCEXTCHXBAR6_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x1C "CONTROLSS_CTRL_ADCEXTCHXBAR7_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x1C 0.--3. 1. "ADCEXTCHXBAR7_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x20 "CONTROLSS_CTRL_ADCEXTCHXBAR8_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x20 0.--3. 1. "ADCEXTCHXBAR8_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." line.long 0x24 "CONTROLSS_CTRL_ADCEXTCHXBAR9_G0_SEL,ADC EXTCH XBAR [x] Input Select." hexmask.long.byte 0x24 0.--3. 1. "ADCEXTCHXBAR9_G0_SEL_SEL,ADC EXTCH XBAR 0 Input Select4'b0000: ADC0EXTCHSEL_BIT04'b0001: ADC0EXTCHSEL_BIT14'b0010: ADC1EXTCHSEL_BIT04'b0011: ADC1EXTCHSEL_BIT14'b0100: ADC2EXTCHSEL_BIT04'b0101: ADC2EXTCHSEL_BIT14'b0110: ADC3EXTCHSEL_BIT04'b0111:.." group.long 0xB0++0x1F line.long 0x0 "CONTROLSS_CTRL_SDFM0_CLK0_OUT_SEL,SDFM0_CLK[x]_OUT Input Select." bitfld.long 0x0 0. "SDFM0_CLK0_OUT_SEL_SEL,SDFM0_CLK0_OUT Input selectWrite 1'b0: ECAP4_OUT [default]Write 1'b1: ECAP12_OUT" "0: ECAP4_OUT [default]Write,1: ECAP12_OUT" line.long 0x4 "CONTROLSS_CTRL_SDFM0_CLK1_OUT_SEL,SDFM0_CLK[x]_OUT Input Select." bitfld.long 0x4 0. "SDFM0_CLK1_OUT_SEL_SEL,SDFM0_CLK1_OUT Input selectWrite 1'b0: ECAP5_OUT [default]Write 1'b1: ECAP13_OUT" "0: ECAP5_OUT [default]Write,1: ECAP13_OUT" line.long 0x8 "CONTROLSS_CTRL_SDFM0_CLK2_OUT_SEL,SDFM0_CLK[x]_OUT Input Select." bitfld.long 0x8 0. "SDFM0_CLK2_OUT_SEL_SEL,SDFM0_CLK2_OUT Input selectWrite 1'b0: ECAP6_OUT [default]Write 1'b1: ECAP14_OUT" "0: ECAP6_OUT [default]Write,1: ECAP14_OUT" line.long 0xC "CONTROLSS_CTRL_SDFM0_CLK3_OUT_SEL,SDFM0_CLK[x]_OUT Input Select." bitfld.long 0xC 0. "SDFM0_CLK3_OUT_SEL_SEL,SDFM0_CLK3_OUT Input selectWrite 1'b0: ECAP7_OUT [default]Write 1'b1: ECAP15_OUT" "0: ECAP7_OUT [default]Write,1: ECAP15_OUT" line.long 0x10 "CONTROLSS_CTRL_SDFM1_CLK0_OUT_SEL,SDFM1_CLK[x]_OUT Input Select." bitfld.long 0x10 0. "SDFM1_CLK0_OUT_SEL_SEL,SDFM1_CLK0_OUT Input selectWrite 1'b0: ECAP7_OUT [default]Write 1'b1: ECAP15_OUT" "0: ECAP7_OUT [default]Write,1: ECAP15_OUT" line.long 0x14 "CONTROLSS_CTRL_SDFM1_CLK1_OUT_SEL,SDFM1_CLK[x]_OUT Input Select." bitfld.long 0x14 0. "SDFM1_CLK1_OUT_SEL_SEL,SDFM1_CLK1_OUT Input selectWrite 1'b0: ECAP6_OUT [default]Write 1'b1: ECAP14_OUT" "0: ECAP6_OUT [default]Write,1: ECAP14_OUT" line.long 0x18 "CONTROLSS_CTRL_SDFM1_CLK2_OUT_SEL,SDFM1_CLK[x]_OUT Input Select." bitfld.long 0x18 0. "SDFM1_CLK2_OUT_SEL_SEL,SDFM1_CLK2_OUT Input selectWrite 1'b0: ECAP5_OUT [default]Write 1'b1: ECAP13_OUT" "0: ECAP5_OUT [default]Write,1: ECAP13_OUT" line.long 0x1C "CONTROLSS_CTRL_SDFM1_CLK3_OUT_SEL,SDFM1_CLK[x]_OUT Input Select." bitfld.long 0x1C 0. "SDFM1_CLK3_OUT_SEL_SEL,SDFM1_CLK3_OUT Input selectWrite 1'b0: ECAP4_OUT [default]Write 1'b1: ECAP12_OUT" "0: ECAP4_OUT [default]Write,1: ECAP12_OUT" group.long 0xE0++0xF line.long 0x0 "CONTROLSS_CTRL_CONTROLSS_G0_EPWM_WLINK,Enable for WLINK of EPWM groups." hexmask.long 0x0 0.--31. 1. "CONTROLSS_G0_EPWM_WLINK_ENABLE,Writing 1'b1 to the bit enables the corresponding EPWM instance for WLINK feature" line.long 0x4 "CONTROLSS_CTRL_CONTROLSS_G1_EPWM_WLINK,Enable for WLINK of EPWM groups." hexmask.long 0x4 0.--31. 1. "CONTROLSS_G1_EPWM_WLINK_ENABLE,Writing 1'b1 to the bit enables the corresponding EPWM instance for WLINK feature" line.long 0x8 "CONTROLSS_CTRL_CONTROLSS_G2_EPWM_WLINK,Enable for WLINK of EPWM groups." hexmask.long 0x8 0.--31. 1. "CONTROLSS_G2_EPWM_WLINK_ENABLE,Writing 1'b1 to the bit enables the corresponding EPWM instance for WLINK feature" line.long 0xC "CONTROLSS_CTRL_CONTROLSS_G3_EPWM_WLINK,Enable for WLINK of EPWM groups." hexmask.long 0xC 0.--31. 1. "CONTROLSS_G3_EPWM_WLINK_ENABLE,Writing 1'b1 to the bit enables the corresponding EPWM instance for WLINK feature" group.long 0x100++0xC7 line.long 0x0 "CONTROLSS_CTRL_EPWM0_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x0 0.--2. "EPWM0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_EPWM1_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x4 0.--2. "EPWM1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_EPWM2_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x8 0.--2. "EPWM2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_EPWM3_CLK_GATE,To clock gate epwm[x]." bitfld.long 0xC 0.--2. "EPWM3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_EPWM4_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x10 0.--2. "EPWM4_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_EPWM5_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x14 0.--2. "EPWM5_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_EPWM6_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x18 0.--2. "EPWM6_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_EPWM7_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x1C 0.--2. "EPWM7_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_EPWM8_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x20 0.--2. "EPWM8_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_EPWM9_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x24 0.--2. "EPWM9_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x28 "CONTROLSS_CTRL_EPWM10_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x28 0.--2. "EPWM10_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x2C "CONTROLSS_CTRL_EPWM11_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x2C 0.--2. "EPWM11_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x30 "CONTROLSS_CTRL_EPWM12_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x30 0.--2. "EPWM12_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x34 "CONTROLSS_CTRL_EPWM13_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x34 0.--2. "EPWM13_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x38 "CONTROLSS_CTRL_EPWM14_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x38 0.--2. "EPWM14_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x3C "CONTROLSS_CTRL_EPWM15_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x3C 0.--2. "EPWM15_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x40 "CONTROLSS_CTRL_EPWM16_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x40 0.--2. "EPWM16_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x44 "CONTROLSS_CTRL_EPWM17_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x44 0.--2. "EPWM17_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x48 "CONTROLSS_CTRL_EPWM18_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x48 0.--2. "EPWM18_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x4C "CONTROLSS_CTRL_EPWM19_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x4C 0.--2. "EPWM19_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x50 "CONTROLSS_CTRL_EPWM20_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x50 0.--2. "EPWM20_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x54 "CONTROLSS_CTRL_EPWM21_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x54 0.--2. "EPWM21_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x58 "CONTROLSS_CTRL_EPWM22_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x58 0.--2. "EPWM22_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x5C "CONTROLSS_CTRL_EPWM23_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x5C 0.--2. "EPWM23_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x60 "CONTROLSS_CTRL_EPWM24_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x60 0.--2. "EPWM24_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x64 "CONTROLSS_CTRL_EPWM25_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x64 0.--2. "EPWM25_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x68 "CONTROLSS_CTRL_EPWM26_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x68 0.--2. "EPWM26_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x6C "CONTROLSS_CTRL_EPWM27_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x6C 0.--2. "EPWM27_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x70 "CONTROLSS_CTRL_EPWM28_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x70 0.--2. "EPWM28_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x74 "CONTROLSS_CTRL_EPWM29_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x74 0.--2. "EPWM29_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x78 "CONTROLSS_CTRL_EPWM30_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x78 0.--2. "EPWM30_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x7C "CONTROLSS_CTRL_EPWM31_CLK_GATE,To clock gate epwm[x]." bitfld.long 0x7C 0.--2. "EPWM31_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x80 "CONTROLSS_CTRL_FSI_TX0_CLK_GATE,fsi_tx[x] clock gate." bitfld.long 0x80 0.--2. "FSI_TX0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x84 "CONTROLSS_CTRL_FSI_TX1_CLK_GATE,fsi_tx[x] clock gate." bitfld.long 0x84 0.--2. "FSI_TX1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x88 "CONTROLSS_CTRL_FSI_TX2_CLK_GATE,fsi_tx[x] clock gate." bitfld.long 0x88 0.--2. "FSI_TX2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x8C "CONTROLSS_CTRL_FSI_TX3_CLK_GATE,fsi_tx[x] clock gate." bitfld.long 0x8C 0.--2. "FSI_TX3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x90 "CONTROLSS_CTRL_FSI_RX0_CLK_GATE,fsi_rx[x] clock gate." bitfld.long 0x90 0.--2. "FSI_RX0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0x94 "CONTROLSS_CTRL_FSI_RX1_CLK_GATE,fsi_rx[x] clock gate." bitfld.long 0x94 0.--2. "FSI_RX1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0x98 "CONTROLSS_CTRL_FSI_RX2_CLK_GATE,fsi_rx[x] clock gate." bitfld.long 0x98 0.--2. "FSI_RX2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0x9C "CONTROLSS_CTRL_FSI_RX3_CLK_GATE,fsi_rx[x] clock gate." bitfld.long 0x9C 0.--2. "FSI_RX3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0xA0 "CONTROLSS_CTRL_CMPSSA0_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xA0 0.--2. "CMPSSA0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xA4 "CONTROLSS_CTRL_CMPSSA1_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xA4 0.--2. "CMPSSA1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xA8 "CONTROLSS_CTRL_CMPSSA2_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xA8 0.--2. "CMPSSA2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xAC "CONTROLSS_CTRL_CMPSSA3_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xAC 0.--2. "CMPSSA3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xB0 "CONTROLSS_CTRL_CMPSSA4_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xB0 0.--2. "CMPSSA4_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xB4 "CONTROLSS_CTRL_CMPSSA5_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xB4 0.--2. "CMPSSA5_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xB8 "CONTROLSS_CTRL_CMPSSA6_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xB8 0.--2. "CMPSSA6_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xBC "CONTROLSS_CTRL_CMPSSA7_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xBC 0.--2. "CMPSSA7_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xC0 "CONTROLSS_CTRL_CMPSSA8_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xC0 0.--2. "CMPSSA8_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xC4 "CONTROLSS_CTRL_CMPSSA9_CLK_GATE,cmpssa[x] clock gate." bitfld.long 0xC4 0.--2. "CMPSSA9_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssa" "0,1,2,3,4,5,6,7" group.long 0x1D0++0x27 line.long 0x0 "CONTROLSS_CTRL_CMPSSB0_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x0 0.--2. "CMPSSB0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_CMPSSB1_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x4 0.--2. "CMPSSB1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_CMPSSB2_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x8 0.--2. "CMPSSB2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_CMPSSB3_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0xC 0.--2. "CMPSSB3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_CMPSSB4_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x10 0.--2. "CMPSSB4_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_CMPSSB5_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x14 0.--2. "CMPSSB5_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_CMPSSB6_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x18 0.--2. "CMPSSB6_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_CMPSSB7_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x1C 0.--2. "CMPSSB7_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_CMPSSB8_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x20 0.--2. "CMPSSB8_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_CMPSSB9_CLK_GATE,cmpssb[x] clock gate." bitfld.long 0x24 0.--2. "CMPSSB9_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding cmpssb" "0,1,2,3,4,5,6,7" group.long 0x200++0x4B line.long 0x0 "CONTROLSS_CTRL_ECAP0_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x0 0.--2. "ECAP0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_ECAP1_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x4 0.--2. "ECAP1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_ECAP2_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x8 0.--2. "ECAP2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_ECAP3_CLK_GATE,Ecap[x] clock gate." bitfld.long 0xC 0.--2. "ECAP3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_ECAP4_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x10 0.--2. "ECAP4_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_ECAP5_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x14 0.--2. "ECAP5_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_ECAP6_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x18 0.--2. "ECAP6_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_ECAP7_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x1C 0.--2. "ECAP7_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_ECAP8_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x20 0.--2. "ECAP8_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_ECAP9_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x24 0.--2. "ECAP9_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x28 "CONTROLSS_CTRL_ECAP10_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x28 0.--2. "ECAP10_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x2C "CONTROLSS_CTRL_ECAP11_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x2C 0.--2. "ECAP11_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x30 "CONTROLSS_CTRL_ECAP12_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x30 0.--2. "ECAP12_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x34 "CONTROLSS_CTRL_ECAP13_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x34 0.--2. "ECAP13_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x38 "CONTROLSS_CTRL_ECAP14_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x38 0.--2. "ECAP14_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x3C "CONTROLSS_CTRL_ECAP15_CLK_GATE,Ecap[x] clock gate." bitfld.long 0x3C 0.--2. "ECAP15_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x40 "CONTROLSS_CTRL_EQEP0_CLK_GATE,Eqep[x] clock gate." bitfld.long 0x40 0.--2. "EQEP0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding eqep" "0,1,2,3,4,5,6,7" line.long 0x44 "CONTROLSS_CTRL_EQEP1_CLK_GATE,Eqep[x] clock gate." bitfld.long 0x44 0.--2. "EQEP1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding eqep" "0,1,2,3,4,5,6,7" line.long 0x48 "CONTROLSS_CTRL_EQEP2_CLK_GATE,Eqep[x] clock gate." bitfld.long 0x48 0.--2. "EQEP2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding eqep" "0,1,2,3,4,5,6,7" group.long 0x250++0x7B line.long 0x0 "CONTROLSS_CTRL_SDFM0_CLK_GATE,Sdfm[x] clock gate." bitfld.long 0x0 0.--2. "SDFM0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding sdfm" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_SDFM1_CLK_GATE,Sdfm[x] clock gate." bitfld.long 0x4 0.--2. "SDFM1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding sdfm" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_DAC_CLK_GATE,dac clock gate." bitfld.long 0x8 0.--2. "DAC_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for dac" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_ADC0_CLK_GATE,Adc[x] clock gate." bitfld.long 0xC 0.--2. "ADC0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_ADC1_CLK_GATE,Adc[x] clock gate." bitfld.long 0x10 0.--2. "ADC1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_ADC2_CLK_GATE,Adc[x] clock gate." bitfld.long 0x14 0.--2. "ADC2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_ADC3_CLK_GATE,Adc[x] clock gate." bitfld.long 0x18 0.--2. "ADC3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_ADC4_CLK_GATE,Adc[x] clock gate." bitfld.long 0x1C 0.--2. "ADC4_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_OTTO0_CLK_GATE,Otto[x] clock gate." bitfld.long 0x20 0.--2. "OTTO0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_OTTO1_CLK_GATE,Otto[x] clock gate." bitfld.long 0x24 0.--2. "OTTO1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x28 "CONTROLSS_CTRL_OTTO2_CLK_GATE,Otto[x] clock gate." bitfld.long 0x28 0.--2. "OTTO2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x2C "CONTROLSS_CTRL_OTTO3_CLK_GATE,Otto[x] clock gate." bitfld.long 0x2C 0.--2. "OTTO3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x30 "CONTROLSS_CTRL_SDFM0_PLL_CLK_GATE,Sdfm[x]_pll clock gate." bitfld.long 0x30 0.--2. "SDFM0_PLL_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding sdfm pll clock" "0,1,2,3,4,5,6,7" line.long 0x34 "CONTROLSS_CTRL_SDFM1_PLL_CLK_GATE,Sdfm[x]_pll clock gate." bitfld.long 0x34 0.--2. "SDFM1_PLL_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding sdfm pll clock" "0,1,2,3,4,5,6,7" line.long 0x38 "CONTROLSS_CTRL_FSI_TX0_PLL_CLK_GATE,fsi_tx[x]_pll clock gate." bitfld.long 0x38 0.--2. "FSI_TX0_PLL_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" line.long 0x3C "CONTROLSS_CTRL_FSI_TX1_PLL_CLK_GATE,fsi_tx[x]_pll clock gate." bitfld.long 0x3C 0.--2. "FSI_TX1_PLL_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" line.long 0x40 "CONTROLSS_CTRL_FSI_TX2_PLL_CLK_GATE,fsi_tx[x]_pll clock gate." bitfld.long 0x40 0.--2. "FSI_TX2_PLL_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" line.long 0x44 "CONTROLSS_CTRL_FSI_TX3_PLL_CLK_GATE,fsi_tx[x]_pll clock gate." bitfld.long 0x44 0.--2. "FSI_TX3_PLL_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" line.long 0x48 "CONTROLSS_CTRL_HW_RESOLVER_CLK_GATE,Hardware resolver clock gate." bitfld.long 0x48 0.--2. "HW_RESOLVER_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding hw_resolver" "0,1,2,3,4,5,6,7" line.long 0x4C "CONTROLSS_CTRL_ADC_SCTILE0_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x4C 0.--2. "ADC_SCTILE0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x50 "CONTROLSS_CTRL_ADC_SCTILE1_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x50 0.--2. "ADC_SCTILE1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x54 "CONTROLSS_CTRL_ADC_SCTILE2_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x54 0.--2. "ADC_SCTILE2_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x58 "CONTROLSS_CTRL_ADC_SCTILE3_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x58 0.--2. "ADC_SCTILE3_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x5C "CONTROLSS_CTRL_ADC_SCTILE4_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x5C 0.--2. "ADC_SCTILE4_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x60 "CONTROLSS_CTRL_ADC_SCTILE5_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x60 0.--2. "ADC_SCTILE5_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x64 "CONTROLSS_CTRL_ADC_SCTILE6_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x64 0.--2. "ADC_SCTILE6_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x68 "CONTROLSS_CTRL_ADC_SCTILE7_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x68 0.--2. "ADC_SCTILE7_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x6C "CONTROLSS_CTRL_ADC_SCTILE8_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x6C 0.--2. "ADC_SCTILE8_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x70 "CONTROLSS_CTRL_ADC_SCTILE9_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x70 0.--2. "ADC_SCTILE9_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x74 "CONTROLSS_CTRL_ADC_SCTILE10_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x74 0.--2. "ADC_SCTILE10_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x78 "CONTROLSS_CTRL_ADC_SCTILE11_CLK_GATE,ADC Safecheck tiles clock gate." bitfld.long 0x78 0.--2. "ADC_SCTILE11_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" group.long 0x2DC++0xF line.long 0x0 "CONTROLSS_CTRL_ADC_AGG0_CLK_GATE,ADC Aggregator clock gate." bitfld.long 0x0 0.--2. "ADC_AGG0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc aggregator" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_CONTROLSS_XBAR_CLK_GATE,clock gate for eight XBARs." bitfld.long 0x4 28.--30. "CONTROLSS_XBAR_CLK_GATE_PWMSYNCOUTXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "CONTROLSS_XBAR_CLK_GATE_OUTPUTXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "CONTROLSS_XBAR_CLK_GATE_DMAXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "CONTROLSS_XBAR_CLK_GATE_INTXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "CONTROLSS_XBAR_CLK_GATE_ICLXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "CONTROLSS_XBAR_CLK_GATE_MDLXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "CONTROLSS_XBAR_CLK_GATE_PWMXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "CONTROLSS_XBAR_CLK_GATE_INPUTXBAR,Writing 3'b111 to register will clock gate the corresponding XBAR" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_ADCR0_CLK_GATE,Adcr[x] clock gate." bitfld.long 0x8 0.--2. "ADCR0_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_ADCR1_CLK_GATE,Adcr[x] clock gate." bitfld.long 0xC 0.--2. "ADCR1_CLK_GATE_CLK_GATE,Writing 3'b111 will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" group.long 0x300++0xC7 line.long 0x0 "CONTROLSS_CTRL_EPWM0_RST,Epwm[x]_reset." bitfld.long 0x0 0.--2. "EPWM0_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_EPWM1_RST,Epwm[x]_reset." bitfld.long 0x4 0.--2. "EPWM1_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_EPWM2_RST,Epwm[x]_reset." bitfld.long 0x8 0.--2. "EPWM2_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_EPWM3_RST,Epwm[x]_reset." bitfld.long 0xC 0.--2. "EPWM3_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_EPWM4_RST,Epwm[x]_reset." bitfld.long 0x10 0.--2. "EPWM4_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_EPWM5_RST,Epwm[x]_reset." bitfld.long 0x14 0.--2. "EPWM5_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_EPWM6_RST,Epwm[x]_reset." bitfld.long 0x18 0.--2. "EPWM6_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_EPWM7_RST,Epwm[x]_reset." bitfld.long 0x1C 0.--2. "EPWM7_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_EPWM8_RST,Epwm[x]_reset." bitfld.long 0x20 0.--2. "EPWM8_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_EPWM9_RST,Epwm[x]_reset." bitfld.long 0x24 0.--2. "EPWM9_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x28 "CONTROLSS_CTRL_EPWM10_RST,Epwm[x]_reset." bitfld.long 0x28 0.--2. "EPWM10_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x2C "CONTROLSS_CTRL_EPWM11_RST,Epwm[x]_reset." bitfld.long 0x2C 0.--2. "EPWM11_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x30 "CONTROLSS_CTRL_EPWM12_RST,Epwm[x]_reset." bitfld.long 0x30 0.--2. "EPWM12_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x34 "CONTROLSS_CTRL_EPWM13_RST,Epwm[x]_reset." bitfld.long 0x34 0.--2. "EPWM13_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x38 "CONTROLSS_CTRL_EPWM14_RST,Epwm[x]_reset." bitfld.long 0x38 0.--2. "EPWM14_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x3C "CONTROLSS_CTRL_EPWM15_RST,Epwm[x]_reset." bitfld.long 0x3C 0.--2. "EPWM15_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x40 "CONTROLSS_CTRL_EPWM16_RST,Epwm[x]_reset." bitfld.long 0x40 0.--2. "EPWM16_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x44 "CONTROLSS_CTRL_EPWM17_RST,Epwm[x]_reset." bitfld.long 0x44 0.--2. "EPWM17_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x48 "CONTROLSS_CTRL_EPWM18_RST,Epwm[x]_reset." bitfld.long 0x48 0.--2. "EPWM18_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x4C "CONTROLSS_CTRL_EPWM19_RST,Epwm[x]_reset." bitfld.long 0x4C 0.--2. "EPWM19_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x50 "CONTROLSS_CTRL_EPWM20_RST,Epwm[x]_reset." bitfld.long 0x50 0.--2. "EPWM20_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x54 "CONTROLSS_CTRL_EPWM21_RST,Epwm[x]_reset." bitfld.long 0x54 0.--2. "EPWM21_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x58 "CONTROLSS_CTRL_EPWM22_RST,Epwm[x]_reset." bitfld.long 0x58 0.--2. "EPWM22_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x5C "CONTROLSS_CTRL_EPWM23_RST,Epwm[x]_reset." bitfld.long 0x5C 0.--2. "EPWM23_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x60 "CONTROLSS_CTRL_EPWM24_RST,Epwm[x]_reset." bitfld.long 0x60 0.--2. "EPWM24_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x64 "CONTROLSS_CTRL_EPWM25_RST,Epwm[x]_reset." bitfld.long 0x64 0.--2. "EPWM25_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x68 "CONTROLSS_CTRL_EPWM26_RST,Epwm[x]_reset." bitfld.long 0x68 0.--2. "EPWM26_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x6C "CONTROLSS_CTRL_EPWM27_RST,Epwm[x]_reset." bitfld.long 0x6C 0.--2. "EPWM27_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x70 "CONTROLSS_CTRL_EPWM28_RST,Epwm[x]_reset." bitfld.long 0x70 0.--2. "EPWM28_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x74 "CONTROLSS_CTRL_EPWM29_RST,Epwm[x]_reset." bitfld.long 0x74 0.--2. "EPWM29_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x78 "CONTROLSS_CTRL_EPWM30_RST,Epwm[x]_reset." bitfld.long 0x78 0.--2. "EPWM30_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x7C "CONTROLSS_CTRL_EPWM31_RST,Epwm[x]_reset." bitfld.long 0x7C 0.--2. "EPWM31_RST_RST,Writing 3'b111 will generate reset for corresponding epwm" "0,1,2,3,4,5,6,7" line.long 0x80 "CONTROLSS_CTRL_FSI_TX0_RST,fsi_tx[x]_reset." bitfld.long 0x80 0.--2. "FSI_TX0_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x84 "CONTROLSS_CTRL_FSI_TX1_RST,fsi_tx[x]_reset." bitfld.long 0x84 0.--2. "FSI_TX1_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x88 "CONTROLSS_CTRL_FSI_TX2_RST,fsi_tx[x]_reset." bitfld.long 0x88 0.--2. "FSI_TX2_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x8C "CONTROLSS_CTRL_FSI_TX3_RST,fsi_tx[x]_reset." bitfld.long 0x8C 0.--2. "FSI_TX3_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" line.long 0x90 "CONTROLSS_CTRL_FSI_RX0_RST,fsi_rx[x]_reset." bitfld.long 0x90 0.--2. "FSI_RX0_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0x94 "CONTROLSS_CTRL_FSI_RX1_RST,fsi_rx[x]_reset." bitfld.long 0x94 0.--2. "FSI_RX1_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0x98 "CONTROLSS_CTRL_FSI_RX2_RST,fsi_rx[x]_reset." bitfld.long 0x98 0.--2. "FSI_RX2_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0x9C "CONTROLSS_CTRL_FSI_RX3_RST,fsi_rx[x]_reset." bitfld.long 0x9C 0.--2. "FSI_RX3_RST_RST,Writing 3'b111 will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" line.long 0xA0 "CONTROLSS_CTRL_CMPSSA0_RST,cmpssa[x]_reset." bitfld.long 0xA0 0.--2. "CMPSSA0_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xA4 "CONTROLSS_CTRL_CMPSSA1_RST,cmpssa[x]_reset." bitfld.long 0xA4 0.--2. "CMPSSA1_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xA8 "CONTROLSS_CTRL_CMPSSA2_RST,cmpssa[x]_reset." bitfld.long 0xA8 0.--2. "CMPSSA2_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xAC "CONTROLSS_CTRL_CMPSSA3_RST,cmpssa[x]_reset." bitfld.long 0xAC 0.--2. "CMPSSA3_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xB0 "CONTROLSS_CTRL_CMPSSA4_RST,cmpssa[x]_reset." bitfld.long 0xB0 0.--2. "CMPSSA4_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xB4 "CONTROLSS_CTRL_CMPSSA5_RST,cmpssa[x]_reset." bitfld.long 0xB4 0.--2. "CMPSSA5_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xB8 "CONTROLSS_CTRL_CMPSSA6_RST,cmpssa[x]_reset." bitfld.long 0xB8 0.--2. "CMPSSA6_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xBC "CONTROLSS_CTRL_CMPSSA7_RST,cmpssa[x]_reset." bitfld.long 0xBC 0.--2. "CMPSSA7_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xC0 "CONTROLSS_CTRL_CMPSSA8_RST,cmpssa[x]_reset." bitfld.long 0xC0 0.--2. "CMPSSA8_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" line.long 0xC4 "CONTROLSS_CTRL_CMPSSA9_RST,cmpssa[x]_reset." bitfld.long 0xC4 0.--2. "CMPSSA9_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssa" "0,1,2,3,4,5,6,7" group.long 0x3D0++0x27 line.long 0x0 "CONTROLSS_CTRL_CMPSSB0_RST,cmpssb[x]_reset." bitfld.long 0x0 0.--2. "CMPSSB0_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_CMPSSB1_RST,cmpssb[x]_reset." bitfld.long 0x4 0.--2. "CMPSSB1_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_CMPSSB2_RST,cmpssb[x]_reset." bitfld.long 0x8 0.--2. "CMPSSB2_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_CMPSSB3_RST,cmpssb[x]_reset." bitfld.long 0xC 0.--2. "CMPSSB3_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_CMPSSB4_RST,cmpssb[x]_reset." bitfld.long 0x10 0.--2. "CMPSSB4_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_CMPSSB5_RST,cmpssb[x]_reset." bitfld.long 0x14 0.--2. "CMPSSB5_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_CMPSSB6_RST,cmpssb[x]_reset." bitfld.long 0x18 0.--2. "CMPSSB6_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_CMPSSB7_RST,cmpssb[x]_reset." bitfld.long 0x1C 0.--2. "CMPSSB7_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_CMPSSB8_RST,cmpssb[x]_reset." bitfld.long 0x20 0.--2. "CMPSSB8_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_CMPSSB9_RST,cmpssb[x]_reset." bitfld.long 0x24 0.--2. "CMPSSB9_RST_RST,Writing 3'b111 will generate reset for corresponding cmpssb" "0,1,2,3,4,5,6,7" group.long 0x400++0x4B line.long 0x0 "CONTROLSS_CTRL_ECAP0_RST,Ecap[x]_reset." bitfld.long 0x0 0.--2. "ECAP0_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_ECAP1_RST,Ecap[x]_reset." bitfld.long 0x4 0.--2. "ECAP1_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_ECAP2_RST,Ecap[x]_reset." bitfld.long 0x8 0.--2. "ECAP2_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_ECAP3_RST,Ecap[x]_reset." bitfld.long 0xC 0.--2. "ECAP3_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_ECAP4_RST,Ecap[x]_reset." bitfld.long 0x10 0.--2. "ECAP4_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_ECAP5_RST,Ecap[x]_reset." bitfld.long 0x14 0.--2. "ECAP5_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_ECAP6_RST,Ecap[x]_reset." bitfld.long 0x18 0.--2. "ECAP6_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_ECAP7_RST,Ecap[x]_reset." bitfld.long 0x1C 0.--2. "ECAP7_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_ECAP8_RST,Ecap[x]_reset." bitfld.long 0x20 0.--2. "ECAP8_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_ECAP9_RST,Ecap[x]_reset." bitfld.long 0x24 0.--2. "ECAP9_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x28 "CONTROLSS_CTRL_ECAP10_RST,Ecap[x]_reset." bitfld.long 0x28 0.--2. "ECAP10_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x2C "CONTROLSS_CTRL_ECAP11_RST,Ecap[x]_reset." bitfld.long 0x2C 0.--2. "ECAP11_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x30 "CONTROLSS_CTRL_ECAP12_RST,Ecap[x]_reset." bitfld.long 0x30 0.--2. "ECAP12_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x34 "CONTROLSS_CTRL_ECAP13_RST,Ecap[x]_reset." bitfld.long 0x34 0.--2. "ECAP13_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x38 "CONTROLSS_CTRL_ECAP14_RST,Ecap[x]_reset." bitfld.long 0x38 0.--2. "ECAP14_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x3C "CONTROLSS_CTRL_ECAP15_RST,Ecap[x]_reset." bitfld.long 0x3C 0.--2. "ECAP15_RST_RST,Writing 3'b111 will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" line.long 0x40 "CONTROLSS_CTRL_EQEP0_RST,Eqep[x]_reset." bitfld.long 0x40 0.--2. "EQEP0_RST_RST,Writing 3'b111 will generate reset for corresponding eqep" "0,1,2,3,4,5,6,7" line.long 0x44 "CONTROLSS_CTRL_EQEP1_RST,Eqep[x]_reset." bitfld.long 0x44 0.--2. "EQEP1_RST_RST,Writing 3'b111 will generate reset for corresponding eqep" "0,1,2,3,4,5,6,7" line.long 0x48 "CONTROLSS_CTRL_EQEP2_RST,Eqep[x]_reset." bitfld.long 0x48 0.--2. "EQEP2_RST_RST,Writing 3'b111 will generate reset for corresponding eqep" "0,1,2,3,4,5,6,7" group.long 0x450++0x63 line.long 0x0 "CONTROLSS_CTRL_SDFM0_RST,Sdfm[x]_reset." bitfld.long 0x0 0.--2. "SDFM0_RST_RST,Writing 3'b111 will generate reset for corresponding sdfm" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_SDFM1_RST,Sdfm[x]_reset." bitfld.long 0x4 0.--2. "SDFM1_RST_RST,Writing 3'b111 will generate reset for corresponding sdfm" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_DAC_RST,dac_reset." bitfld.long 0x8 0.--2. "DAC_RST_RST,Writing 3'b111 will generate reset for dac" "0,1,2,3,4,5,6,7" line.long 0xC "CONTROLSS_CTRL_ADC0_RST,Adc[x]_reset." bitfld.long 0xC 0.--2. "ADC0_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x10 "CONTROLSS_CTRL_ADC1_RST,Adc[x]_reset." bitfld.long 0x10 0.--2. "ADC1_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x14 "CONTROLSS_CTRL_ADC2_RST,Adc[x]_reset." bitfld.long 0x14 0.--2. "ADC2_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x18 "CONTROLSS_CTRL_ADC3_RST,Adc[x]_reset." bitfld.long 0x18 0.--2. "ADC3_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_CTRL_ADC4_RST,Adc[x]_reset." bitfld.long 0x1C 0.--2. "ADC4_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x20 "CONTROLSS_CTRL_OTTO0_RST,Otto[x]_reset." bitfld.long 0x20 0.--2. "OTTO0_RST_RST,Writing 3'b111 will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x24 "CONTROLSS_CTRL_OTTO1_RST,Otto[x]_reset." bitfld.long 0x24 0.--2. "OTTO1_RST_RST,Writing 3'b111 will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x28 "CONTROLSS_CTRL_OTTO2_RST,Otto[x]_reset." bitfld.long 0x28 0.--2. "OTTO2_RST_RST,Writing 3'b111 will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x2C "CONTROLSS_CTRL_OTTO3_RST,Otto[x]_reset." bitfld.long 0x2C 0.--2. "OTTO3_RST_RST,Writing 3'b111 will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" line.long 0x30 "CONTROLSS_CTRL_HW_RESOLVER_RST,Hardware resolver reset." bitfld.long 0x30 0.--2. "HW_RESOLVER_RST_RST,Writing 3'b111 will generate reset for corresponding hw_resolver" "0,1,2,3,4,5,6,7" line.long 0x34 "CONTROLSS_CTRL_ADC_SCTILE0_RST,ADC Safecheck tiles Reset." bitfld.long 0x34 0.--2. "ADC_SCTILE0_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x38 "CONTROLSS_CTRL_ADC_SCTILE1_RST,ADC Safecheck tiles Reset." bitfld.long 0x38 0.--2. "ADC_SCTILE1_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x3C "CONTROLSS_CTRL_ADC_SCTILE2_RST,ADC Safecheck tiles Reset." bitfld.long 0x3C 0.--2. "ADC_SCTILE2_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x40 "CONTROLSS_CTRL_ADC_SCTILE3_RST,ADC Safecheck tiles Reset." bitfld.long 0x40 0.--2. "ADC_SCTILE3_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x44 "CONTROLSS_CTRL_ADC_SCTILE4_RST,ADC Safecheck tiles Reset." bitfld.long 0x44 0.--2. "ADC_SCTILE4_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x48 "CONTROLSS_CTRL_ADC_SCTILE5_RST,ADC Safecheck tiles Reset." bitfld.long 0x48 0.--2. "ADC_SCTILE5_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x4C "CONTROLSS_CTRL_ADC_SCTILE6_RST,ADC Safecheck tiles Reset." bitfld.long 0x4C 0.--2. "ADC_SCTILE6_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x50 "CONTROLSS_CTRL_ADC_SCTILE7_RST,ADC Safecheck tiles Reset." bitfld.long 0x50 0.--2. "ADC_SCTILE7_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x54 "CONTROLSS_CTRL_ADC_SCTILE8_RST,ADC Safecheck tiles Reset." bitfld.long 0x54 0.--2. "ADC_SCTILE8_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x58 "CONTROLSS_CTRL_ADC_SCTILE9_RST,ADC Safecheck tiles Reset." bitfld.long 0x58 0.--2. "ADC_SCTILE9_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x5C "CONTROLSS_CTRL_ADC_SCTILE10_RST,ADC Safecheck tiles Reset." bitfld.long 0x5C 0.--2. "ADC_SCTILE10_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" line.long 0x60 "CONTROLSS_CTRL_ADC_SCTILE11_RST,ADC Safecheck tiles Reset." bitfld.long 0x60 0.--2. "ADC_SCTILE11_RST_RST,Writing 3'b111 will generate reset for corresponding adc safety tiles" "0,1,2,3,4,5,6,7" group.long 0x4C4++0xB line.long 0x0 "CONTROLSS_CTRL_ADC_AGG0_RST,ADC Aggregator Reset." bitfld.long 0x0 0.--2. "ADC_AGG0_RST_RST,Writing 3'b111 will generate reset for corresponding adc aggregator" "0,1,2,3,4,5,6,7" line.long 0x4 "CONTROLSS_CTRL_ADCR0_RST,Adcr[x] reset." bitfld.long 0x4 0.--2. "ADCR0_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" line.long 0x8 "CONTROLSS_CTRL_ADCR1_RST,Adcr[x] reset." bitfld.long 0x8 0.--2. "ADCR1_RST_RST,Writing 3'b111 will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" group.long 0x500++0x11B line.long 0x0 "CONTROLSS_CTRL_EPWM0_HALTEN,Epwm halt enable." bitfld.long 0x0 3. "EPWM0_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x0 2. "EPWM0_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x0 1. "EPWM0_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x0 0. "EPWM0_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x4 "CONTROLSS_CTRL_EPWM1_HALTEN,Epwm halt enable." bitfld.long 0x4 3. "EPWM1_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x4 2. "EPWM1_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x4 1. "EPWM1_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x4 0. "EPWM1_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x8 "CONTROLSS_CTRL_EPWM2_HALTEN,Epwm halt enable." bitfld.long 0x8 3. "EPWM2_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x8 2. "EPWM2_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x8 1. "EPWM2_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x8 0. "EPWM2_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xC "CONTROLSS_CTRL_EPWM3_HALTEN,Epwm halt enable." bitfld.long 0xC 3. "EPWM3_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC 2. "EPWM3_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC 1. "EPWM3_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC 0. "EPWM3_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x10 "CONTROLSS_CTRL_EPWM4_HALTEN,Epwm halt enable." bitfld.long 0x10 3. "EPWM4_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x10 2. "EPWM4_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x10 1. "EPWM4_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x10 0. "EPWM4_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x14 "CONTROLSS_CTRL_EPWM5_HALTEN,Epwm halt enable." bitfld.long 0x14 3. "EPWM5_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x14 2. "EPWM5_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x14 1. "EPWM5_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x14 0. "EPWM5_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x18 "CONTROLSS_CTRL_EPWM6_HALTEN,Epwm halt enable." bitfld.long 0x18 3. "EPWM6_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x18 2. "EPWM6_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x18 1. "EPWM6_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x18 0. "EPWM6_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x1C "CONTROLSS_CTRL_EPWM7_HALTEN,Epwm halt enable." bitfld.long 0x1C 3. "EPWM7_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x1C 2. "EPWM7_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x1C 1. "EPWM7_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x1C 0. "EPWM7_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x20 "CONTROLSS_CTRL_EPWM8_HALTEN,Epwm halt enable." bitfld.long 0x20 3. "EPWM8_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x20 2. "EPWM8_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x20 1. "EPWM8_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x20 0. "EPWM8_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x24 "CONTROLSS_CTRL_EPWM9_HALTEN,Epwm halt enable." bitfld.long 0x24 3. "EPWM9_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x24 2. "EPWM9_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x24 1. "EPWM9_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x24 0. "EPWM9_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x28 "CONTROLSS_CTRL_EPWM10_HALTEN,Epwm halt enable." bitfld.long 0x28 3. "EPWM10_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x28 2. "EPWM10_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x28 1. "EPWM10_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x28 0. "EPWM10_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x2C "CONTROLSS_CTRL_EPWM11_HALTEN,Epwm halt enable." bitfld.long 0x2C 3. "EPWM11_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x2C 2. "EPWM11_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x2C 1. "EPWM11_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x2C 0. "EPWM11_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x30 "CONTROLSS_CTRL_EPWM12_HALTEN,Epwm halt enable." bitfld.long 0x30 3. "EPWM12_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x30 2. "EPWM12_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x30 1. "EPWM12_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x30 0. "EPWM12_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x34 "CONTROLSS_CTRL_EPWM13_HALTEN,Epwm halt enable." bitfld.long 0x34 3. "EPWM13_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x34 2. "EPWM13_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x34 1. "EPWM13_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x34 0. "EPWM13_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x38 "CONTROLSS_CTRL_EPWM14_HALTEN,Epwm halt enable." bitfld.long 0x38 3. "EPWM14_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x38 2. "EPWM14_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x38 1. "EPWM14_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x38 0. "EPWM14_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x3C "CONTROLSS_CTRL_EPWM15_HALTEN,Epwm halt enable." bitfld.long 0x3C 3. "EPWM15_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x3C 2. "EPWM15_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x3C 1. "EPWM15_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x3C 0. "EPWM15_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x40 "CONTROLSS_CTRL_EPWM16_HALTEN,Epwm halt enable." bitfld.long 0x40 3. "EPWM16_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x40 2. "EPWM16_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x40 1. "EPWM16_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x40 0. "EPWM16_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x44 "CONTROLSS_CTRL_EPWM17_HALTEN,Epwm halt enable." bitfld.long 0x44 3. "EPWM17_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x44 2. "EPWM17_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x44 1. "EPWM17_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x44 0. "EPWM17_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x48 "CONTROLSS_CTRL_EPWM18_HALTEN,Epwm halt enable." bitfld.long 0x48 3. "EPWM18_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x48 2. "EPWM18_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x48 1. "EPWM18_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x48 0. "EPWM18_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x4C "CONTROLSS_CTRL_EPWM19_HALTEN,Epwm halt enable." bitfld.long 0x4C 3. "EPWM19_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x4C 2. "EPWM19_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x4C 1. "EPWM19_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x4C 0. "EPWM19_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x50 "CONTROLSS_CTRL_EPWM20_HALTEN,Epwm halt enable." bitfld.long 0x50 3. "EPWM20_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x50 2. "EPWM20_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x50 1. "EPWM20_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x50 0. "EPWM20_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x54 "CONTROLSS_CTRL_EPWM21_HALTEN,Epwm halt enable." bitfld.long 0x54 3. "EPWM21_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x54 2. "EPWM21_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x54 1. "EPWM21_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x54 0. "EPWM21_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x58 "CONTROLSS_CTRL_EPWM22_HALTEN,Epwm halt enable." bitfld.long 0x58 3. "EPWM22_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x58 2. "EPWM22_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x58 1. "EPWM22_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x58 0. "EPWM22_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x5C "CONTROLSS_CTRL_EPWM23_HALTEN,Epwm halt enable." bitfld.long 0x5C 3. "EPWM23_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x5C 2. "EPWM23_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x5C 1. "EPWM23_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x5C 0. "EPWM23_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x60 "CONTROLSS_CTRL_EPWM24_HALTEN,Epwm halt enable." bitfld.long 0x60 3. "EPWM24_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x60 2. "EPWM24_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x60 1. "EPWM24_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x60 0. "EPWM24_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x64 "CONTROLSS_CTRL_EPWM25_HALTEN,Epwm halt enable." bitfld.long 0x64 3. "EPWM25_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x64 2. "EPWM25_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x64 1. "EPWM25_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x64 0. "EPWM25_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x68 "CONTROLSS_CTRL_EPWM26_HALTEN,Epwm halt enable." bitfld.long 0x68 3. "EPWM26_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x68 2. "EPWM26_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x68 1. "EPWM26_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x68 0. "EPWM26_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x6C "CONTROLSS_CTRL_EPWM27_HALTEN,Epwm halt enable." bitfld.long 0x6C 3. "EPWM27_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x6C 2. "EPWM27_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x6C 1. "EPWM27_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x6C 0. "EPWM27_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x70 "CONTROLSS_CTRL_EPWM28_HALTEN,Epwm halt enable." bitfld.long 0x70 3. "EPWM28_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x70 2. "EPWM28_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x70 1. "EPWM28_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x70 0. "EPWM28_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x74 "CONTROLSS_CTRL_EPWM29_HALTEN,Epwm halt enable." bitfld.long 0x74 3. "EPWM29_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x74 2. "EPWM29_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x74 1. "EPWM29_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x74 0. "EPWM29_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x78 "CONTROLSS_CTRL_EPWM30_HALTEN,Epwm halt enable." bitfld.long 0x78 3. "EPWM30_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x78 2. "EPWM30_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x78 1. "EPWM30_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x78 0. "EPWM30_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x7C "CONTROLSS_CTRL_EPWM31_HALTEN,Epwm halt enable." bitfld.long 0x7C 3. "EPWM31_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x7C 2. "EPWM31_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x7C 1. "EPWM31_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x7C 0. "EPWM31_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x80 "CONTROLSS_CTRL_CMPSSA0_HALTEN,cmpssa halt enable." bitfld.long 0x80 3. "CMPSSA0_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x80 2. "CMPSSA0_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x80 1. "CMPSSA0_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x80 0. "CMPSSA0_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x84 "CONTROLSS_CTRL_CMPSSA1_HALTEN,cmpssa halt enable." bitfld.long 0x84 3. "CMPSSA1_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x84 2. "CMPSSA1_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x84 1. "CMPSSA1_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x84 0. "CMPSSA1_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x88 "CONTROLSS_CTRL_CMPSSA2_HALTEN,cmpssa halt enable." bitfld.long 0x88 3. "CMPSSA2_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x88 2. "CMPSSA2_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x88 1. "CMPSSA2_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x88 0. "CMPSSA2_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x8C "CONTROLSS_CTRL_CMPSSA3_HALTEN,cmpssa halt enable." bitfld.long 0x8C 3. "CMPSSA3_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x8C 2. "CMPSSA3_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x8C 1. "CMPSSA3_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x8C 0. "CMPSSA3_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x90 "CONTROLSS_CTRL_CMPSSA4_HALTEN,cmpssa halt enable." bitfld.long 0x90 3. "CMPSSA4_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x90 2. "CMPSSA4_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x90 1. "CMPSSA4_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x90 0. "CMPSSA4_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x94 "CONTROLSS_CTRL_CMPSSA5_HALTEN,cmpssa halt enable." bitfld.long 0x94 3. "CMPSSA5_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x94 2. "CMPSSA5_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x94 1. "CMPSSA5_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x94 0. "CMPSSA5_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x98 "CONTROLSS_CTRL_CMPSSA6_HALTEN,cmpssa halt enable." bitfld.long 0x98 3. "CMPSSA6_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x98 2. "CMPSSA6_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x98 1. "CMPSSA6_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x98 0. "CMPSSA6_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x9C "CONTROLSS_CTRL_CMPSSA7_HALTEN,cmpssa halt enable." bitfld.long 0x9C 3. "CMPSSA7_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x9C 2. "CMPSSA7_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x9C 1. "CMPSSA7_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x9C 0. "CMPSSA7_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xA0 "CONTROLSS_CTRL_CMPSSA8_HALTEN,cmpssa halt enable." bitfld.long 0xA0 3. "CMPSSA8_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA0 2. "CMPSSA8_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA0 1. "CMPSSA8_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA0 0. "CMPSSA8_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xA4 "CONTROLSS_CTRL_CMPSSA9_HALTEN,cmpssa halt enable." bitfld.long 0xA4 3. "CMPSSA9_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA4 2. "CMPSSA9_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA4 1. "CMPSSA9_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA4 0. "CMPSSA9_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xA8 "CONTROLSS_CTRL_CMPSSB0_HALTEN,cmpssb halt enable." bitfld.long 0xA8 3. "CMPSSB0_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA8 2. "CMPSSB0_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA8 1. "CMPSSB0_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xA8 0. "CMPSSB0_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xAC "CONTROLSS_CTRL_CMPSSB1_HALTEN,cmpssb halt enable." bitfld.long 0xAC 3. "CMPSSB1_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xAC 2. "CMPSSB1_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xAC 1. "CMPSSB1_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xAC 0. "CMPSSB1_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xB0 "CONTROLSS_CTRL_CMPSSB2_HALTEN,cmpssb halt enable." bitfld.long 0xB0 3. "CMPSSB2_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB0 2. "CMPSSB2_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB0 1. "CMPSSB2_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB0 0. "CMPSSB2_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xB4 "CONTROLSS_CTRL_CMPSSB3_HALTEN,cmpssb halt enable." bitfld.long 0xB4 3. "CMPSSB3_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB4 2. "CMPSSB3_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB4 1. "CMPSSB3_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB4 0. "CMPSSB3_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xB8 "CONTROLSS_CTRL_CMPSSB4_HALTEN,cmpssb halt enable." bitfld.long 0xB8 3. "CMPSSB4_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB8 2. "CMPSSB4_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB8 1. "CMPSSB4_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xB8 0. "CMPSSB4_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xBC "CONTROLSS_CTRL_CMPSSB5_HALTEN,cmpssb halt enable." bitfld.long 0xBC 3. "CMPSSB5_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xBC 2. "CMPSSB5_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xBC 1. "CMPSSB5_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xBC 0. "CMPSSB5_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xC0 "CONTROLSS_CTRL_CMPSSB6_HALTEN,cmpssb halt enable." bitfld.long 0xC0 3. "CMPSSB6_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC0 2. "CMPSSB6_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC0 1. "CMPSSB6_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC0 0. "CMPSSB6_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xC4 "CONTROLSS_CTRL_CMPSSB7_HALTEN,cmpssb halt enable." bitfld.long 0xC4 3. "CMPSSB7_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC4 2. "CMPSSB7_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC4 1. "CMPSSB7_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC4 0. "CMPSSB7_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xC8 "CONTROLSS_CTRL_CMPSSB8_HALTEN,cmpssb halt enable." bitfld.long 0xC8 3. "CMPSSB8_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC8 2. "CMPSSB8_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC8 1. "CMPSSB8_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xC8 0. "CMPSSB8_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xCC "CONTROLSS_CTRL_CMPSSB9_HALTEN,cmpssb halt enable." bitfld.long 0xCC 3. "CMPSSB9_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xCC 2. "CMPSSB9_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xCC 1. "CMPSSB9_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xCC 0. "CMPSSB9_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xD0 "CONTROLSS_CTRL_ECAP0_HALTEN,Ecap halt enable." bitfld.long 0xD0 3. "ECAP0_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD0 2. "ECAP0_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD0 1. "ECAP0_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD0 0. "ECAP0_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xD4 "CONTROLSS_CTRL_ECAP1_HALTEN,Ecap halt enable." bitfld.long 0xD4 3. "ECAP1_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD4 2. "ECAP1_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD4 1. "ECAP1_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD4 0. "ECAP1_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xD8 "CONTROLSS_CTRL_ECAP2_HALTEN,Ecap halt enable." bitfld.long 0xD8 3. "ECAP2_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD8 2. "ECAP2_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD8 1. "ECAP2_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xD8 0. "ECAP2_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xDC "CONTROLSS_CTRL_ECAP3_HALTEN,Ecap halt enable." bitfld.long 0xDC 3. "ECAP3_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xDC 2. "ECAP3_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xDC 1. "ECAP3_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xDC 0. "ECAP3_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xE0 "CONTROLSS_CTRL_ECAP4_HALTEN,Ecap halt enable." bitfld.long 0xE0 3. "ECAP4_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE0 2. "ECAP4_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE0 1. "ECAP4_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE0 0. "ECAP4_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xE4 "CONTROLSS_CTRL_ECAP5_HALTEN,Ecap halt enable." bitfld.long 0xE4 3. "ECAP5_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE4 2. "ECAP5_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE4 1. "ECAP5_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE4 0. "ECAP5_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xE8 "CONTROLSS_CTRL_ECAP6_HALTEN,Ecap halt enable." bitfld.long 0xE8 3. "ECAP6_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE8 2. "ECAP6_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE8 1. "ECAP6_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xE8 0. "ECAP6_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xEC "CONTROLSS_CTRL_ECAP7_HALTEN,Ecap halt enable." bitfld.long 0xEC 3. "ECAP7_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xEC 2. "ECAP7_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xEC 1. "ECAP7_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xEC 0. "ECAP7_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xF0 "CONTROLSS_CTRL_ECAP8_HALTEN,Ecap halt enable." bitfld.long 0xF0 3. "ECAP8_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF0 2. "ECAP8_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF0 1. "ECAP8_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF0 0. "ECAP8_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xF4 "CONTROLSS_CTRL_ECAP9_HALTEN,Ecap halt enable." bitfld.long 0xF4 3. "ECAP9_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF4 2. "ECAP9_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF4 1. "ECAP9_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF4 0. "ECAP9_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xF8 "CONTROLSS_CTRL_EQEP0_HALTEN,Eqep halt enable." bitfld.long 0xF8 3. "EQEP0_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF8 2. "EQEP0_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF8 1. "EQEP0_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xF8 0. "EQEP0_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0xFC "CONTROLSS_CTRL_EQEP1_HALTEN,Eqep halt enable." bitfld.long 0xFC 3. "EQEP1_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xFC 2. "EQEP1_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xFC 1. "EQEP1_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0xFC 0. "EQEP1_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x100 "CONTROLSS_CTRL_EQEP2_HALTEN,Eqep halt enable." bitfld.long 0x100 3. "EQEP2_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x100 2. "EQEP2_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x100 1. "EQEP2_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x100 0. "EQEP2_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x104 "CONTROLSS_CTRL_ECAP10_HALTEN,Ecap halt enable." bitfld.long 0x104 3. "ECAP10_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x104 2. "ECAP10_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x104 1. "ECAP10_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x104 0. "ECAP10_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x108 "CONTROLSS_CTRL_ECAP11_HALTEN,Ecap halt enable." bitfld.long 0x108 3. "ECAP11_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x108 2. "ECAP11_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x108 1. "ECAP11_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x108 0. "ECAP11_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x10C "CONTROLSS_CTRL_ECAP12_HALTEN,Ecap halt enable." bitfld.long 0x10C 3. "ECAP12_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x10C 2. "ECAP12_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x10C 1. "ECAP12_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x10C 0. "ECAP12_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x110 "CONTROLSS_CTRL_ECAP13_HALTEN,Ecap halt enable." bitfld.long 0x110 3. "ECAP13_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x110 2. "ECAP13_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x110 1. "ECAP13_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x110 0. "ECAP13_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x114 "CONTROLSS_CTRL_ECAP14_HALTEN,Ecap halt enable." bitfld.long 0x114 3. "ECAP14_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x114 2. "ECAP14_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x114 1. "ECAP14_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x114 0. "ECAP14_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" line.long 0x118 "CONTROLSS_CTRL_ECAP15_HALTEN,Ecap halt enable." bitfld.long 0x118 3. "ECAP15_HALTEN_CR5B1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x118 2. "ECAP15_HALTEN_CR5A1,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x118 1. "ECAP15_HALTEN_CR5B0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" newline bitfld.long 0x118 0. "ECAP15_HALTEN_CR5A0,Write 1'b0: IP Halt disabled with corresponding CPU haltWrite 1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU haltWrite,1: IP Halt enabled with corresponding CPU halt" group.long 0x1008++0x1B line.long 0x0 "CONTROLSS_CTRL_LOCK0_KICK0,- KICK0 component." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CONTROLSS_CTRL_LOCK0_KICK1,- KICK1 component." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CONTROLSS_CTRL_INTR_RAW_STATUS,Interrupt Raw Status/Set Register." bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CONTROLSS_CTRL_INTR_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear register." bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CONTROLSS_CTRL_INTR_ENABLE,Interrupt Enable register." bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CONTROLSS_CTRL_INTR_ENABLE_CLEAR,Interrupt Enable Clear register." bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CONTROLSS_CTRL_EOI,EOI register." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CONTROLSS_CTRL_FAULT_ADDRESS,Fault Address register." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CONTROLSS_CTRL_FAULT_TYPE_STATUS,Fault Type Status register." bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." line.long 0x8 "CONTROLSS_CTRL_FAULT_ATTR_STATUS,Fault Attribute Status register." hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "CONTROLSS_CTRL_FAULT_CLEAR,Fault Clear register." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree "CONTROLSS_ICLXBAR" base ad:0x502D4000 group.long 0x100++0xB line.long 0x0 "CONTROLSS_ICLXBAR0_G0,ICL XBAR 0 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR0_G0_SEL,ICL XBAR0 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR0_G1,ICL XBAR 0 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR0_G1_SEL,ICL XBAR0 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR0_G2,ICL XBAR 0 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR0_G2_SEL,ICL XBAR0 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x140++0xB line.long 0x0 "CONTROLSS_ICLXBAR1_G0,ICL XBAR 1 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR1_G0_SEL,ICL XBAR1 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR1_G1,ICL XBAR 1 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR1_G1_SEL,ICL XBAR1 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR1_G2,ICL XBAR 1 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR1_G2_SEL,ICL XBAR1 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x180++0xB line.long 0x0 "CONTROLSS_ICLXBAR2_G0,ICL XBAR 2 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR2_G0_SEL,ICL XBAR2 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR2_G1,ICL XBAR 2 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR2_G1_SEL,ICL XBAR2 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR2_G2,ICL XBAR 2 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR2_G2_SEL,ICL XBAR2 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x1C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR3_G0,ICL XBAR 3 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR3_G0_SEL,ICL XBAR3 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR3_G1,ICL XBAR 3 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR3_G1_SEL,ICL XBAR3 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR3_G2,ICL XBAR 3 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR3_G2_SEL,ICL XBAR3 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x200++0xB line.long 0x0 "CONTROLSS_ICLXBAR4_G0,ICL XBAR 4 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR4_G0_SEL,ICL XBAR4 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR4_G1,ICL XBAR 4 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR4_G1_SEL,ICL XBAR4 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR4_G2,ICL XBAR 4 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR4_G2_SEL,ICL XBAR4 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x240++0xB line.long 0x0 "CONTROLSS_ICLXBAR5_G0,ICL XBAR 5 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR5_G0_SEL,ICL XBAR5 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR5_G1,ICL XBAR 5 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR5_G1_SEL,ICL XBAR5 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR5_G2,ICL XBAR 5 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR5_G2_SEL,ICL XBAR5 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x280++0xB line.long 0x0 "CONTROLSS_ICLXBAR6_G0,ICL XBAR 6 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR6_G0_SEL,ICL XBAR6 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR6_G1,ICL XBAR 6 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR6_G1_SEL,ICL XBAR6 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR6_G2,ICL XBAR 6 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR6_G2_SEL,ICL XBAR6 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x2C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR7_G0,ICL XBAR 7 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR7_G0_SEL,ICL XBAR7 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR7_G1,ICL XBAR 7 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR7_G1_SEL,ICL XBAR7 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR7_G2,ICL XBAR 7 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR7_G2_SEL,ICL XBAR7 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x300++0xB line.long 0x0 "CONTROLSS_ICLXBAR8_G0,ICL XBAR 8 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR8_G0_SEL,ICL XBAR8 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR8_G1,ICL XBAR 8 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR8_G1_SEL,ICL XBAR8 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR8_G2,ICL XBAR 8 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR8_G2_SEL,ICL XBAR8 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x340++0xB line.long 0x0 "CONTROLSS_ICLXBAR9_G0,ICL XBAR 9 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR9_G0_SEL,ICL XBAR9 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR9_G1,ICL XBAR 9 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR9_G1_SEL,ICL XBAR9 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR9_G2,ICL XBAR 9 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR9_G2_SEL,ICL XBAR9 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x380++0xB line.long 0x0 "CONTROLSS_ICLXBAR10_G0,ICL XBAR 10 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR10_G0_SEL,ICL XBAR10 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR10_G1,ICL XBAR 10 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR10_G1_SEL,ICL XBAR10 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR10_G2,ICL XBAR 10 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR10_G2_SEL,ICL XBAR10 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x3C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR11_G0,ICL XBAR 11 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR11_G0_SEL,ICL XBAR11 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR11_G1,ICL XBAR 11 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR11_G1_SEL,ICL XBAR11 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR11_G2,ICL XBAR 11 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR11_G2_SEL,ICL XBAR11 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x400++0xB line.long 0x0 "CONTROLSS_ICLXBAR12_G0,ICL XBAR 12 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR12_G0_SEL,ICL XBAR12 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR12_G1,ICL XBAR 12 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR12_G1_SEL,ICL XBAR12 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR12_G2,ICL XBAR 12 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR12_G2_SEL,ICL XBAR12 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x440++0xB line.long 0x0 "CONTROLSS_ICLXBAR13_G0,ICL XBAR 13 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR13_G0_SEL,ICL XBAR13 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR13_G1,ICL XBAR 13 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR13_G1_SEL,ICL XBAR13 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR13_G2,ICL XBAR 13 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR13_G2_SEL,ICL XBAR13 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x480++0xB line.long 0x0 "CONTROLSS_ICLXBAR14_G0,ICL XBAR 14 Input Select." hexmask.long 0x0 0.--31. 1. "ICLXBAR14_G0_SEL,ICL XBAR14 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR14_G1,ICL XBAR 14 Input Select." hexmask.long 0x4 0.--31. 1. "ICLXBAR14_G1_SEL,ICL XBAR14 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR14_G2,ICL XBAR 14 Input Select." hexmask.long 0x8 0.--31. 1. "ICLXBAR14_G2_SEL,ICL XBAR14 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x4C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR15_G0,ICL XBAR 15 Input Select ." hexmask.long 0x0 0.--31. 1. "ICLXBAR15_G0_SEL,ICL XBAR15 G0 input bit select. Input source is PWMA hr select1:PWMA hr bit[x] selected0:PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR15_G1,ICL XBAR 15 Input Select ." hexmask.long 0x4 0.--31. 1. "ICLXBAR15_G1_SEL,ICL XBAR15 G1 input bit select. Input source is PWMB hr select1:PWMB hr bit[x] selected0:PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR15_G2,ICL XBAR 15 Input Select ." hexmask.long 0x8 0.--31. 1. "ICLXBAR15_G2_SEL,ICL XBAR15 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" tree.end tree "CONTROLSS_INPUTXBAR" base ad:0x502D0000 group.long 0x100++0xF line.long 0x0 "CONTROLSS_INPUTXBAR0_GSEL,INPUT XBAR0 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR0_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR0_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR0_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR0_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR0_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR0_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR0_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x140++0xF line.long 0x0 "CONTROLSS_INPUTXBAR1_GSEL,INPUT XBAR1 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR1_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR1_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR1_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR1_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR1_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR1_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR1_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x180++0xF line.long 0x0 "CONTROLSS_INPUTXBAR2_GSEL,INPUT XBAR2 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR2_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR2_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR2_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR2_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR2_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR2_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR2_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x1C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR3_GSEL,INPUT XBAR3 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR3_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR3_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR3_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR3_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR3_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR3_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR3_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x200++0xF line.long 0x0 "CONTROLSS_INPUTXBAR4_GSEL,INPUT XBAR4 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR4_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR4_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR4_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR4_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR4_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR4_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR4_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x240++0xF line.long 0x0 "CONTROLSS_INPUTXBAR5_GSEL,INPUT XBAR5 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR5_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR5_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR5_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR5_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR5_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR5_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR5_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x280++0xF line.long 0x0 "CONTROLSS_INPUTXBAR6_GSEL,INPUT XBAR6 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR6_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR6_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR6_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR6_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR6_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR6_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR6_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x2C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR7_GSEL,INPUT XBAR7 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR7_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR7_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR7_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR7_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR7_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR7_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR7_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x300++0xF line.long 0x0 "CONTROLSS_INPUTXBAR8_GSEL,INPUT XBAR8 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR8_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR8_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR8_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR8_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR8_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR8_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR8_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x340++0xF line.long 0x0 "CONTROLSS_INPUTXBAR9_GSEL,INPUT XBAR9 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR9_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR9_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR9_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR9_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR9_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR9_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR9_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x380++0xF line.long 0x0 "CONTROLSS_INPUTXBAR10_GSEL,INPUT XBAR10 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR10_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR10_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR10_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR10_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR10_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR10_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR10_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x3C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR11_GSEL,INPUT XBAR11 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR11_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR11_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR11_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR11_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR11_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR11_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR11_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x400++0xF line.long 0x0 "CONTROLSS_INPUTXBAR12_GSEL,INPUT XBAR12 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR12_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR12_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR12_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR12_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR12_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR12_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR12_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x440++0xF line.long 0x0 "CONTROLSS_INPUTXBAR13_GSEL,INPUT XBAR13 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR13_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR13_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR13_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR13_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR13_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR13_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR13_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x480++0xF line.long 0x0 "CONTROLSS_INPUTXBAR14_GSEL,INPUT XBAR14 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR14_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR14_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR14_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR14_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR14_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR14_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR14_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x4C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR15_GSEL,INPUT XBAR15 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR15_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR15_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR15_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR15_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR15_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR15_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR15_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x500++0xF line.long 0x0 "CONTROLSS_INPUTXBAR16_GSEL,INPUT XBAR16 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR16_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR16_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR16_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR16_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR16_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR16_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR16_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x540++0xF line.long 0x0 "CONTROLSS_INPUTXBAR17_GSEL,INPUT XBAR17 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR17_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR17_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR17_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR17_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR17_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR17_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR17_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x580++0xF line.long 0x0 "CONTROLSS_INPUTXBAR18_GSEL,INPUT XBAR18 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR18_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR18_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR18_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR18_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR18_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR18_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR18_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x5C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR19_GSEL,INPUT XBAR19 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR19_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR19_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR19_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR19_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR19_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR19_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR19_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x600++0xF line.long 0x0 "CONTROLSS_INPUTXBAR20_GSEL,INPUT XBAR20 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR20_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR20_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR20_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR20_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR20_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR20_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR20_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x640++0xF line.long 0x0 "CONTROLSS_INPUTXBAR21_GSEL,INPUT XBAR21 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR21_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR21_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR21_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR21_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR21_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR21_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR21_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x680++0xF line.long 0x0 "CONTROLSS_INPUTXBAR22_GSEL,INPUT XBAR22 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR22_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR22_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR22_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR22_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR22_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR22_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR22_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x6C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR23_GSEL,INPUT XBAR23 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR23_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR23_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR23_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR23_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR23_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR23_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR23_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x700++0xF line.long 0x0 "CONTROLSS_INPUTXBAR24_GSEL,INPUT XBAR24 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR24_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR24_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR24_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR24_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR24_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR24_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR24_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x740++0xF line.long 0x0 "CONTROLSS_INPUTXBAR25_GSEL,INPUT XBAR25 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR25_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR25_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR25_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR25_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR25_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR25_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR25_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x780++0xF line.long 0x0 "CONTROLSS_INPUTXBAR26_GSEL,INPUT XBAR26 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR26_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR26_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR26_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR26_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR26_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR26_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR26_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x7C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR27_GSEL,INPUT XBAR27 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR27_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR27_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR27_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR27_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR27_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR27_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR27_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x800++0xF line.long 0x0 "CONTROLSS_INPUTXBAR28_GSEL,INPUT XBAR28 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR28_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR28_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR28_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR28_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR28_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR28_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR28_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x840++0xF line.long 0x0 "CONTROLSS_INPUTXBAR29_GSEL,INPUT XBAR29 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR29_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR29_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR29_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR29_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR29_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR29_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR29_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x880++0xF line.long 0x0 "CONTROLSS_INPUTXBAR30_GSEL,INPUT XBAR30 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR30_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR30_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR30_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR30_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR30_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR30_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR30_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" group.long 0x8C0++0xF line.long 0x0 "CONTROLSS_INPUTXBAR31_GSEL,INPUT XBAR31 Input Select0 : GPI1: ICSS GPO port." bitfld.long 0x0 0.--1. "INPUTXBAR31_GSEL_GSEL,Select input source Group:0 G0 selected1 G1 selected2 G2 selected" "0,1,2,3" line.long 0x4 "CONTROLSS_INPUTXBAR31_G0,Input GPI XBAR selection - valid inputs are GPI[143:0]." hexmask.long.byte 0x4 0.--7. 1. "INPUTXBAR31_G0_SEL,Select input source:0 G0.0 selected..x G0.x selected" line.long 0x8 "CONTROLSS_INPUTXBAR31_G1,ICSS GPO port selection - ICSS GPO[31:0]." hexmask.long.byte 0x8 0.--4. 1. "INPUTXBAR31_G1_SEL,Select input source:0 G1.0 selected..31 G1.31 selected" line.long 0xC "CONTROLSS_INPUTXBAR31_G2,OUTPUTXBAR port selection - OUTPUTXBAR[15:0]." hexmask.long.byte 0xC 0.--3. 1. "INPUTXBAR31_G2_SEL,Select input source:0 G2.0 selected..15 G2.15 selected" tree.end tree "CONTROLSS_INTXBAR" base ad:0x502D5000 group.long 0x100++0x27 line.long 0x0 "CONTROLSS_INTXBAR0_G0,INT XBAR 0 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR0_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR0_G1,INT XBAR 0 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR0_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR0_G2,INT XBAR 0 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR0_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR0_G3,INT XBAR 0 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR0_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR0_G4,INT XBAR 0 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR0_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR0_G5,INT XBAR 0 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR0_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR0_G6,INT XBAR 0 Input Select." bitfld.long 0x18 0.--2. "INTXBAR0_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR0_G7,INT XBAR 0 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR0_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR0_G8,INT XBAR 0 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR0_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR0_G9,INT XBAR 0 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR0_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x140++0x27 line.long 0x0 "CONTROLSS_INTXBAR1_G0,INT XBAR 1 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR1_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR1_G1,INT XBAR 1 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR1_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR1_G2,INT XBAR 1 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR1_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR1_G3,INT XBAR 1 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR1_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR1_G4,INT XBAR 1 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR1_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR1_G5,INT XBAR 1 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR1_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR1_G6,INT XBAR 1 Input Select." bitfld.long 0x18 0.--2. "INTXBAR1_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR1_G7,INT XBAR 1 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR1_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR1_G8,INT XBAR 1 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR1_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR1_G9,INT XBAR 1 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR1_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x180++0x27 line.long 0x0 "CONTROLSS_INTXBAR2_G0,INT XBAR 2 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR2_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR2_G1,INT XBAR 2 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR2_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR2_G2,INT XBAR 2 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR2_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR2_G3,INT XBAR 2 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR2_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR2_G4,INT XBAR 2 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR2_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR2_G5,INT XBAR 2 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR2_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR2_G6,INT XBAR 2 Input Select." bitfld.long 0x18 0.--2. "INTXBAR2_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR2_G7,INT XBAR 2 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR2_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR2_G8,INT XBAR 2 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR2_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR2_G9,INT XBAR 2 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR2_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x1C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR3_G0,INT XBAR 3 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR3_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR3_G1,INT XBAR 3 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR3_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR3_G2,INT XBAR 3 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR3_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR3_G3,INT XBAR 3 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR3_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR3_G4,INT XBAR 3 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR3_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR3_G5,INT XBAR 3 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR3_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR3_G6,INT XBAR 3 Input Select." bitfld.long 0x18 0.--2. "INTXBAR3_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR3_G7,INT XBAR 3 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR3_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR3_G8,INT XBAR 3 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR3_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR3_G9,INT XBAR 3 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR3_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x200++0x27 line.long 0x0 "CONTROLSS_INTXBAR4_G0,INT XBAR 4 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR4_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR4_G1,INT XBAR 4 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR4_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR4_G2,INT XBAR 4 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR4_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR4_G3,INT XBAR 4 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR4_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR4_G4,INT XBAR 4 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR4_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR4_G5,INT XBAR 4 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR4_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR4_G6,INT XBAR 4 Input Select." bitfld.long 0x18 0.--2. "INTXBAR4_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR4_G7,INT XBAR 4 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR4_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR4_G8,INT XBAR 4 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR4_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR4_G9,INT XBAR 4 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR4_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x240++0x27 line.long 0x0 "CONTROLSS_INTXBAR5_G0,INT XBAR 5 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR5_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR5_G1,INT XBAR 5 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR5_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR5_G2,INT XBAR 5 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR5_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR5_G3,INT XBAR 5 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR5_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR5_G4,INT XBAR 5 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR5_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR5_G5,INT XBAR 5 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR5_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR5_G6,INT XBAR 5 Input Select." bitfld.long 0x18 0.--2. "INTXBAR5_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR5_G7,INT XBAR 5 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR5_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR5_G8,INT XBAR 5 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR5_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR5_G9,INT XBAR 5 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR5_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x280++0x27 line.long 0x0 "CONTROLSS_INTXBAR6_G0,INT XBAR 6 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR6_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR6_G1,INT XBAR 6 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR6_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR6_G2,INT XBAR 6 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR6_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR6_G3,INT XBAR 6 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR6_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR6_G4,INT XBAR 6 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR6_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR6_G5,INT XBAR 6 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR6_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR6_G6,INT XBAR 6 Input Select." bitfld.long 0x18 0.--2. "INTXBAR6_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR6_G7,INT XBAR 6 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR6_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR6_G8,INT XBAR 6 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR6_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR6_G9,INT XBAR 6 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR6_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x2C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR7_G0,INT XBAR 7 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR7_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR7_G1,INT XBAR 7 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR7_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR7_G2,INT XBAR 7 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR7_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR7_G3,INT XBAR 7 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR7_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR7_G4,INT XBAR 7 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR7_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR7_G5,INT XBAR 7 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR7_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR7_G6,INT XBAR 7 Input Select." bitfld.long 0x18 0.--2. "INTXBAR7_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR7_G7,INT XBAR 7 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR7_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR7_G8,INT XBAR 7 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR7_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR7_G9,INT XBAR 7 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR7_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x300++0x27 line.long 0x0 "CONTROLSS_INTXBAR8_G0,INT XBAR 8 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR8_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR8_G1,INT XBAR 8 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR8_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR8_G2,INT XBAR 8 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR8_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR8_G3,INT XBAR 8 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR8_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR8_G4,INT XBAR 8 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR8_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR8_G5,INT XBAR 8 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR8_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR8_G6,INT XBAR 8 Input Select." bitfld.long 0x18 0.--2. "INTXBAR8_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR8_G7,INT XBAR 8 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR8_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR8_G8,INT XBAR 8 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR8_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR8_G9,INT XBAR 8 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR8_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x340++0x27 line.long 0x0 "CONTROLSS_INTXBAR9_G0,INT XBAR 9 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR9_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR9_G1,INT XBAR 9 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR9_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR9_G2,INT XBAR 9 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR9_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR9_G3,INT XBAR 9 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR9_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR9_G4,INT XBAR 9 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR9_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR9_G5,INT XBAR 9 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR9_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR9_G6,INT XBAR 9 Input Select." bitfld.long 0x18 0.--2. "INTXBAR9_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR9_G7,INT XBAR 9 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR9_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR9_G8,INT XBAR 9 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR9_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR9_G9,INT XBAR 9 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR9_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x380++0x27 line.long 0x0 "CONTROLSS_INTXBAR10_G0,INT XBAR 10 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR10_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR10_G1,INT XBAR 10 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR10_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR10_G2,INT XBAR 10 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR10_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR10_G3,INT XBAR 10 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR10_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR10_G4,INT XBAR 10 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR10_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR10_G5,INT XBAR 10 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR10_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR10_G6,INT XBAR 10 Input Select." bitfld.long 0x18 0.--2. "INTXBAR10_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR10_G7,INT XBAR 10 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR10_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR10_G8,INT XBAR 10 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR10_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR10_G9,INT XBAR 10 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR10_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x3C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR11_G0,INT XBAR 11 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR11_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR11_G1,INT XBAR 11 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR11_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR11_G2,INT XBAR 11 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR11_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR11_G3,INT XBAR 11 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR11_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR11_G4,INT XBAR 11 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR11_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR11_G5,INT XBAR 11 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR11_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR11_G6,INT XBAR 11 Input Select." bitfld.long 0x18 0.--2. "INTXBAR11_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR11_G7,INT XBAR 11 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR11_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR11_G8,INT XBAR 11 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR11_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR11_G9,INT XBAR 11 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR11_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x400++0x27 line.long 0x0 "CONTROLSS_INTXBAR12_G0,INT XBAR 12 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR12_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR12_G1,INT XBAR 12 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR12_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR12_G2,INT XBAR 12 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR12_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR12_G3,INT XBAR 12 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR12_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR12_G4,INT XBAR 12 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR12_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR12_G5,INT XBAR 12 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR12_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR12_G6,INT XBAR 12 Input Select." bitfld.long 0x18 0.--2. "INTXBAR12_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR12_G7,INT XBAR 12 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR12_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR12_G8,INT XBAR 12 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR12_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR12_G9,INT XBAR 12 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR12_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x440++0x27 line.long 0x0 "CONTROLSS_INTXBAR13_G0,INT XBAR 13 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR13_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR13_G1,INT XBAR 13 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR13_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR13_G2,INT XBAR 13 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR13_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR13_G3,INT XBAR 13 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR13_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR13_G4,INT XBAR 13 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR13_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR13_G5,INT XBAR 13 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR13_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR13_G6,INT XBAR 13 Input Select." bitfld.long 0x18 0.--2. "INTXBAR13_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR13_G7,INT XBAR 13 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR13_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR13_G8,INT XBAR 13 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR13_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR13_G9,INT XBAR 13 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR13_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x480++0x27 line.long 0x0 "CONTROLSS_INTXBAR14_G0,INT XBAR 14 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR14_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR14_G1,INT XBAR 14 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR14_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR14_G2,INT XBAR 14 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR14_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR14_G3,INT XBAR 14 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR14_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR14_G4,INT XBAR 14 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR14_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR14_G5,INT XBAR 14 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR14_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR14_G6,INT XBAR 14 Input Select." bitfld.long 0x18 0.--2. "INTXBAR14_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR14_G7,INT XBAR 14 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR14_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR14_G8,INT XBAR 14 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR14_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR14_G9,INT XBAR 14 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR14_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x4C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR15_G0,INT XBAR 15 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR15_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR15_G1,INT XBAR 15 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR15_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR15_G2,INT XBAR 15 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR15_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR15_G3,INT XBAR 15 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR15_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR15_G4,INT XBAR 15 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR15_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR15_G5,INT XBAR 15 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR15_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR15_G6,INT XBAR 15 Input Select." bitfld.long 0x18 0.--2. "INTXBAR15_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR15_G7,INT XBAR 15 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR15_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR15_G8,INT XBAR 15 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR15_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR15_G9,INT XBAR 15 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR15_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x500++0x27 line.long 0x0 "CONTROLSS_INTXBAR16_G0,INT XBAR 16 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR16_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR16_G1,INT XBAR 16 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR16_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR16_G2,INT XBAR 16 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR16_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR16_G3,INT XBAR 16 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR16_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR16_G4,INT XBAR 16 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR16_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR16_G5,INT XBAR 16 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR16_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR16_G6,INT XBAR 16 Input Select." bitfld.long 0x18 0.--2. "INTXBAR16_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR16_G7,INT XBAR 16 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR16_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR16_G8,INT XBAR 16 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR16_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR16_G9,INT XBAR 16 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR16_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x540++0x27 line.long 0x0 "CONTROLSS_INTXBAR17_G0,INT XBAR 17 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR17_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR17_G1,INT XBAR 17 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR17_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR17_G2,INT XBAR 17 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR17_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR17_G3,INT XBAR 17 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR17_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR17_G4,INT XBAR 17 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR17_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR17_G5,INT XBAR 17 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR17_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR17_G6,INT XBAR 17 Input Select." bitfld.long 0x18 0.--2. "INTXBAR17_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR17_G7,INT XBAR 17 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR17_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR17_G8,INT XBAR 17 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR17_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR17_G9,INT XBAR 17 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR17_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x580++0x27 line.long 0x0 "CONTROLSS_INTXBAR18_G0,INT XBAR 18 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR18_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR18_G1,INT XBAR 18 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR18_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR18_G2,INT XBAR 18 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR18_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR18_G3,INT XBAR 18 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR18_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR18_G4,INT XBAR 18 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR18_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR18_G5,INT XBAR 18 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR18_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR18_G6,INT XBAR 18 Input Select." bitfld.long 0x18 0.--2. "INTXBAR18_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR18_G7,INT XBAR 18 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR18_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR18_G8,INT XBAR 18 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR18_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR18_G9,INT XBAR 18 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR18_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x5C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR19_G0,INT XBAR 19 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR19_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR19_G1,INT XBAR 19 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR19_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR19_G2,INT XBAR 19 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR19_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR19_G3,INT XBAR 19 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR19_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR19_G4,INT XBAR 19 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR19_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR19_G5,INT XBAR 19 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR19_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR19_G6,INT XBAR 19 Input Select." bitfld.long 0x18 0.--2. "INTXBAR19_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR19_G7,INT XBAR 19 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR19_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR19_G8,INT XBAR 19 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR19_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR19_G9,INT XBAR 19 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR19_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x600++0x27 line.long 0x0 "CONTROLSS_INTXBAR20_G0,INT XBAR 20 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR20_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR20_G1,INT XBAR 20 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR20_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR20_G2,INT XBAR 20 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR20_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR20_G3,INT XBAR 20 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR20_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR20_G4,INT XBAR 20 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR20_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR20_G5,INT XBAR 20 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR20_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR20_G6,INT XBAR 20 Input Select." bitfld.long 0x18 0.--2. "INTXBAR20_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR20_G7,INT XBAR 20 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR20_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR20_G8,INT XBAR 20 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR20_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR20_G9,INT XBAR 20 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR20_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x640++0x27 line.long 0x0 "CONTROLSS_INTXBAR21_G0,INT XBAR 21 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR21_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR21_G1,INT XBAR 21 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR21_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR21_G2,INT XBAR 21 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR21_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR21_G3,INT XBAR 21 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR21_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR21_G4,INT XBAR 21 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR21_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR21_G5,INT XBAR 21 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR21_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR21_G6,INT XBAR 21 Input Select." bitfld.long 0x18 0.--2. "INTXBAR21_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR21_G7,INT XBAR 21 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR21_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR21_G8,INT XBAR 21 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR21_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR21_G9,INT XBAR 21 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR21_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x680++0x27 line.long 0x0 "CONTROLSS_INTXBAR22_G0,INT XBAR 22 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR22_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR22_G1,INT XBAR 22 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR22_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR22_G2,INT XBAR 22 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR22_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR22_G3,INT XBAR 22 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR22_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR22_G4,INT XBAR 22 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR22_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR22_G5,INT XBAR 22 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR22_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR22_G6,INT XBAR 22 Input Select." bitfld.long 0x18 0.--2. "INTXBAR22_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR22_G7,INT XBAR 22 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR22_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR22_G8,INT XBAR 22 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR22_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR22_G9,INT XBAR 22 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR22_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x6C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR23_G0,INT XBAR 23 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR23_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR23_G1,INT XBAR 23 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR23_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR23_G2,INT XBAR 23 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR23_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR23_G3,INT XBAR 23 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR23_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR23_G4,INT XBAR 23 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR23_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR23_G5,INT XBAR 23 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR23_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR23_G6,INT XBAR 23 Input Select." bitfld.long 0x18 0.--2. "INTXBAR23_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR23_G7,INT XBAR 23 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR23_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR23_G8,INT XBAR 23 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR23_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR23_G9,INT XBAR 23 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR23_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x700++0x27 line.long 0x0 "CONTROLSS_INTXBAR24_G0,INT XBAR 24 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR24_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR24_G1,INT XBAR 24 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR24_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR24_G2,INT XBAR 24 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR24_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR24_G3,INT XBAR 24 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR24_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR24_G4,INT XBAR 24 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR24_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR24_G5,INT XBAR 24 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR24_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR24_G6,INT XBAR 24 Input Select." bitfld.long 0x18 0.--2. "INTXBAR24_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR24_G7,INT XBAR 24 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR24_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR24_G8,INT XBAR 24 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR24_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR24_G9,INT XBAR 24 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR24_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x740++0x27 line.long 0x0 "CONTROLSS_INTXBAR25_G0,INT XBAR 25 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR25_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR25_G1,INT XBAR 25 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR25_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR25_G2,INT XBAR 25 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR25_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR25_G3,INT XBAR 25 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR25_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR25_G4,INT XBAR 25 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR25_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR25_G5,INT XBAR 25 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR25_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR25_G6,INT XBAR 25 Input Select." bitfld.long 0x18 0.--2. "INTXBAR25_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR25_G7,INT XBAR 25 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR25_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR25_G8,INT XBAR 25 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR25_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR25_G9,INT XBAR 25 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR25_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x780++0x27 line.long 0x0 "CONTROLSS_INTXBAR26_G0,INT XBAR 26 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR26_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR26_G1,INT XBAR 26 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR26_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR26_G2,INT XBAR 26 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR26_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR26_G3,INT XBAR 26 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR26_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR26_G4,INT XBAR 26 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR26_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR26_G5,INT XBAR 26 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR26_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR26_G6,INT XBAR 26 Input Select." bitfld.long 0x18 0.--2. "INTXBAR26_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR26_G7,INT XBAR 26 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR26_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR26_G8,INT XBAR 26 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR26_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR26_G9,INT XBAR 26 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR26_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x7C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR27_G0,INT XBAR 27 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR27_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR27_G1,INT XBAR 27 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR27_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR27_G2,INT XBAR 27 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR27_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR27_G3,INT XBAR 27 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR27_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR27_G4,INT XBAR 27 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR27_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR27_G5,INT XBAR 27 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR27_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR27_G6,INT XBAR 27 Input Select." bitfld.long 0x18 0.--2. "INTXBAR27_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR27_G7,INT XBAR 27 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR27_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR27_G8,INT XBAR 27 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR27_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR27_G9,INT XBAR 27 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR27_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x800++0x27 line.long 0x0 "CONTROLSS_INTXBAR28_G0,INT XBAR 28 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR28_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR28_G1,INT XBAR 28 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR28_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR28_G2,INT XBAR 28 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR28_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR28_G3,INT XBAR 28 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR28_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR28_G4,INT XBAR 28 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR28_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR28_G5,INT XBAR 28 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR28_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR28_G6,INT XBAR 28 Input Select." bitfld.long 0x18 0.--2. "INTXBAR28_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR28_G7,INT XBAR 28 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR28_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR28_G8,INT XBAR 28 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR28_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR28_G9,INT XBAR 28 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR28_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x840++0x27 line.long 0x0 "CONTROLSS_INTXBAR29_G0,INT XBAR 29 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR29_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR29_G1,INT XBAR 29 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR29_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR29_G2,INT XBAR 29 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR29_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR29_G3,INT XBAR 29 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR29_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR29_G4,INT XBAR 29 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR29_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR29_G5,INT XBAR 29 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR29_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR29_G6,INT XBAR 29 Input Select." bitfld.long 0x18 0.--2. "INTXBAR29_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR29_G7,INT XBAR 29 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR29_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR29_G8,INT XBAR 29 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR29_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR29_G9,INT XBAR 29 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR29_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x880++0x27 line.long 0x0 "CONTROLSS_INTXBAR30_G0,INT XBAR 30 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR30_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR30_G1,INT XBAR 30 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR30_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR30_G2,INT XBAR 30 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR30_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR30_G3,INT XBAR 30 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR30_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR30_G4,INT XBAR 30 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR30_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR30_G5,INT XBAR 30 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR30_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR30_G6,INT XBAR 30 Input Select." bitfld.long 0x18 0.--2. "INTXBAR30_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR30_G7,INT XBAR 30 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR30_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR30_G8,INT XBAR 30 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR30_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR30_G9,INT XBAR 30 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR30_G9_SEL,Corresponding INT XBAR G9 Input.." group.long 0x8C0++0x27 line.long 0x0 "CONTROLSS_INTXBAR31_G0,INT XBAR 31 Input Select." hexmask.long 0x0 0.--31. 1. "INTXBAR31_G0_SEL,EPWM INT interrupt to corresponding XBAR1:PWMx.INT is selected0:PWMx.INT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_INTXBAR31_G1,INT XBAR 31 Input Select." hexmask.long 0x4 0.--31. 1. "INTXBAR31_G1_SEL,EPWM TZINT interrupt to corresponding XBAR1:PWMx.TZINT is selected0:PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR31_G2,INT XBAR 31 Input Select." hexmask.long 0x8 0.--31. 1. "INTXBAR31_G2_SEL,Corresponding INT XBAR G2 Input.." line.long 0xC "CONTROLSS_INTXBAR31_G3,INT XBAR 31 Input Select." hexmask.long.word 0xC 0.--15. 1. "INTXBAR31_G3_SEL,Corresponding INT XBAR G3 Input.." line.long 0x10 "CONTROLSS_INTXBAR31_G4,INT XBAR 31 Input Select." hexmask.long.word 0x10 0.--9. 1. "INTXBAR31_G4_SEL,Corresponding INT XBAR G4 Input Select0:SD0.ERR1:SD0.FILT1.DRINT2:SD0.FILT2.DRINT3:SD0.FILT3.DRINT4:SD0.FILT4.DRINT5:SD1.ERR6:SD1.FILT1.DRINT7:SD1.FILT2.DRINT8:SD1.FILT3.DRINT9:SD1.FILT4.DRINT" line.long 0x14 "CONTROLSS_INTXBAR31_G5,INT XBAR 31 Input Select." hexmask.long.word 0x14 0.--15. 1. "INTXBAR31_G5_SEL,Corresponding INT XBAR G5 Input Select0:ECAP0.INT1:ECAP1.INT2:ECAP2.INT3:ECAP3.INT4:ECAP4.INT5:ECAP5.INT6:ECAP6.INT7:ECAP7.INT8:ECAP8.INT9:ECAP9.INT10:ECAP10.INT11:ECAP11.INT12:ECAP12.INT13:ECAP13.INT14:ECAP14.INT15:ECAP15.INT" line.long 0x18 "CONTROLSS_INTXBAR31_G6,INT XBAR 31 Input Select." bitfld.long 0x18 0.--2. "INTXBAR31_G6_SEL,Corresponding INT XBAR G6 Input Select0:EQEP0.INT1:EQEP1.INT2:EQEP2.INT" "0,1,2,3,4,5,6,7" line.long 0x1C "CONTROLSS_INTXBAR31_G7,INT XBAR 31 Input Select." hexmask.long.word 0x1C 0.--9. 1. "INTXBAR31_G7_SEL,Corresponding INT XBAR G7 Input SelectBit0:ADCR0.INT1Bit1:ADCR0.INT2Bit2:ADCR0.INT3Bit3:ADCR0.INT4Bit4:ADCR0.EVTINTBit5:ADCR1.INT1Bit6:ADCR1.INT2Bit7:ADCR1.INT3Bit8:ADCR1.INT4Bit9:ADCR1.EVTINTBit 1031:Reserved" line.long 0x20 "CONTROLSS_INTXBAR31_G8,INT XBAR 31 Input Select." hexmask.long.tbyte 0x20 0.--19. 1. "INTXBAR31_G8_SEL,Corresponding INT XBAR G8 Input.." line.long 0x24 "CONTROLSS_INTXBAR31_G9,INT XBAR 31 Input Select." hexmask.long.tbyte 0x24 0.--19. 1. "INTXBAR31_G9_SEL,Corresponding INT XBAR G9 Input.." tree.end tree "CONTROLSS_MDLXBAR" base ad:0x502D3000 group.long 0x100++0xB line.long 0x0 "CONTROLSS_MDLXBAR0_G0,MDL XBAR 0 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR0_G0_SEL,MDL XBAR0 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR0_G1,MDL XBAR 0 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR0_G1_SEL,MDL XBAR0 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR0_G2,MDL XBAR 0 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR0_G2_SEL,MDL XBAR0 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x140++0xB line.long 0x0 "CONTROLSS_MDLXBAR1_G0,MDL XBAR 1 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR1_G0_SEL,MDL XBAR1 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR1_G1,MDL XBAR 1 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR1_G1_SEL,MDL XBAR1 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR1_G2,MDL XBAR 1 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR1_G2_SEL,MDL XBAR1 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x180++0xB line.long 0x0 "CONTROLSS_MDLXBAR2_G0,MDL XBAR 2 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR2_G0_SEL,MDL XBAR2 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR2_G1,MDL XBAR 2 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR2_G1_SEL,MDL XBAR2 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR2_G2,MDL XBAR 2 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR2_G2_SEL,MDL XBAR2 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x1C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR3_G0,MDL XBAR 3 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR3_G0_SEL,MDL XBAR3 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR3_G1,MDL XBAR 3 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR3_G1_SEL,MDL XBAR3 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR3_G2,MDL XBAR 3 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR3_G2_SEL,MDL XBAR3 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x200++0xB line.long 0x0 "CONTROLSS_MDLXBAR4_G0,MDL XBAR 4 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR4_G0_SEL,MDL XBAR4 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR4_G1,MDL XBAR 4 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR4_G1_SEL,MDL XBAR4 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR4_G2,MDL XBAR 4 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR4_G2_SEL,MDL XBAR4 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x240++0xB line.long 0x0 "CONTROLSS_MDLXBAR5_G0,MDL XBAR 5 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR5_G0_SEL,MDL XBAR5 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR5_G1,MDL XBAR 5 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR5_G1_SEL,MDL XBAR5 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR5_G2,MDL XBAR 5 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR5_G2_SEL,MDL XBAR5 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x280++0xB line.long 0x0 "CONTROLSS_MDLXBAR6_G0,MDL XBAR 6 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR6_G0_SEL,MDL XBAR6 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR6_G1,MDL XBAR 6 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR6_G1_SEL,MDL XBAR6 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR6_G2,MDL XBAR 6 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR6_G2_SEL,MDL XBAR6 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x2C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR7_G0,MDL XBAR 7 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR7_G0_SEL,MDL XBAR7 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR7_G1,MDL XBAR 7 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR7_G1_SEL,MDL XBAR7 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR7_G2,MDL XBAR 7 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR7_G2_SEL,MDL XBAR7 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x300++0xB line.long 0x0 "CONTROLSS_MDLXBAR8_G0,MDL XBAR 8 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR8_G0_SEL,MDL XBAR8 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR8_G1,MDL XBAR 8 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR8_G1_SEL,MDL XBAR8 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR8_G2,MDL XBAR 8 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR8_G2_SEL,MDL XBAR8 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x340++0xB line.long 0x0 "CONTROLSS_MDLXBAR9_G0,MDL XBAR 9 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR9_G0_SEL,MDL XBAR9 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR9_G1,MDL XBAR 9 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR9_G1_SEL,MDL XBAR9 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR9_G2,MDL XBAR 9 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR9_G2_SEL,MDL XBAR9 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x380++0xB line.long 0x0 "CONTROLSS_MDLXBAR10_G0,MDL XBAR 10 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR10_G0_SEL,MDL XBAR10 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR10_G1,MDL XBAR 10 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR10_G1_SEL,MDL XBAR10 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR10_G2,MDL XBAR 10 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR10_G2_SEL,MDL XBAR10 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x3C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR11_G0,MDL XBAR 11 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR11_G0_SEL,MDL XBAR11 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR11_G1,MDL XBAR 11 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR11_G1_SEL,MDL XBAR11 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR11_G2,MDL XBAR 11 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR11_G2_SEL,MDL XBAR11 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x400++0xB line.long 0x0 "CONTROLSS_MDLXBAR12_G0,MDL XBAR 12 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR12_G0_SEL,MDL XBAR12 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR12_G1,MDL XBAR 12 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR12_G1_SEL,MDL XBAR12 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR12_G2,MDL XBAR 12 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR12_G2_SEL,MDL XBAR12 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x440++0xB line.long 0x0 "CONTROLSS_MDLXBAR13_G0,MDL XBAR 13 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR13_G0_SEL,MDL XBAR13 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR13_G1,MDL XBAR 13 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR13_G1_SEL,MDL XBAR13 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR13_G2,MDL XBAR 13 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR13_G2_SEL,MDL XBAR13 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x480++0xB line.long 0x0 "CONTROLSS_MDLXBAR14_G0,MDL XBAR 14 Input Select." hexmask.long 0x0 0.--31. 1. "MDLXBAR14_G0_SEL,MDL XBAR14 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR14_G1,MDL XBAR 14 Input Select." hexmask.long 0x4 0.--31. 1. "MDLXBAR14_G1_SEL,MDL XBAR14 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR14_G2,MDL XBAR 14 Input Select." hexmask.long 0x8 0.--31. 1. "MDLXBAR14_G2_SEL,MDL XBAR14 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" group.long 0x4C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR15_G0,MDL XBAR 15 Input Select ." hexmask.long 0x0 0.--31. 1. "MDLXBAR15_G0_SEL,MDL XBAR15 G0 input bit select. Input source is PWMA sclk select1:PWMA sclk bit[x] selected0:PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR15_G1,MDL XBAR 15 Input Select ." hexmask.long 0x4 0.--31. 1. "MDLXBAR15_G1_SEL,MDL XBAR15 G1 input bit select. Input source is PWMB sclk select1:PWMB sclk bit[x] selected0:PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR15_G2,MDL XBAR 15 Input Select ." hexmask.long 0x8 0.--31. 1. "MDLXBAR15_G2_SEL,MDL XBAR15 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311:ICSS_PORT[y].GPO[x] selected.0:ICSS_PORT[y].GPO[x] is de-selected" tree.end tree "CONTROLSS_OUTPUTXBAR" base ad:0x502D8000 rgroup.long 0x10++0x3 line.long 0x0 "CONTROLSS_OUTPUTXBAR_STATUS,Output Signal Status." hexmask.long.word 0x0 0.--15. 1. "OUTPUTXBAR_STATUS_STS,Status" group.long 0x14++0x1F line.long 0x0 "CONTROLSS_OUTPUTXBAR_FLAGINVERT,Output Signal Invert Before Latch." hexmask.long.word 0x0 0.--15. 1. "OUTPUTXBAR_FLAGINVERT_INVERT,FlagInvert" line.long 0x4 "CONTROLSS_OUTPUTXBAR_FLAG,Output Signal Latched Flag." bitfld.long 0x4 15. "OUTPUTXBAR_FLAG_BIT15,Output XBAR flag" "0,1" bitfld.long 0x4 14. "OUTPUTXBAR_FLAG_BIT14,Output XBAR flag" "0,1" bitfld.long 0x4 13. "OUTPUTXBAR_FLAG_BIT13,Output XBAR flag" "0,1" newline bitfld.long 0x4 12. "OUTPUTXBAR_FLAG_BIT12,Output XBAR flag" "0,1" bitfld.long 0x4 11. "OUTPUTXBAR_FLAG_BIT11,Output XBAR flag" "0,1" bitfld.long 0x4 10. "OUTPUTXBAR_FLAG_BIT10,Output XBAR flag" "0,1" newline bitfld.long 0x4 9. "OUTPUTXBAR_FLAG_BIT9,Output XBAR flag" "0,1" bitfld.long 0x4 8. "OUTPUTXBAR_FLAG_BIT8,Output XBAR flag" "0,1" bitfld.long 0x4 7. "OUTPUTXBAR_FLAG_BIT7,Output XBAR flag" "0,1" newline bitfld.long 0x4 6. "OUTPUTXBAR_FLAG_BIT6,Output XBAR flag" "0,1" bitfld.long 0x4 5. "OUTPUTXBAR_FLAG_BIT5,Output XBAR flag" "0,1" bitfld.long 0x4 4. "OUTPUTXBAR_FLAG_BIT4,Output XBAR flag" "0,1" newline bitfld.long 0x4 3. "OUTPUTXBAR_FLAG_BIT3,Output XBAR flag" "0,1" bitfld.long 0x4 2. "OUTPUTXBAR_FLAG_BIT2,Output XBAR flag" "0,1" bitfld.long 0x4 1. "OUTPUTXBAR_FLAG_BIT1,Output XBAR flag" "0,1" newline bitfld.long 0x4 0. "OUTPUTXBAR_FLAG_BIT0,Output XBAR flag" "0,1" line.long 0x8 "CONTROLSS_OUTPUTXBAR_FLAG_CLR,Output Signal Latched Flag Clear." bitfld.long 0x8 15. "OUTPUTXBAR_FLAG_CLR_BIT15,Output XBAR flag clear" "0,1" bitfld.long 0x8 14. "OUTPUTXBAR_FLAG_CLR_BIT14,Output XBAR flag clear" "0,1" bitfld.long 0x8 13. "OUTPUTXBAR_FLAG_CLR_BIT13,Output XBAR flag clear" "0,1" newline bitfld.long 0x8 12. "OUTPUTXBAR_FLAG_CLR_BIT12,Output XBAR flag clear" "0,1" bitfld.long 0x8 11. "OUTPUTXBAR_FLAG_CLR_BIT11,Output XBAR flag clear" "0,1" bitfld.long 0x8 10. "OUTPUTXBAR_FLAG_CLR_BIT10,Output XBAR flag clear" "0,1" newline bitfld.long 0x8 9. "OUTPUTXBAR_FLAG_CLR_BIT9,Output XBAR flag clear" "0,1" bitfld.long 0x8 8. "OUTPUTXBAR_FLAG_CLR_BIT8,Output XBAR flag clear" "0,1" bitfld.long 0x8 7. "OUTPUTXBAR_FLAG_CLR_BIT7,Output XBAR flag clear" "0,1" newline bitfld.long 0x8 6. "OUTPUTXBAR_FLAG_CLR_BIT6,Output XBAR flag clear" "0,1" bitfld.long 0x8 5. "OUTPUTXBAR_FLAG_CLR_BIT5,Output XBAR flag clear" "0,1" bitfld.long 0x8 4. "OUTPUTXBAR_FLAG_CLR_BIT4,Output XBAR flag clear" "0,1" newline bitfld.long 0x8 3. "OUTPUTXBAR_FLAG_CLR_BIT3,Output XBAR flag clear" "0,1" bitfld.long 0x8 2. "OUTPUTXBAR_FLAG_CLR_BIT2,Output XBAR flag clear" "0,1" bitfld.long 0x8 1. "OUTPUTXBAR_FLAG_CLR_BIT1,Output XBAR flag clear" "0,1" newline bitfld.long 0x8 0. "OUTPUTXBAR_FLAG_CLR_BIT0,Output XBAR flag clear" "0,1" line.long 0xC "CONTROLSS_OUTPUTXBAR_FLAGFORCE,Output Signal Latched Flag Force." hexmask.long.word 0xC 0.--15. 1. "OUTPUTXBAR_FLAGFORCE_FRC,FlagForce" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTLATCH,Output Signal Select Latch." hexmask.long.word 0x10 0.--15. 1. "OUTPUTXBAR_OUTLATCH_LATCHSEL,OutLatch" line.long 0x14 "CONTROLSS_OUTPUTXBAR_OUTSTRETCH,Output Signal Stretched Pulse Version Select." hexmask.long.word 0x14 0.--15. 1. "OUTPUTXBAR_OUTSTRETCH_STRETCHSEL,OutStretch" line.long 0x18 "CONTROLSS_OUTPUTXBAR_OUTLENGTH,Output Signal Stretched Pulse Length Select." hexmask.long.word 0x18 0.--15. 1. "OUTPUTXBAR_OUTLENGTH_LENGTHSEL,OutLength" line.long 0x1C "CONTROLSS_OUTPUTXBAR_OUTINVERT,Output Signal Invert Select." hexmask.long.word 0x1C 0.--15. 1. "OUTPUTXBAR_OUTINVERT_OUTINVERT,OutInvert" group.long 0x100++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR0_G0,OUTPUT XBAR 0 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR0_G0_SEL,G0: PWM XBAR0 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR0_G1,OUTPUT XBAR 0 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR0_G1_SEL,G1: OUTPUT XBAR0 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR0_G2,OUTPUT XBAR 0 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR0_G2_SEL,G2: OUTPUT XBAR0 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR0_G3,OUTPUT XBAR 0 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR0_G3_SEL,G3: OUTPUT XBAR0 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR0_G4,OUTPUT XBAR 0 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR0_G4_SEL,G4: OUTPUT XBAR0 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR0_G5,OUTPUT XBAR 0 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR0_G5_SEL,G5: OUTPUT XBAR0 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR0_G6,OUTPUT XBAR 0 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR0_G6_SEL,G6: OUTPUT XBAR0 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR0_G7,OUTPUT XBAR 0 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR0_G7_SEL,G7: OUTPUT XBAR0 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR0_G8,OUTPUT XBAR 0 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR0_G8_SEL,G8: OUTPUT XBAR0 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR0_G9,OUTPUT XBAR 0 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR0_G9_SEL,G9: OUTPUT XBAR0 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR0_G10,OUTPUT XBAR 0 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR0_G10_SEL,G10: OUTPUT XBAR0 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x140++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR1_G0,OUTPUT XBAR 1 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR1_G0_SEL,G0: PWM XBAR1 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR1_G1,OUTPUT XBAR 1 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR1_G1_SEL,G1: OUTPUT XBAR1 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR1_G2,OUTPUT XBAR 1 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR1_G2_SEL,G2: OUTPUT XBAR1 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR1_G3,OUTPUT XBAR 1 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR1_G3_SEL,G3: OUTPUT XBAR1 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR1_G4,OUTPUT XBAR 1 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR1_G4_SEL,G4: OUTPUT XBAR1 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR1_G5,OUTPUT XBAR 1 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR1_G5_SEL,G5: OUTPUT XBAR1 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR1_G6,OUTPUT XBAR 1 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR1_G6_SEL,G6: OUTPUT XBAR1 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR1_G7,OUTPUT XBAR 1 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR1_G7_SEL,G7: OUTPUT XBAR1 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR1_G8,OUTPUT XBAR 1 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR1_G8_SEL,G8: OUTPUT XBAR1 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR1_G9,OUTPUT XBAR 1 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR1_G9_SEL,G9: OUTPUT XBAR1 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR1_G10,OUTPUT XBAR 1 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR1_G10_SEL,G10: OUTPUT XBAR1 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x180++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR2_G0,OUTPUT XBAR 2 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR2_G0_SEL,G0: PWM XBAR2 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR2_G1,OUTPUT XBAR 2 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR2_G1_SEL,G1: OUTPUT XBAR2 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR2_G2,OUTPUT XBAR 2 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR2_G2_SEL,G2: OUTPUT XBAR2 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR2_G3,OUTPUT XBAR 2 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR2_G3_SEL,G3: OUTPUT XBAR2 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR2_G4,OUTPUT XBAR 2 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR2_G4_SEL,G4: OUTPUT XBAR2 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR2_G5,OUTPUT XBAR 2 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR2_G5_SEL,G5: OUTPUT XBAR2 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR2_G6,OUTPUT XBAR 2 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR2_G6_SEL,G6: OUTPUT XBAR2 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR2_G7,OUTPUT XBAR 2 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR2_G7_SEL,G7: OUTPUT XBAR2 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR2_G8,OUTPUT XBAR 2 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR2_G8_SEL,G8: OUTPUT XBAR2 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR2_G9,OUTPUT XBAR 2 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR2_G9_SEL,G9: OUTPUT XBAR2 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR2_G10,OUTPUT XBAR 2 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR2_G10_SEL,G10: OUTPUT XBAR2 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x1C0++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR3_G0,OUTPUT XBAR 3 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR3_G0_SEL,G0: PWM XBAR3 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR3_G1,OUTPUT XBAR 3 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR3_G1_SEL,G1: OUTPUT XBAR3 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR3_G2,OUTPUT XBAR 3 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR3_G2_SEL,G2: OUTPUT XBAR3 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR3_G3,OUTPUT XBAR 3 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR3_G3_SEL,G3: OUTPUT XBAR3 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR3_G4,OUTPUT XBAR 3 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR3_G4_SEL,G4: OUTPUT XBAR3 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR3_G5,OUTPUT XBAR 3 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR3_G5_SEL,G5: OUTPUT XBAR3 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR3_G6,OUTPUT XBAR 3 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR3_G6_SEL,G6: OUTPUT XBAR3 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR3_G7,OUTPUT XBAR 3 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR3_G7_SEL,G7: OUTPUT XBAR3 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR3_G8,OUTPUT XBAR 3 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR3_G8_SEL,G8: OUTPUT XBAR3 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR3_G9,OUTPUT XBAR 3 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR3_G9_SEL,G9: OUTPUT XBAR3 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR3_G10,OUTPUT XBAR 3 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR3_G10_SEL,G10: OUTPUT XBAR3 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x200++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR4_G0,OUTPUT XBAR 4 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR4_G0_SEL,G0: PWM XBAR4 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR4_G1,OUTPUT XBAR 4 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR4_G1_SEL,G1: OUTPUT XBAR4 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR4_G2,OUTPUT XBAR 4 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR4_G2_SEL,G2: OUTPUT XBAR4 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR4_G3,OUTPUT XBAR 4 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR4_G3_SEL,G3: OUTPUT XBAR4 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR4_G4,OUTPUT XBAR 4 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR4_G4_SEL,G4: OUTPUT XBAR4 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR4_G5,OUTPUT XBAR 4 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR4_G5_SEL,G5: OUTPUT XBAR4 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR4_G6,OUTPUT XBAR 4 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR4_G6_SEL,G6: OUTPUT XBAR4 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR4_G7,OUTPUT XBAR 4 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR4_G7_SEL,G7: OUTPUT XBAR4 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR4_G8,OUTPUT XBAR 4 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR4_G8_SEL,G8: OUTPUT XBAR4 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR4_G9,OUTPUT XBAR 4 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR4_G9_SEL,G9: OUTPUT XBAR4 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR4_G10,OUTPUT XBAR 4 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR4_G10_SEL,G10: OUTPUT XBAR4 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x240++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR5_G0,OUTPUT XBAR 5 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR5_G0_SEL,G0: PWM XBAR5 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR5_G1,OUTPUT XBAR 5 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR5_G1_SEL,G1: OUTPUT XBAR5 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR5_G2,OUTPUT XBAR 5 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR5_G2_SEL,G2: OUTPUT XBAR5 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR5_G3,OUTPUT XBAR 5 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR5_G3_SEL,G3: OUTPUT XBAR5 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR5_G4,OUTPUT XBAR 5 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR5_G4_SEL,G4: OUTPUT XBAR5 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR5_G5,OUTPUT XBAR 5 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR5_G5_SEL,G5: OUTPUT XBAR5 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR5_G6,OUTPUT XBAR 5 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR5_G6_SEL,G6: OUTPUT XBAR5 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR5_G7,OUTPUT XBAR 5 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR5_G7_SEL,G7: OUTPUT XBAR5 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR5_G8,OUTPUT XBAR 5 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR5_G8_SEL,G8: OUTPUT XBAR5 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR5_G9,OUTPUT XBAR 5 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR5_G9_SEL,G9: OUTPUT XBAR5 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR5_G10,OUTPUT XBAR 5 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR5_G10_SEL,G10: OUTPUT XBAR5 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x280++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR6_G0,OUTPUT XBAR 6 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR6_G0_SEL,G0: PWM XBAR6 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR6_G1,OUTPUT XBAR 6 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR6_G1_SEL,G1: OUTPUT XBAR6 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR6_G2,OUTPUT XBAR 6 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR6_G2_SEL,G2: OUTPUT XBAR6 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR6_G3,OUTPUT XBAR 6 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR6_G3_SEL,G3: OUTPUT XBAR6 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR6_G4,OUTPUT XBAR 6 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR6_G4_SEL,G4: OUTPUT XBAR6 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR6_G5,OUTPUT XBAR 6 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR6_G5_SEL,G5: OUTPUT XBAR6 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR6_G6,OUTPUT XBAR 6 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR6_G6_SEL,G6: OUTPUT XBAR6 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR6_G7,OUTPUT XBAR 6 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR6_G7_SEL,G7: OUTPUT XBAR6 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR6_G8,OUTPUT XBAR 6 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR6_G8_SEL,G8: OUTPUT XBAR6 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR6_G9,OUTPUT XBAR 6 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR6_G9_SEL,G9: OUTPUT XBAR6 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR6_G10,OUTPUT XBAR 6 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR6_G10_SEL,G10: OUTPUT XBAR6 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x2C0++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR7_G0,OUTPUT XBAR 7 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR7_G0_SEL,G0: PWM XBAR7 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR7_G1,OUTPUT XBAR 7 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR7_G1_SEL,G1: OUTPUT XBAR7 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR7_G2,OUTPUT XBAR 7 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR7_G2_SEL,G2: OUTPUT XBAR7 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR7_G3,OUTPUT XBAR 7 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR7_G3_SEL,G3: OUTPUT XBAR7 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR7_G4,OUTPUT XBAR 7 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR7_G4_SEL,G4: OUTPUT XBAR7 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR7_G5,OUTPUT XBAR 7 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR7_G5_SEL,G5: OUTPUT XBAR7 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR7_G6,OUTPUT XBAR 7 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR7_G6_SEL,G6: OUTPUT XBAR7 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR7_G7,OUTPUT XBAR 7 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR7_G7_SEL,G7: OUTPUT XBAR7 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR7_G8,OUTPUT XBAR 7 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR7_G8_SEL,G8: OUTPUT XBAR7 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR7_G9,OUTPUT XBAR 7 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR7_G9_SEL,G9: OUTPUT XBAR7 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR7_G10,OUTPUT XBAR 7 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR7_G10_SEL,G10: OUTPUT XBAR7 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x300++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR8_G0,OUTPUT XBAR 8 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR8_G0_SEL,G0: PWM XBAR8 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR8_G1,OUTPUT XBAR 8 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR8_G1_SEL,G1: OUTPUT XBAR8 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR8_G2,OUTPUT XBAR 8 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR8_G2_SEL,G2: OUTPUT XBAR8 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR8_G3,OUTPUT XBAR 8 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR8_G3_SEL,G3: OUTPUT XBAR8 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR8_G4,OUTPUT XBAR 8 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR8_G4_SEL,G4: OUTPUT XBAR8 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR8_G5,OUTPUT XBAR 8 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR8_G5_SEL,G5: OUTPUT XBAR8 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR8_G6,OUTPUT XBAR 8 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR8_G6_SEL,G6: OUTPUT XBAR8 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR8_G7,OUTPUT XBAR 8 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR8_G7_SEL,G7: OUTPUT XBAR8 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR8_G8,OUTPUT XBAR 8 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR8_G8_SEL,G8: OUTPUT XBAR8 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR8_G9,OUTPUT XBAR 8 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR8_G9_SEL,G9: OUTPUT XBAR8 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR8_G10,OUTPUT XBAR 8 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR8_G10_SEL,G10: OUTPUT XBAR8 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x340++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR9_G0,OUTPUT XBAR 9 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR9_G0_SEL,G0: PWM XBAR9 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR9_G1,OUTPUT XBAR 9 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR9_G1_SEL,G1: OUTPUT XBAR9 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR9_G2,OUTPUT XBAR 9 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR9_G2_SEL,G2: OUTPUT XBAR9 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR9_G3,OUTPUT XBAR 9 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR9_G3_SEL,G3: OUTPUT XBAR9 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR9_G4,OUTPUT XBAR 9 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR9_G4_SEL,G4: OUTPUT XBAR9 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR9_G5,OUTPUT XBAR 9 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR9_G5_SEL,G5: OUTPUT XBAR9 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR9_G6,OUTPUT XBAR 9 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR9_G6_SEL,G6: OUTPUT XBAR9 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR9_G7,OUTPUT XBAR 9 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR9_G7_SEL,G7: OUTPUT XBAR9 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR9_G8,OUTPUT XBAR 9 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR9_G8_SEL,G8: OUTPUT XBAR9 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR9_G9,OUTPUT XBAR 9 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR9_G9_SEL,G9: OUTPUT XBAR9 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR9_G10,OUTPUT XBAR 9 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR9_G10_SEL,G10: OUTPUT XBAR9 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x380++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR10_G0,OUTPUT XBAR 10 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR10_G0_SEL,G0: PWM XBAR10 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR10_G1,OUTPUT XBAR 10 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR10_G1_SEL,G1: OUTPUT XBAR10 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR10_G2,OUTPUT XBAR 10 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR10_G2_SEL,G2: OUTPUT XBAR10 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR10_G3,OUTPUT XBAR 10 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR10_G3_SEL,G3: OUTPUT XBAR10 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR10_G4,OUTPUT XBAR 10 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR10_G4_SEL,G4: OUTPUT XBAR10 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR10_G5,OUTPUT XBAR 10 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR10_G5_SEL,G5: OUTPUT XBAR10 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR10_G6,OUTPUT XBAR 10 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR10_G6_SEL,G6: OUTPUT XBAR10 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR10_G7,OUTPUT XBAR 10 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR10_G7_SEL,G7: OUTPUT XBAR10 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR10_G8,OUTPUT XBAR 10 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR10_G8_SEL,G8: OUTPUT XBAR10 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR10_G9,OUTPUT XBAR 10 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR10_G9_SEL,G9: OUTPUT XBAR10 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR10_G10,OUTPUT XBAR 10 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR10_G10_SEL,G10: OUTPUT XBAR10 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x3C0++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR11_G0,OUTPUT XBAR 11 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR11_G0_SEL,G0: PWM XBAR11 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR11_G1,OUTPUT XBAR 11 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR11_G1_SEL,G1: OUTPUT XBAR11 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR11_G2,OUTPUT XBAR 11 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR11_G2_SEL,G2: OUTPUT XBAR11 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR11_G3,OUTPUT XBAR 11 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR11_G3_SEL,G3: OUTPUT XBAR11 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR11_G4,OUTPUT XBAR 11 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR11_G4_SEL,G4: OUTPUT XBAR11 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR11_G5,OUTPUT XBAR 11 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR11_G5_SEL,G5: OUTPUT XBAR11 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR11_G6,OUTPUT XBAR 11 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR11_G6_SEL,G6: OUTPUT XBAR11 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR11_G7,OUTPUT XBAR 11 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR11_G7_SEL,G7: OUTPUT XBAR11 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR11_G8,OUTPUT XBAR 11 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR11_G8_SEL,G8: OUTPUT XBAR11 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR11_G9,OUTPUT XBAR 11 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR11_G9_SEL,G9: OUTPUT XBAR11 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR11_G10,OUTPUT XBAR 11 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR11_G10_SEL,G10: OUTPUT XBAR11 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x400++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR12_G0,OUTPUT XBAR 12 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR12_G0_SEL,G0: PWM XBAR12 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR12_G1,OUTPUT XBAR 12 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR12_G1_SEL,G1: OUTPUT XBAR12 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR12_G2,OUTPUT XBAR 12 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR12_G2_SEL,G2: OUTPUT XBAR12 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR12_G3,OUTPUT XBAR 12 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR12_G3_SEL,G3: OUTPUT XBAR12 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR12_G4,OUTPUT XBAR 12 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR12_G4_SEL,G4: OUTPUT XBAR12 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR12_G5,OUTPUT XBAR 12 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR12_G5_SEL,G5: OUTPUT XBAR12 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR12_G6,OUTPUT XBAR 12 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR12_G6_SEL,G6: OUTPUT XBAR12 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR12_G7,OUTPUT XBAR 12 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR12_G7_SEL,G7: OUTPUT XBAR12 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR12_G8,OUTPUT XBAR 12 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR12_G8_SEL,G8: OUTPUT XBAR12 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR12_G9,OUTPUT XBAR 12 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR12_G9_SEL,G9: OUTPUT XBAR12 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR12_G10,OUTPUT XBAR 12 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR12_G10_SEL,G10: OUTPUT XBAR12 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x440++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR13_G0,OUTPUT XBAR 13 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR13_G0_SEL,G0: PWM XBAR13 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR13_G1,OUTPUT XBAR 13 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR13_G1_SEL,G1: OUTPUT XBAR13 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR13_G2,OUTPUT XBAR 13 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR13_G2_SEL,G2: OUTPUT XBAR13 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR13_G3,OUTPUT XBAR 13 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR13_G3_SEL,G3: OUTPUT XBAR13 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR13_G4,OUTPUT XBAR 13 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR13_G4_SEL,G4: OUTPUT XBAR13 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR13_G5,OUTPUT XBAR 13 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR13_G5_SEL,G5: OUTPUT XBAR13 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR13_G6,OUTPUT XBAR 13 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR13_G6_SEL,G6: OUTPUT XBAR13 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR13_G7,OUTPUT XBAR 13 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR13_G7_SEL,G7: OUTPUT XBAR13 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR13_G8,OUTPUT XBAR 13 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR13_G8_SEL,G8: OUTPUT XBAR13 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR13_G9,OUTPUT XBAR 13 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR13_G9_SEL,G9: OUTPUT XBAR13 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR13_G10,OUTPUT XBAR 13 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR13_G10_SEL,G10: OUTPUT XBAR13 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x480++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR14_G0,OUTPUT XBAR 14 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR14_G0_SEL,G0: PWM XBAR14 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR14_G1,OUTPUT XBAR 14 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR14_G1_SEL,G1: OUTPUT XBAR14 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR14_G2,OUTPUT XBAR 14 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR14_G2_SEL,G2: OUTPUT XBAR14 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR14_G3,OUTPUT XBAR 14 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR14_G3_SEL,G3: OUTPUT XBAR14 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR14_G4,OUTPUT XBAR 14 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR14_G4_SEL,G4: OUTPUT XBAR14 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR14_G5,OUTPUT XBAR 14 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR14_G5_SEL,G5: OUTPUT XBAR14 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR14_G6,OUTPUT XBAR 14 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR14_G6_SEL,G6: OUTPUT XBAR14 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR14_G7,OUTPUT XBAR 14 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR14_G7_SEL,G7: OUTPUT XBAR14 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR14_G8,OUTPUT XBAR 14 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR14_G8_SEL,G8: OUTPUT XBAR14 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR14_G9,OUTPUT XBAR 14 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR14_G9_SEL,G9: OUTPUT XBAR14 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR14_G10,OUTPUT XBAR 14 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR14_G10_SEL,G10: OUTPUT XBAR14 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." group.long 0x4C0++0x2B line.long 0x0 "CONTROLSS_OUTPUTXBAR15_G0,OUTPUT XBAR 15 Input Select." hexmask.long 0x0 0.--31. 1. "OUTPUTXBAR15_G0_SEL,G0: PWM XBAR15 G0 input bit select. Input source is PWM[x].TRIPOUT1:PWM[x] TRIPOUT selected0:PWM[x] TRIPOUT is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x4 "CONTROLSS_OUTPUTXBAR15_G1,OUTPUT XBAR 15 Input Select." hexmask.long 0x4 0.--31. 1. "OUTPUTXBAR15_G1_SEL,G1: OUTPUT XBAR15 G1 input bit select. Input source is PWM[x].SOCA1:PWM[x] SOCA selected0:PWM[x] SOCA is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0x8 "CONTROLSS_OUTPUTXBAR15_G2,OUTPUT XBAR 15 Input Select." hexmask.long 0x8 0.--31. 1. "OUTPUTXBAR15_G2_SEL,G2: OUTPUT XBAR15 G2 input bit select. Input source is PWM[x].SOCB1:PWM[x] SOCB selected0:PWM[x] SOCB is de-selected x can have value from 0 to 31 corresponding to each PWM instance" line.long 0xC "CONTROLSS_OUTPUTXBAR15_G3,OUTPUT XBAR 15 Input Select." hexmask.long 0xC 0.--31. 1. "OUTPUTXBAR15_G3_SEL,G3: OUTPUT XBAR15 G3 input bit select. Input source is DEL[x].ACTIVE1:DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x10 "CONTROLSS_OUTPUTXBAR15_G4,OUTPUT XBAR 15 Input Select." hexmask.long 0x10 0.--31. 1. "OUTPUTXBAR15_G4_SEL,G4: OUTPUT XBAR15 G4 input bit select. Input source is DEL[x].TRIP1:DEL[x] TRIP selected0: DEL[x] TRIP is de-selected x can have value from 0 to 31 corresponding to each DEL instance" line.long 0x14 "CONTROLSS_OUTPUTXBAR15_G5,OUTPUT XBAR 15 Input Select." hexmask.long.tbyte 0x14 0.--23. 1. "OUTPUTXBAR15_G5_SEL,G5: OUTPUT XBAR15 G5 input bit.." line.long 0x18 "CONTROLSS_OUTPUTXBAR15_G6,OUTPUT XBAR 15 Input Select." hexmask.long.tbyte 0x18 0.--19. 1. "OUTPUTXBAR15_G6_SEL,G6: OUTPUT XBAR15 G6 Input.." line.long 0x1C "CONTROLSS_OUTPUTXBAR15_G7,OUTPUT XBAR 15 Input Select." hexmask.long.tbyte 0x1C 0.--19. 1. "OUTPUTXBAR15_G7_SEL,G7: OUTPUT XBAR15 G7 Input.." line.long 0x20 "CONTROLSS_OUTPUTXBAR15_G8,OUTPUT XBAR 15 Input Select." hexmask.long 0x20 0.--27. 1. "OUTPUTXBAR15_G8_SEL,G8: OUTPUT XBAR15 G8 Input Select0:ADC0.EVT11:ADC0.EVT22:ADC0.EVT33:ADC0.EVT44:ADC1.EVT15:ADC1.EVT26:ADC1.EVT37:ADC1 EVT48:ADC2.EVT19:ADC2.." line.long 0x24 "CONTROLSS_OUTPUTXBAR15_G9,OUTPUT XBAR 15 Input Select." hexmask.long 0x24 0.--25. 1. "OUTPUTXBAR15_G9_SEL,G9: OUTPUT XBAR15 G9 Input.." line.long 0x28 "CONTROLSS_OUTPUTXBAR15_G10,OUTPUT XBAR 15 Input Select." hexmask.long.tbyte 0x28 0.--21. 1. "OUTPUTXBAR15_G10_SEL,G10: OUTPUT XBAR15 G10 Input Select[3:0]: FSIRX0.RX_TRIG[3:0][7:4]: FSIRX1.RX_TRIG[3:0][11:8]: FSIRX2.RX_TRIG[3:0][15:12]:.." tree.end tree "CONTROLSS_PWMSYNCOUTXBAR" base ad:0x502D2000 group.long 0x100++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR0_G0,EPWM pwmsyncout XBAR0 select." hexmask.long 0x0 0.--31. 1. "PWMSYNCOUTXBAR0_G0_SEL,EPWM pwmsyncout XBAR0 select1:PWM[x] SYNCOUT selected0:PWM[x] SYNCOUT is de-selected" group.long 0x140++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR1_G0,EPWM pwmsyncout XBAR1 select." hexmask.long 0x0 0.--31. 1. "PWMSYNCOUTXBAR1_G0_SEL,EPWM pwmsyncout XBAR1 select1:PWM[x] SYNCOUT selected0:PWM[x] SYNCOUT is de-selected" group.long 0x180++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR2_G0,EPWM pwmsyncout XBAR2 select." hexmask.long 0x0 0.--31. 1. "PWMSYNCOUTXBAR2_G0_SEL,EPWM pwmsyncout XBAR2 select1:PWM[x] SYNCOUT selected0:PWM[x] SYNCOUT is de-selected" group.long 0x1C0++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR3_G0,EPWM pwmsyncout XBAR2 select." hexmask.long 0x0 0.--31. 1. "PWMSYNCOUTXBAR3_G0_SEL,EPWM pwmsyncout XBAR3 select1:PWM[x] SYNCOUT selected0:PWM[x] SYNCOUT is de-selected" group.long 0x200++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR0_G1,EPWM pwmsyncout XBAR3 select." hexmask.long.word 0x0 0.--15. 1. "PWMSYNCOUTXBAR0_G1_SEL,EPWM pwmsyncout XBAR0 select1:ECAP[x] SYNCOUT selected0:ECAP[x] SYNCOUT is de-selected" group.long 0x240++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR1_G1,EPWM pwmsyncout XBAR3 select." hexmask.long.word 0x0 0.--15. 1. "PWMSYNCOUTXBAR1_G1_SEL,EPWM pwmsyncout XBAR1 select1:ECAP[x] SYNCOUT selected0:ECAP[x] SYNCOUT is de-selected" group.long 0x280++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR2_G1,EPWM pwmsyncout XBAR0 select." hexmask.long.word 0x0 0.--15. 1. "PWMSYNCOUTXBAR2_G1_SEL,EPWM pwmsyncout XBAR2 select1:ECAP[x] SYNCOUT selected0:ECAP[x] SYNCOUT is de-selected" group.long 0x2C0++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR3_G1,EPWM pwmsyncout XBAR1 select." hexmask.long.word 0x0 0.--15. 1. "PWMSYNCOUTXBAR3_G1_SEL,EPWM pwmsyncout XBAR3 select1:ECAP[x] SYNCOUT selected0:ECAP[x] SYNCOUT is de-selected" tree.end tree "CONTROLSS_PWMXBAR" base ad:0x502D1000 rgroup.long 0x10++0x3 line.long 0x0 "CONTROLSS_PWMXBAR_STATUS,Output Signal Status." hexmask.long 0x0 0.--29. 1. "PWMXBAR_STATUS_STS,Output Signal Status" group.long 0x14++0xB line.long 0x0 "CONTROLSS_PWMXBAR_FLAGINVERT,Output Signal Invert Before Latch." hexmask.long 0x0 0.--29. 1. "PWMXBAR_FLAGINVERT_INVERT,Output Signal Invert Before Latch" line.long 0x4 "CONTROLSS_PWMXBAR_FLAG,Output Signal Latched Flag." bitfld.long 0x4 29. "PWMXBAR_FLAG_BIT29,Output Signal Latched Flag" "0,1" bitfld.long 0x4 28. "PWMXBAR_FLAG_BIT28,Output Signal Latched Flag" "0,1" bitfld.long 0x4 27. "PWMXBAR_FLAG_BIT27,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 26. "PWMXBAR_FLAG_BIT26,Output Signal Latched Flag" "0,1" bitfld.long 0x4 25. "PWMXBAR_FLAG_BIT25,Output Signal Latched Flag" "0,1" bitfld.long 0x4 24. "PWMXBAR_FLAG_BIT24,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 23. "PWMXBAR_FLAG_BIT23,Output Signal Latched Flag" "0,1" bitfld.long 0x4 22. "PWMXBAR_FLAG_BIT22,Output Signal Latched Flag" "0,1" bitfld.long 0x4 21. "PWMXBAR_FLAG_BIT21,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 20. "PWMXBAR_FLAG_BIT20,Output Signal Latched Flag" "0,1" bitfld.long 0x4 19. "PWMXBAR_FLAG_BIT19,Output Signal Latched Flag" "0,1" bitfld.long 0x4 18. "PWMXBAR_FLAG_BIT18,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 17. "PWMXBAR_FLAG_BIT17,Output Signal Latched Flag" "0,1" bitfld.long 0x4 16. "PWMXBAR_FLAG_BIT16,Output Signal Latched Flag" "0,1" bitfld.long 0x4 15. "PWMXBAR_FLAG_BIT15,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 14. "PWMXBAR_FLAG_BIT14,Output Signal Latched Flag" "0,1" bitfld.long 0x4 13. "PWMXBAR_FLAG_BIT13,Output Signal Latched Flag" "0,1" bitfld.long 0x4 12. "PWMXBAR_FLAG_BIT12,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 11. "PWMXBAR_FLAG_BIT11,Output Signal Latched Flag" "0,1" bitfld.long 0x4 10. "PWMXBAR_FLAG_BIT10,Output Signal Latched Flag" "0,1" bitfld.long 0x4 9. "PWMXBAR_FLAG_BIT9,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 8. "PWMXBAR_FLAG_BIT8,Output Signal Latched Flag" "0,1" bitfld.long 0x4 7. "PWMXBAR_FLAG_BIT7,Output Signal Latched Flag" "0,1" bitfld.long 0x4 6. "PWMXBAR_FLAG_BIT6,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 5. "PWMXBAR_FLAG_BIT5,Output Signal Latched Flag" "0,1" bitfld.long 0x4 4. "PWMXBAR_FLAG_BIT4,Output Signal Latched Flag" "0,1" bitfld.long 0x4 3. "PWMXBAR_FLAG_BIT3,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 2. "PWMXBAR_FLAG_BIT2,Output Signal Latched Flag" "0,1" bitfld.long 0x4 1. "PWMXBAR_FLAG_BIT1,Output Signal Latched Flag" "0,1" bitfld.long 0x4 0. "PWMXBAR_FLAG_BIT0,Output Signal Latched Flag" "0,1" line.long 0x8 "CONTROLSS_PWMXBAR_FLAG_CLR,Output Signal Latched Flag Clear." bitfld.long 0x8 29. "PWMXBAR_FLAG_CLR_BIT29,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 28. "PWMXBAR_FLAG_CLR_BIT28,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 27. "PWMXBAR_FLAG_CLR_BIT27,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 26. "PWMXBAR_FLAG_CLR_BIT26,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 25. "PWMXBAR_FLAG_CLR_BIT25,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 24. "PWMXBAR_FLAG_CLR_BIT24,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 23. "PWMXBAR_FLAG_CLR_BIT23,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 22. "PWMXBAR_FLAG_CLR_BIT22,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 21. "PWMXBAR_FLAG_CLR_BIT21,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 20. "PWMXBAR_FLAG_CLR_BIT20,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 19. "PWMXBAR_FLAG_CLR_BIT19,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 18. "PWMXBAR_FLAG_CLR_BIT18,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 17. "PWMXBAR_FLAG_CLR_BIT17,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 16. "PWMXBAR_FLAG_CLR_BIT16,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 15. "PWMXBAR_FLAG_CLR_BIT15,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 14. "PWMXBAR_FLAG_CLR_BIT14,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 13. "PWMXBAR_FLAG_CLR_BIT13,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 12. "PWMXBAR_FLAG_CLR_BIT12,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 11. "PWMXBAR_FLAG_CLR_BIT11,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 10. "PWMXBAR_FLAG_CLR_BIT10,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 9. "PWMXBAR_FLAG_CLR_BIT9,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 8. "PWMXBAR_FLAG_CLR_BIT8,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 7. "PWMXBAR_FLAG_CLR_BIT7,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 6. "PWMXBAR_FLAG_CLR_BIT6,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 5. "PWMXBAR_FLAG_CLR_BIT5,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 4. "PWMXBAR_FLAG_CLR_BIT4,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 3. "PWMXBAR_FLAG_CLR_BIT3,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 2. "PWMXBAR_FLAG_CLR_BIT2,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 1. "PWMXBAR_FLAG_CLR_BIT1,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 0. "PWMXBAR_FLAG_CLR_BIT0,Output Signal Latched Flag Clear" "0,1" group.long 0x100++0x27 line.long 0x0 "CONTROLSS_PWMXBAR0_G0,PWM XBAR 0 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR0_G0_SEL,PWM XBAR0 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR0_G1,PWM XBAR 0 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR0_G1_SEL,PWM XBAR0 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR0_G2,PWM XBAR 0 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR0_G2_SEL,PWM XBAR0 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR0_G3,PWM XBAR 0 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR0_G3_SEL,PWM XBAR0 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR0_G4,PWM XBAR 0 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR0_G4_SEL,PWM XBAR0 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR0_G5,PWM XBAR 0 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR0_G5_SEL,PWM XBAR0 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR0_G6,PWM XBAR 0 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR0_G6_SEL,PWM XBAR0 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR0_G7,PWM XBAR 0 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR0_G7_SEL,PWM XBAR0 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR0_G8,PWM XBAR 0 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR0_G8_SEL,PWM XBAR0 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR0_G9,PWM XBAR 0 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR0_G9_SEL,PWM XBAR0 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x140++0x27 line.long 0x0 "CONTROLSS_PWMXBAR1_G0,PWM XBAR 1 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR1_G0_SEL,PWM XBAR1 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR1_G1,PWM XBAR 1 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR1_G1_SEL,PWM XBAR1 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR1_G2,PWM XBAR 1 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR1_G2_SEL,PWM XBAR1 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR1_G3,PWM XBAR 1 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR1_G3_SEL,PWM XBAR1 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR1_G4,PWM XBAR 1 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR1_G4_SEL,PWM XBAR1 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR1_G5,PWM XBAR 1 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR1_G5_SEL,PWM XBAR1 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR1_G6,PWM XBAR 1 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR1_G6_SEL,PWM XBAR1 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR1_G7,PWM XBAR 1 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR1_G7_SEL,PWM XBAR1 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR1_G8,PWM XBAR 1 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR1_G8_SEL,PWM XBAR1 G8 Input Select0:EQEP0.ERR1:EQEP1.ERR2:EQEP2.ERR63:FSIRX0.RX_TRIG4107:FSIRX1.RX_TRIG41411:FSIRX2.RX_TRIG41815:FSIRX3.RX_TRIG4 3119:ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR1_G9,PWM XBAR 1 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR1_G9_SEL,PWM XBAR1 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x180++0x27 line.long 0x0 "CONTROLSS_PWMXBAR2_G0,PWM XBAR 2 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR2_G0_SEL,PWM XBAR2 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR2_G1,PWM XBAR 2 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR2_G1_SEL,PWM XBAR2 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR2_G2,PWM XBAR 2 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR2_G2_SEL,PWM XBAR2 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR2_G3,PWM XBAR 2 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR2_G3_SEL,PWM XBAR2 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR2_G4,PWM XBAR 2 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR2_G4_SEL,PWM XBAR2 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR2_G5,PWM XBAR 2 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR2_G5_SEL,PWM XBAR2 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR2_G6,PWM XBAR 2 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR2_G6_SEL,PWM XBAR2 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR2_G7,PWM XBAR 2 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR2_G7_SEL,PWM XBAR2 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR2_G8,PWM XBAR 2 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR2_G8_SEL,PWM XBAR2 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR2_G9,PWM XBAR 2 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR2_G9_SEL,PWM XBAR2 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x1C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR3_G0,PWM XBAR 3 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR3_G0_SEL,PWM XBAR3 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR3_G1,PWM XBAR 3 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR3_G1_SEL,PWM XBAR3 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR3_G2,PWM XBAR 3 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR3_G2_SEL,PWM XBAR3 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR3_G3,PWM XBAR 3 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR3_G3_SEL,PWM XBAR3 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR3_G4,PWM XBAR 3 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR3_G4_SEL,PWM XBAR3 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR3_G5,PWM XBAR 3 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR3_G5_SEL,PWM XBAR3 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR3_G6,PWM XBAR 3 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR3_G6_SEL,PWM XBAR3 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR3_G7,PWM XBAR 3 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR3_G7_SEL,PWM XBAR3 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR3_G8,PWM XBAR 3 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR3_G8_SEL,PWM XBAR3 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR3_G9,PWM XBAR 3 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR3_G9_SEL,PWM XBAR3 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x200++0x27 line.long 0x0 "CONTROLSS_PWMXBAR4_G0,PWM XBAR 4 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR4_G0_SEL,PWM XBAR4 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR4_G1,PWM XBAR 4 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR4_G1_SEL,PWM XBAR4 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR4_G2,PWM XBAR 4 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR4_G2_SEL,PWM XBAR4 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR4_G3,PWM XBAR 4 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR4_G3_SEL,PWM XBAR4 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR4_G4,PWM XBAR 4 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR4_G4_SEL,PWM XBAR4 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR4_G5,PWM XBAR 4 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR4_G5_SEL,PWM XBAR4 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR4_G6,PWM XBAR 4 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR4_G6_SEL,PWM XBAR4 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR4_G7,PWM XBAR 4 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR4_G7_SEL,PWM XBAR4 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR4_G8,PWM XBAR 4 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR4_G8_SEL,PWM XBAR4 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR4_G9,PWM XBAR 4 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR4_G9_SEL,PWM XBAR4 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x240++0x27 line.long 0x0 "CONTROLSS_PWMXBAR5_G0,PWM XBAR 5 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR5_G0_SEL,PWM XBAR5 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR5_G1,PWM XBAR 5 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR5_G1_SEL,PWM XBAR5 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR5_G2,PWM XBAR 5 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR5_G2_SEL,PWM XBAR5 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR5_G3,PWM XBAR 5 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR5_G3_SEL,PWM XBAR5 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR5_G4,PWM XBAR 5 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR5_G4_SEL,PWM XBAR5 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR5_G5,PWM XBAR 5 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR5_G5_SEL,PWM XBAR5 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR5_G6,PWM XBAR 5 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR5_G6_SEL,PWM XBAR5 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR5_G7,PWM XBAR 5 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR5_G7_SEL,PWM XBAR5 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR5_G8,PWM XBAR 5 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR5_G8_SEL,PWM XBAR5 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR5_G9,PWM XBAR 5 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR5_G9_SEL,PWM XBAR5 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x280++0x27 line.long 0x0 "CONTROLSS_PWMXBAR6_G0,PWM XBAR 6 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR6_G0_SEL,PWM XBAR6 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR6_G1,PWM XBAR 6 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR6_G1_SEL,PWM XBAR6 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR6_G2,PWM XBAR 6 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR6_G2_SEL,PWM XBAR6 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR6_G3,PWM XBAR 6 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR6_G3_SEL,PWM XBAR6 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR6_G4,PWM XBAR 6 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR6_G4_SEL,PWM XBAR6 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR6_G5,PWM XBAR 6 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR6_G5_SEL,PWM XBAR6 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR6_G6,PWM XBAR 6 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR6_G6_SEL,PWM XBAR6 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR6_G7,PWM XBAR 6 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR6_G7_SEL,PWM XBAR6 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR6_G8,PWM XBAR 6 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR6_G8_SEL,PWM XBAR6 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR6_G9,PWM XBAR 6 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR6_G9_SEL,PWM XBAR6 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x2C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR7_G0,PWM XBAR 7 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR7_G0_SEL,PWM XBAR7 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR7_G1,PWM XBAR 7 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR7_G1_SEL,PWM XBAR7 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR7_G2,PWM XBAR 7 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR7_G2_SEL,PWM XBAR7 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR7_G3,PWM XBAR 7 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR7_G3_SEL,PWM XBAR7 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR7_G4,PWM XBAR 7 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR7_G4_SEL,PWM XBAR7 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR7_G5,PWM XBAR 7 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR7_G5_SEL,PWM XBAR7 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR7_G6,PWM XBAR 7 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR7_G6_SEL,PWM XBAR7 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR7_G7,PWM XBAR 7 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR7_G7_SEL,PWM XBAR7 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR7_G8,PWM XBAR 7 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR7_G8_SEL,PWM XBAR7 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR7_G9,PWM XBAR 7 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR7_G9_SEL,PWM XBAR7 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x300++0x27 line.long 0x0 "CONTROLSS_PWMXBAR8_G0,PWM XBAR 8 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR8_G0_SEL,PWM XBAR8 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR8_G1,PWM XBAR 8 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR8_G1_SEL,PWM XBAR8 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR8_G2,PWM XBAR 8 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR8_G2_SEL,PWM XBAR8 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR8_G3,PWM XBAR 8 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR8_G3_SEL,PWM XBAR8 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR8_G4,PWM XBAR 8 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR8_G4_SEL,PWM XBAR8 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR8_G5,PWM XBAR 8 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR8_G5_SEL,PWM XBAR8 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR8_G6,PWM XBAR 8 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR8_G6_SEL,PWM XBAR8 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR8_G7,PWM XBAR 8 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR8_G7_SEL,PWM XBAR8 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR8_G8,PWM XBAR 8 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR8_G8_SEL,PWM XBAR8 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR8_G9,PWM XBAR 8 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR8_G9_SEL,PWM XBAR8 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x340++0x27 line.long 0x0 "CONTROLSS_PWMXBAR9_G0,PWM XBAR 9 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR9_G0_SEL,PWM XBAR9 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR9_G1,PWM XBAR 9 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR9_G1_SEL,PWM XBAR9 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR9_G2,PWM XBAR 9 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR9_G2_SEL,PWM XBAR9 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR9_G3,PWM XBAR 9 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR9_G3_SEL,PWM XBAR9 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR9_G4,PWM XBAR 9 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR9_G4_SEL,PWM XBAR9 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR9_G5,PWM XBAR 9 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR9_G5_SEL,PWM XBAR9 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR9_G6,PWM XBAR 9 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR9_G6_SEL,PWM XBAR9 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR9_G7,PWM XBAR 9 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR9_G7_SEL,PWM XBAR9 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR9_G8,PWM XBAR 9 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR9_G8_SEL,PWM XBAR9 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR9_G9,PWM XBAR 9 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR9_G9_SEL,PWM XBAR9 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x380++0x27 line.long 0x0 "CONTROLSS_PWMXBAR10_G0,PWM XBAR 10 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR10_G0_SEL,PWM XBAR10 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR10_G1,PWM XBAR 10 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR10_G1_SEL,PWM XBAR10 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR10_G2,PWM XBAR 10 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR10_G2_SEL,PWM XBAR10 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR10_G3,PWM XBAR 10 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR10_G3_SEL,PWM XBAR10 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR10_G4,PWM XBAR 10 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR10_G4_SEL,PWM XBAR10 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR10_G5,PWM XBAR 10 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR10_G5_SEL,PWM XBAR10 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR10_G6,PWM XBAR 10 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR10_G6_SEL,PWM XBAR10 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR10_G7,PWM XBAR 10 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR10_G7_SEL,PWM XBAR10 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR10_G8,PWM XBAR 10 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR10_G8_SEL,PWM XBAR10 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR10_G9,PWM XBAR 10 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR10_G9_SEL,PWM XBAR10 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x3C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR11_G0,PWM XBAR 11 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR11_G0_SEL,PWM XBAR11 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR11_G1,PWM XBAR 11 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR11_G1_SEL,PWM XBAR11 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR11_G2,PWM XBAR 11 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR11_G2_SEL,PWM XBAR11 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR11_G3,PWM XBAR 11 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR11_G3_SEL,PWM XBAR11 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR11_G4,PWM XBAR 11 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR11_G4_SEL,PWM XBAR11 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR11_G5,PWM XBAR 11 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR11_G5_SEL,PWM XBAR11 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR11_G6,PWM XBAR 11 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR11_G6_SEL,PWM XBAR11 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR11_G7,PWM XBAR 11 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR11_G7_SEL,PWM XBAR11 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR11_G8,PWM XBAR 11 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR11_G8_SEL,PWM XBAR11 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR11_G9,PWM XBAR 11 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR11_G9_SEL,PWM XBAR11 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x400++0x27 line.long 0x0 "CONTROLSS_PWMXBAR12_G0,PWM XBAR 12 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR12_G0_SEL,PWM XBAR12 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR12_G1,PWM XBAR 12 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR12_G1_SEL,PWM XBAR12 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR12_G2,PWM XBAR 12 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR12_G2_SEL,PWM XBAR12 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR12_G3,PWM XBAR 12 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR12_G3_SEL,PWM XBAR12 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR12_G4,PWM XBAR 12 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR12_G4_SEL,PWM XBAR12 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR12_G5,PWM XBAR 12 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR12_G5_SEL,PWM XBAR12 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR12_G6,PWM XBAR 12 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR12_G6_SEL,PWM XBAR12 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR12_G7,PWM XBAR 12 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR12_G7_SEL,PWM XBAR12 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR12_G8,PWM XBAR 12 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR12_G8_SEL,PWM XBAR12 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR12_G9,PWM XBAR 12 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR12_G9_SEL,PWM XBAR12 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x440++0x27 line.long 0x0 "CONTROLSS_PWMXBAR13_G0,PWM XBAR 13 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR13_G0_SEL,PWM XBAR13 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR13_G1,PWM XBAR 13 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR13_G1_SEL,PWM XBAR13 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR13_G2,PWM XBAR 13 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR13_G2_SEL,PWM XBAR13 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR13_G3,PWM XBAR 13 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR13_G3_SEL,PWM XBAR13 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR13_G4,PWM XBAR 13 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR13_G4_SEL,PWM XBAR13 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR13_G5,PWM XBAR 13 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR13_G5_SEL,PWM XBAR13 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR13_G6,PWM XBAR 13 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR13_G6_SEL,PWM XBAR13 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR13_G7,PWM XBAR 13 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR13_G7_SEL,PWM XBAR13 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR13_G8,PWM XBAR 13 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR13_G8_SEL,PWM XBAR13 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR13_G9,PWM XBAR 13 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR13_G9_SEL,PWM XBAR13 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x480++0x27 line.long 0x0 "CONTROLSS_PWMXBAR14_G0,PWM XBAR 14 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR14_G0_SEL,PWM XBAR14 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR14_G1,PWM XBAR 14 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR14_G1_SEL,PWM XBAR14 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR14_G2,PWM XBAR 14 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR14_G2_SEL,PWM XBAR14 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR14_G3,PWM XBAR 14 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR14_G3_SEL,PWM XBAR14 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR14_G4,PWM XBAR 14 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR14_G4_SEL,PWM XBAR14 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR14_G5,PWM XBAR 14 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR14_G5_SEL,PWM XBAR14 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR14_G6,PWM XBAR 14 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR14_G6_SEL,PWM XBAR14 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR14_G7,PWM XBAR 14 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR14_G7_SEL,PWM XBAR14 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR14_G8,PWM XBAR 14 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR14_G8_SEL,PWM XBAR14 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR14_G9,PWM XBAR 14 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR14_G9_SEL,PWM XBAR14 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x4C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR15_G0,PWM XBAR 15 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR15_G0_SEL,PWM XBAR15 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR15_G1,PWM XBAR 15 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR15_G1_SEL,PWM XBAR15 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR15_G2,PWM XBAR 15 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR15_G2_SEL,PWM XBAR15 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR15_G3,PWM XBAR 15 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR15_G3_SEL,PWM XBAR15 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR15_G4,PWM XBAR 15 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR15_G4_SEL,PWM XBAR15 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR15_G5,PWM XBAR 15 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR15_G5_SEL,PWM XBAR15 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR15_G6,PWM XBAR 15 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR15_G6_SEL,PWM XBAR15 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR15_G7,PWM XBAR 15 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR15_G7_SEL,PWM XBAR15 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR15_G8,PWM XBAR 15 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR15_G8_SEL,PWM XBAR15 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR15_G9,PWM XBAR 15 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR15_G9_SEL,PWM XBAR15 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x500++0x27 line.long 0x0 "CONTROLSS_PWMXBAR16_G0,PWM XBAR 16 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR16_G0_SEL,PWM XBAR16 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR16_G1,PWM XBAR 16 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR16_G1_SEL,PWM XBAR16 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR16_G2,PWM XBAR 16 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR16_G2_SEL,PWM XBAR16 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR16_G3,PWM XBAR 16 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR16_G3_SEL,PWM XBAR16 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR16_G4,PWM XBAR 16 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR16_G4_SEL,PWM XBAR16 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR16_G5,PWM XBAR 16 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR16_G5_SEL,PWM XBAR16 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR16_G6,PWM XBAR 16 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR16_G6_SEL,PWM XBAR16 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR16_G7,PWM XBAR 16 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR16_G7_SEL,PWM XBAR16 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR16_G8,PWM XBAR 16 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR16_G8_SEL,PWM XBAR16 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR16_G9,PWM XBAR 16 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR16_G9_SEL,PWM XBAR16 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x540++0x27 line.long 0x0 "CONTROLSS_PWMXBAR17_G0,PWM XBAR 17 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR17_G0_SEL,PWM XBAR17 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR17_G1,PWM XBAR 17 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR17_G1_SEL,PWM XBAR17 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR17_G2,PWM XBAR 17 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR17_G2_SEL,PWM XBAR17 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR17_G3,PWM XBAR 17 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR17_G3_SEL,PWM XBAR17 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR17_G4,PWM XBAR 17 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR17_G4_SEL,PWM XBAR17 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR17_G5,PWM XBAR 17 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR17_G5_SEL,PWM XBAR17 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR17_G6,PWM XBAR 17 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR17_G6_SEL,PWM XBAR17 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR17_G7,PWM XBAR 17 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR17_G7_SEL,PWM XBAR17 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR17_G8,PWM XBAR 17 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR17_G8_SEL,PWM XBAR17 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR17_G9,PWM XBAR 17 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR17_G9_SEL,PWM XBAR17 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x580++0x27 line.long 0x0 "CONTROLSS_PWMXBAR18_G0,PWM XBAR 18 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR18_G0_SEL,PWM XBAR18 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR18_G1,PWM XBAR 18 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR18_G1_SEL,PWM XBAR18 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR18_G2,PWM XBAR 18 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR18_G2_SEL,PWM XBAR18 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR18_G3,PWM XBAR 18 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR18_G3_SEL,PWM XBAR18 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR18_G4,PWM XBAR 18 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR18_G4_SEL,PWM XBAR18 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR18_G5,PWM XBAR 18 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR18_G5_SEL,PWM XBAR18 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR18_G6,PWM XBAR 18 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR18_G6_SEL,PWM XBAR18 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR18_G7,PWM XBAR 18 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR18_G7_SEL,PWM XBAR18 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR18_G8,PWM XBAR 18 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR18_G8_SEL,PWM XBAR18 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR18_G9,PWM XBAR 18 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR18_G9_SEL,PWM XBAR18 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x5C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR19_G0,PWM XBAR 19 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR19_G0_SEL,PWM XBAR19 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR19_G1,PWM XBAR 19 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR19_G1_SEL,PWM XBAR19 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR19_G2,PWM XBAR 19 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR19_G2_SEL,PWM XBAR19 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR19_G3,PWM XBAR 19 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR19_G3_SEL,PWM XBAR19 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR19_G4,PWM XBAR 19 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR19_G4_SEL,PWM XBAR19 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR19_G5,PWM XBAR 19 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR19_G5_SEL,PWM XBAR19 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR19_G6,PWM XBAR 19 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR19_G6_SEL,PWM XBAR19 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR19_G7,PWM XBAR 19 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR19_G7_SEL,PWM XBAR19 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR19_G8,PWM XBAR 19 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR19_G8_SEL,PWM XBAR19 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR19_G9,PWM XBAR 19 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR19_G9_SEL,PWM XBAR19 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x600++0x27 line.long 0x0 "CONTROLSS_PWMXBAR20_G0,PWM XBAR 20 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR20_G0_SEL,PWM XBAR20 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR20_G1,PWM XBAR 20 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR20_G1_SEL,PWM XBAR20 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR20_G2,PWM XBAR 20 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR20_G2_SEL,PWM XBAR20 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR20_G3,PWM XBAR 20 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR20_G3_SEL,PWM XBAR20 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR20_G4,PWM XBAR 20 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR20_G4_SEL,PWM XBAR20 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR20_G5,PWM XBAR 20 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR20_G5_SEL,PWM XBAR20 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR20_G6,PWM XBAR 20 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR20_G6_SEL,PWM XBAR20 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR20_G7,PWM XBAR 20 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR20_G7_SEL,PWM XBAR20 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR20_G8,PWM XBAR 20 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR20_G8_SEL,PWM XBAR20 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR20_G9,PWM XBAR 20 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR20_G9_SEL,PWM XBAR20 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x640++0x27 line.long 0x0 "CONTROLSS_PWMXBAR21_G0,PWM XBAR 21 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR21_G0_SEL,PWM XBAR21 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR21_G1,PWM XBAR 21 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR21_G1_SEL,PWM XBAR21 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR21_G2,PWM XBAR 21 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR21_G2_SEL,PWM XBAR21 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR21_G3,PWM XBAR 21 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR21_G3_SEL,PWM XBAR21 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR21_G4,PWM XBAR 21 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR21_G4_SEL,PWM XBAR21 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR21_G5,PWM XBAR 21 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR21_G5_SEL,PWM XBAR21 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR21_G6,PWM XBAR 21 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR21_G6_SEL,PWM XBAR21 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR21_G7,PWM XBAR 21 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR21_G7_SEL,PWM XBAR21 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR21_G8,PWM XBAR 21 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR21_G8_SEL,PWM XBAR21 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR21_G9,PWM XBAR 21 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR21_G9_SEL,PWM XBAR21 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x680++0x27 line.long 0x0 "CONTROLSS_PWMXBAR22_G0,PWM XBAR 22 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR22_G0_SEL,PWM XBAR22 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR22_G1,PWM XBAR 22 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR22_G1_SEL,PWM XBAR22 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR22_G2,PWM XBAR 22 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR22_G2_SEL,PWM XBAR22 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR22_G3,PWM XBAR 22 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR22_G3_SEL,PWM XBAR22 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR22_G4,PWM XBAR 22 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR22_G4_SEL,PWM XBAR22 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR22_G5,PWM XBAR 22 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR22_G5_SEL,PWM XBAR22 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR22_G6,PWM XBAR 22 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR22_G6_SEL,PWM XBAR22 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR22_G7,PWM XBAR 22 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR22_G7_SEL,PWM XBAR22 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR22_G8,PWM XBAR 22 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR22_G8_SEL,PWM XBAR22 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR22_G9,PWM XBAR 22 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR22_G9_SEL,PWM XBAR22 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x6C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR23_G0,PWM XBAR 23 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR23_G0_SEL,PWM XBAR23 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR23_G1,PWM XBAR 23 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR23_G1_SEL,PWM XBAR23 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR23_G2,PWM XBAR 23 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR23_G2_SEL,PWM XBAR23 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR23_G3,PWM XBAR 23 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR23_G3_SEL,PWM XBAR23 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR23_G4,PWM XBAR 23 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR23_G4_SEL,PWM XBAR23 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR23_G5,PWM XBAR 23 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR23_G5_SEL,PWM XBAR23 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR23_G6,PWM XBAR 23 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR23_G6_SEL,PWM XBAR23 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR23_G7,PWM XBAR 23 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR23_G7_SEL,PWM XBAR23 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR23_G8,PWM XBAR 23 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR23_G8_SEL,PWM XBAR23 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR23_G9,PWM XBAR 23 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR23_G9_SEL,PWM XBAR23 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x700++0x27 line.long 0x0 "CONTROLSS_PWMXBAR24_G0,PWM XBAR 24 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR24_G0_SEL,PWM XBAR24 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR24_G1,PWM XBAR 24 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR24_G1_SEL,PWM XBAR24 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR24_G2,PWM XBAR 24 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR24_G2_SEL,PWM XBAR24 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR24_G3,PWM XBAR 24 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR24_G3_SEL,PWM XBAR24 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR24_G4,PWM XBAR 24 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR24_G4_SEL,PWM XBAR24 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR24_G5,PWM XBAR 24 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR24_G5_SEL,PWM XBAR24 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR24_G6,PWM XBAR 24 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR24_G6_SEL,PWM XBAR24 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR24_G7,PWM XBAR 24 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR24_G7_SEL,PWM XBAR24 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR24_G8,PWM XBAR 24 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR24_G8_SEL,PWM XBAR24 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR24_G9,PWM XBAR 24 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR24_G9_SEL,PWM XBAR24 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x740++0x27 line.long 0x0 "CONTROLSS_PWMXBAR25_G0,PWM XBAR 25 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR25_G0_SEL,PWM XBAR25 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR25_G1,PWM XBAR 25 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR25_G1_SEL,PWM XBAR25 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR25_G2,PWM XBAR 25 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR25_G2_SEL,PWM XBAR25 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR25_G3,PWM XBAR 25 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR25_G3_SEL,PWM XBAR25 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR25_G4,PWM XBAR 25 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR25_G4_SEL,PWM XBAR25 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR25_G5,PWM XBAR 25 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR25_G5_SEL,PWM XBAR25 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR25_G6,PWM XBAR 25 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR25_G6_SEL,PWM XBAR25 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR25_G7,PWM XBAR 25 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR25_G7_SEL,PWM XBAR25 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR25_G8,PWM XBAR 25 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR25_G8_SEL,PWM XBAR25 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR25_G9,PWM XBAR 25 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR25_G9_SEL,PWM XBAR25 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x780++0x27 line.long 0x0 "CONTROLSS_PWMXBAR26_G0,PWM XBAR 26 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR26_G0_SEL,PWM XBAR26 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR26_G1,PWM XBAR 26 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR26_G1_SEL,PWM XBAR26 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR26_G2,PWM XBAR 26 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR26_G2_SEL,PWM XBAR26 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR26_G3,PWM XBAR 26 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR26_G3_SEL,PWM XBAR26 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR26_G4,PWM XBAR 26 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR26_G4_SEL,PWM XBAR26 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR26_G5,PWM XBAR 26 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR26_G5_SEL,PWM XBAR26 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR26_G6,PWM XBAR 26 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR26_G6_SEL,PWM XBAR26 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR26_G7,PWM XBAR 26 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR26_G7_SEL,PWM XBAR26 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR26_G8,PWM XBAR 26 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR26_G8_SEL,PWM XBAR26 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR26_G9,PWM XBAR 26 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR26_G9_SEL,PWM XBAR26 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x7C0++0x27 line.long 0x0 "CONTROLSS_PWMXBAR27_G0,PWM XBAR 27 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR27_G0_SEL,PWM XBAR27 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR27_G1,PWM XBAR 27 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR27_G1_SEL,PWM XBAR27 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR27_G2,PWM XBAR 27 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR27_G2_SEL,PWM XBAR27 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR27_G3,PWM XBAR 27 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR27_G3_SEL,PWM XBAR27 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR27_G4,PWM XBAR 27 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR27_G4_SEL,PWM XBAR27 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR27_G5,PWM XBAR 27 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR27_G5_SEL,PWM XBAR27 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR27_G6,PWM XBAR 27 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR27_G6_SEL,PWM XBAR27 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR27_G7,PWM XBAR 27 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR27_G7_SEL,PWM XBAR27 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR27_G8,PWM XBAR 27 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR27_G8_SEL,PWM XBAR27 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR27_G9,PWM XBAR 27 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR27_G9_SEL,PWM XBAR27 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x800++0x27 line.long 0x0 "CONTROLSS_PWMXBAR28_G0,PWM XBAR 28 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR28_G0_SEL,PWM XBAR28 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR28_G1,PWM XBAR 28 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR28_G1_SEL,PWM XBAR28 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR28_G2,PWM XBAR 28 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR28_G2_SEL,PWM XBAR28 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR28_G3,PWM XBAR 28 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR28_G3_SEL,PWM XBAR28 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR28_G4,PWM XBAR 28 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR28_G4_SEL,PWM XBAR28 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR28_G5,PWM XBAR 28 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR28_G5_SEL,PWM XBAR28 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR28_G6,PWM XBAR 28 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR28_G6_SEL,PWM XBAR28 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR28_G7,PWM XBAR 28 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR28_G7_SEL,PWM XBAR28 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR28_G8,PWM XBAR 28 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR28_G8_SEL,PWM XBAR28 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR28_G9,PWM XBAR 28 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR28_G9_SEL,PWM XBAR28 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" group.long 0x840++0x27 line.long 0x0 "CONTROLSS_PWMXBAR29_G0,PWM XBAR 29 Input Select." hexmask.long.tbyte 0x0 0.--19. 1. "PWMXBAR29_G0_SEL,PWM XBAR29 G0 Input.." line.long 0x4 "CONTROLSS_PWMXBAR29_G1,PWM XBAR 29 Input Select." hexmask.long.tbyte 0x4 0.--19. 1. "PWMXBAR29_G1_SEL,PWM XBAR29 G1 Input.." line.long 0x8 "CONTROLSS_PWMXBAR29_G2,PWM XBAR 29 Input Select." hexmask.long.tbyte 0x8 0.--23. 1. "PWMXBAR29_G2_SEL,PWM XBAR29 G2 Input.." line.long 0xC "CONTROLSS_PWMXBAR29_G3,PWM XBAR 29 Input Select." hexmask.long 0xC 0.--31. 1. "PWMXBAR29_G3_SEL,PWM XBAR29 G3 Input.." line.long 0x10 "CONTROLSS_PWMXBAR29_G4,PWM XBAR 29 Input Select." hexmask.long 0x10 0.--31. 1. "PWMXBAR29_G4_SEL,PWM XBAR29 G4 input bit select. Input source is INPUT XBAR.1:INPUT XBAR output bit[x] selected0:INPUT XBAR output bit[x] is de-selected" line.long 0x14 "CONTROLSS_PWMXBAR29_G5,PWM XBAR 29 Input Select." hexmask.long 0x14 0.--31. 1. "PWMXBAR29_G5_SEL,PWM XBAR29 G5 input bit select. Input source is PWM TRIPOUT.1:PWM TRIPOUT bit[x] selected0:PWM TRIPOUT bit[x] is de-selected" line.long 0x18 "CONTROLSS_PWMXBAR29_G6,PWM XBAR 29 Input Select." hexmask.long 0x18 0.--31. 1. "PWMXBAR29_G6_SEL,PWM XBAR29 G6 input bit select. Input source is PWM DEL TRIP1:PWM DEL TRIP bit[x] selected0:PWM DEL TRIP bit[x] is de-selected" line.long 0x1C "CONTROLSS_PWMXBAR29_G7,PWM XBAR 29 Input Select." hexmask.long 0x1C 0.--31. 1. "PWMXBAR29_G7_SEL,PWM XBAR29 G7 input bit select. Input source is PWM DEL ACTIVE1:PWM DEL ACTIVE bit[x] selected0:PWM DEL ACTIVE bit[x] is de-selected" line.long 0x20 "CONTROLSS_PWMXBAR29_G8,PWM XBAR 29 Input Select." hexmask.long 0x20 0.--31. 1. "PWMXBAR29_G8_SEL,PWM XBAR29 G8 Input SelectBit0:EQEP0.ERRBit1:EQEP1.ERRBit2:EQEP2.ERRBit [6:3]: FSIRX0.RX_TRIG4Bit [10:7]: FSIRX1.RX_TRIG4Bit [14:11]: FSIRX2.RX_TRIG4Bit [18:15]: FSIRX3.RX_TRIG4 Bit [31:19]: ECAP[12:0].TRIPOUT" line.long 0x24 "CONTROLSS_PWMXBAR29_G9,PWM XBAR 29 Input Select." hexmask.long.byte 0x24 0.--6. 1. "PWMXBAR29_G9_SEL,PWM XBAR29 G9 Input Select20:ECAP[15:13].TRIPOUT3:SYNCOUTXBAR04:SYNCOUTXBAR15:SOC_A_SEL6:SOC_B_SEL" tree.end tree.end tree "CPSW0" base ad:0x52800000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_IDVER_REG,ID Version Register." hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x4++0xB line.long 0x0 "CPSW_SS_SYNCE_COUNT_REG,SS SYNCE Count Register." hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,SyncE Count Value - This value determines the toggle rate of the TS_SYNCE output. When this value is zero the TS_SYNCE output is disabled (low). When this value is non-zero the TS_SYNCE output toggles each time the synce count value is.." line.long 0x4 "CPSW_SS_SYNCE_MUX_REG,SS Synce Mux Register." bitfld.long 0x4 4.--5. "SYNCE_SEL,Sync E Interface Select. 00 - GMIIn_MRCLK_I input clock from selected GMII port 01 - RMII_MHZ_50_CLK (same for all ports if RMII included) 10 - RGMIIn_RXC_I input clock from selected port (If RGMII included) 11 - SERDESn_RXCLK from.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "SYNCE_PORT_SEL,Sync E Port Select - This field selects the port that will be used for the synchronous Ethernet receive clock. The port interface is selected with synce_sel. 0 - Port 1 1 - Port 2 ... 7 - Port 8 8-15 - Reserved" line.long 0x8 "CPSW_SS_CONTROL_REG,SS Control Register." bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode. 0 - The low power indicate state (LPI) includes gating off the CPPI_GCLK to the CPSW. 1 - The low power indicate state (LPI) does not gate the clock to the CPSW" "0,1" bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable. 0 - EEE is disabled 1 - EEE is enabled" "0,1" group.long 0x18++0x3 line.long 0x0 "CPSW_SS_INT_CONTROL_REG,SS Interrupt Control Register." bitfld.long 0x0 31. "INT_TEST,Interrupt Test - Test bit to the interrupt pacing blocks" "0,1" bitfld.long 0x0 30. "INT_SEL_VEC_EN,Interrupt Select Vector Enable. 0 - in_vector is an 8-bit mask for tx_pend rx_pend and rx_thresh_pend. 1 - in_vector is the 3-bit encoded value of the highest interrupt channel set for tx_pend rx_pend and rx_thresh_pend." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "INT_PACE_EN,Interrupt Pacing Enable Bus. int_pace_en[0] - Enables C0_Rx_Pulse Pacing (0 is pacing bypass) int_pace_en[1] - Enables C0_Tx_Pulse Pacing (0 is pacing bypass) int_pace_en[2] - Enables C1_Rx_Pulse Pacing (0 is pacing bypass).." hexmask.long.word 0x0 0.--11. 1. "INT_PRESCALE,Interrupt Counter Prescaler - The number of VBUSP_CLK periods in 4us." rgroup.long 0x1C++0x7 line.long 0x0 "CPSW_SS_STATUS_REG,SS Status Register." bitfld.long 0x0 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1" line.long 0x4 "CPSW_SUBSYSTEM_CONFIG_REG,Subsystem Configuration Register." hexmask.long.byte 0x4 20.--27. 1. "XGMII,The Number of XGMII Ports included in the CPSW" bitfld.long 0x4 19. "QSGMII,QSGMII is included in the CPSW" "0,1" newline bitfld.long 0x4 18. "SGMII,SGMII is included in the CPSW" "0,1" bitfld.long 0x4 17. "RGMII,RGMII is included in the CPSW" "0,1" newline bitfld.long 0x4 16. "RMII,RMII is included in the CPSW" "0,1" hexmask.long.byte 0x4 8.--12. 1. "NUM_GENF,The number of CPTS GENF outputs" newline hexmask.long.byte 0x4 0.--7. 1. "NUM_PORTS,The total number of ports including the host port 0" rgroup.long 0x30++0x7 line.long 0x0 "CPSW_RGMII1_STATUS_REG,RGMII1 Status Register." bitfld.long 0x0 3. "FULLDUPLEX,Rgmii1 Full-duplex 0 - Half-duplex 1 - Full-duplex" "0,1" bitfld.long 0x0 1.--2. "SPEED,Rgmii1 Speed 00 - 10Mbps 01 - 100Mbps 10 - 1000Mbps 11 - reserved" "0,1,2,3" newline bitfld.long 0x0 0. "LINK,Rgmii1 Link Indicator 0 - Link is down 1 - Link is up" "0,1" line.long 0x4 "CPSW_RGMII2_STATUS_REG,RGMII2 Status Register." bitfld.long 0x4 3. "FULLDUPLEX,Rgmii2 Full-duplex 0 - Half-duplex 1 - Full-duplex" "0,1" bitfld.long 0x4 1.--2. "SPEED,Rgmii2 Speed 00 - 10Mbps 01 - 100Mbps 10 - 1000Mbps 11 - reserved" "0,1,2,3" newline bitfld.long 0x4 0. "LINK,Rgmii2 Link Indicator 0 - Link is down 1 - Link is up" "0,1" rgroup.long 0xF00++0x3 line.long 0x0 "CPSW_MDIO_VERSION_REG,MDIO Version Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0xF04++0x7 line.long 0x0 "CPSW_MDIO_CONTROL_REG,MDIO Control Register" rbitfld.long 0x0 31. "IDLE,MDIO state machine IDLE. Set to 1 by the hardware when the state machine is in the idle state." "0,1" bitfld.long 0x0 30. "ENABLE,Enable control. Writing a 1 to this bit enables the MDIO state machine writing a 0 disables it. If the MDIO state machine is active at the time it is disabled it will complete the current operation before halting and setting the idle bit. If.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1. This implies that MDIOUserAccess1 is the highest available user access channel." bitfld.long 0x0 20. "PREAMBLE,Preamble disable. Writing a 1 to this bit disables this device from sending MDIO frame preambles in clause 22 mode of operation. This bit has no effect in clause 45 mode of operation." "0,1" newline bitfld.long 0x0 19. "FAULT,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection." "0,1" newline bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable. This bit can be set to 1 to enable the host to set the userint and linkint bits for test purposes." "0,1" hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0. MDCLK frequency = clk frequency/(clkdiv+1)." line.long 0x4 "CPSW_MDIO_ALIVE_REG,MDIO Alive Register" hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO Alive. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY the bit is reset if the PHY fails to acknowledge the access. Both the.." rgroup.long 0xF0C++0x3 line.long 0x0 "CPSW_MDIO_LINK_REG,MDIO Link Register" hexmask.long 0x0 0.--31. 1. "LINK,MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The corresponding bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is cleared to.." group.long 0xF10++0x37 line.long 0x0 "CPSW_MDIO_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register" bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value. Normal mode operation: When asserted a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register." "0,1,2,3" line.long 0x4 "CPSW_MDIO_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register" bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value. Normal mode operation: When asserted a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register.." "0,1,2,3" line.long 0x8 "CPSW_MDIO_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register" bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set. Normal Mode Operation: This register is not used in normal mode. In normal mode the MDIO_LINKINT[1:0] interrupts are enabled with the linkint_enable bit in the associated MDIOUserPhySel0/1 register. MDIO.." "0,1" line.long 0xC "CPSW_MDIO_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register" bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear. Normal Mode Operation: This register is not used in normal mode. In normal mode the MDIO_LINKINT[1:0] interrupts are enabled with the linkint_enable bit in the associated MDIOUserPhySel0/1 register. MDIO.." "0,1" line.long 0x10 "CPSW_MDIO_USER_INT_RAW_REG,MDIO User Interrupt Raw Register" bitfld.long 0x10 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively. When asserted a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has.." "0,1,2,3" line.long 0x14 "CPSW_MDIO_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register" bitfld.long 0x14 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively. When asserted a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess.." "0,1,2,3" line.long 0x18 "CPSW_MDIO_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register" bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for userintmasked[1:0] respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess.." "0,1,2,3" line.long 0x1C "CPSW_MDIO_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register" bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for userintmasked[1:0] respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0 to this register has no.." "0,1,2,3" line.long 0x20 "CPSW_MDIO_MANUAL_IF_REG,MDIO Manual Interface Register" bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output - This value is the MDCLK_O output value when the manualmode bit is set in the MDIO_POLL_IPG register." "0,1" bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable - This value is inverted and output on the MDIO_OE_N output when the manualmode bit is set in the MDIO_POLL_IPG register." "0,1" newline bitfld.long 0x20 0. "MDIO_PIN,MDIO_Pin Value - This is the external MDIO data pin value when the manualmode bit is set in the MDIO_POLL_IPG register. That is this value is driven on the MDIO_O (the MDIO serial data output) when MDIO_OE is asserted. The read value for this.." "0,1" line.long 0x24 "CPSW_MDIO_POLL_REG,MDIO Poll Register" bitfld.long 0x24 31. "MANUALMODE,Polling Inter Packet Gap Value - This value is the number of MDCLK_O clocks between each poll when polling is enabled." "0,1" bitfld.long 0x24 30. "STATECHANGEMODE,State Change Mode - When set the MDIO is operating in State Change Mode. When clear the MDIO is operating in normal mode. State change mode effects interrupt operations." "0,1" newline hexmask.long.byte 0x24 0.--7. 1. "IPG,Manual Mode - When set the MDIO pins are directly controlled by software through the bits in the MDIOManual_IF register" line.long 0x28 "CPSW_MDIO_POLL_EN_REG,MDIO Poll Enable Register" hexmask.long 0x28 0.--31. 1. "POLL_EN,Poll Enable - When set the bit indicates that the associated PHY will be included in polling operations. When clear the associated PHY will not be polled. Each bit in this field is associated with a PHY. Bit zero is associated with PHY 0 and.." line.long 0x2C "CPSW_MDIO_CLAUS45_REG,MDIO Clause45 Register" hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO clause 45 mode. When a clause45 bit is cleared the PHY associated with the clause45 bit is operating in the clause 22 mode. When set the PHY associated with the clause45 bit is operating in the clause 45 mode. Bit 0 is associated with.." line.long 0x30 "CPSW_MDIO_USER_ADDR0_REG,MDIO Address 0 Register" hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,User Address 0 - In clause 45 mode this field value is the address transferred in the address transfer inititated before each MDIOUserAccess0 access. This is not used for PHYs operating in clause22 mode as there is no address transfer.." line.long 0x34 "CPSW_MDIO_USER_ADDR1_REG,MDIO Address 1 Register" hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,User Address 1 - In clause 45 mode this field value is the address transferred in the address transfer inititated before each MDIOUserAccess1 access. This is not used for PHYs operating in clause22 mode as there is no address transfer.." group.long 0x1800++0xF line.long 0x0 "CPSW_REGS_INT_SS_C0_TH_THRESH_PULSE_EN_REG,Core 0 THost Threshold Pulse Interrupt Enable Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_EN,Core 0 THost Threshold Enable - Each bit in this register corresponds to the bit in the THost threshold interrupt that is enabled to generate an interrupt on C0_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C0_TH_PULSE_EN_REG,Core 0 THost Pulse Interrupt Enable Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_EN,Core 0 THost Enable - Each bit in this register corresponds to the bit in the THost interrupt that is enabled to generate an interrupt on C0_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C0_FH_PULSE_EN_REG,Core 0 FHost Pulse Interrupt Enable Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_EN,Core 0 FHost Interrupt Enable - Each bit in this register corresponds to the bit in the FHost interrupt that is enabled to generate an interrupt on C0_FH_PULSE." line.long 0xC "CPSW_REGS_INT_SS_C0_MISC_EN_REG,Core 0 Misc Interrupt Enable Register" bitfld.long 0xC 6. "DED_PEND_EN,Core 0 MISC DED Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" bitfld.long 0xC 5. "SEC_PEND_EN,Core 0 MISC SEC Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" newline bitfld.long 0xC 4. "EVNT_PEND_EN,Core 0 MISC CPTS Event Interrupt Enable - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" bitfld.long 0xC 3. "STAT_PEND_EN,Core 0 MISC Statistics Interrupt Enable - Logical OR of all port statistics bits (bits n downto 0) - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" newline bitfld.long 0xC 2. "HOST_PEND_EN,Core 0 MISC Host Interrupt Enable - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" bitfld.long 0xC 1. "MDIO_LINKINT_EN,Core 0 MISC MDIO linkint - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" newline bitfld.long 0xC 0. "MDIO_USERINT_EN,Core 0 MISC_MDIO userint interrupt enable - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C0_Misc_PULSE" "0,1" rgroup.long 0x1810++0xB line.long 0x0 "CPSW_REGS_INT_SS_C0_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_STATUS,Core 0 THost Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the THost threshold interrupt that is enabled and generating an interrupt on C0_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C0_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_STATUS,Core 0 THost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on C0_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C0_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_STATUS,Core 0 FHost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on C0_FH_PULSE ." group.long 0x181C++0xB line.long 0x0 "CPSW_REGS_INT_SS_C0_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted" bitfld.long 0x0 6. "DED_PEND,Core 0 MISC DED Memory Protect Error Interrupt" "0,1" bitfld.long 0x0 5. "SEC_PEND,Core 0 MISC SEC Memory Protect Error Interrupt" "0,1" newline bitfld.long 0x0 4. "EVNT_PEND,Core 0 MISC CPTS Event Interrupt" "0,1" bitfld.long 0x0 3. "STAT_PEND,Core 0 MISC Statistics Interrupt - Logical OR of bits n downto 0" "0,1" newline bitfld.long 0x0 2. "HOST_PEND,Core 0 MISC Host Interrupt Enable" "0,1" bitfld.long 0x0 1. "MDIO_LINKINT,Core 0 MISC MDIO linkint - Logical OR of bits 1 and 0" "0,1" newline bitfld.long 0x0 0. "MDIO_USERINT,Core 0 MISC_MDIO userint interrupt - Logical OR of bits 1 and 0" "0,1" line.long 0x4 "CPSW_REGS_INT_SS_C0_TH_IMAX_REG,Core 0 THost Interrupt Max Register Register" hexmask.long.byte 0x4 0.--5. 1. "TH_IMAX,Core 0 THost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C0_TH_PULSE if pacing is enabled for this interrupt." line.long 0x8 "CPSW_REGS_INT_SS_C0_FH_IMAX_REG,Core 0 FHost Interrupt Max Register Register" hexmask.long.byte 0x8 0.--5. 1. "FH_IMAX,Core 0 FHost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C0_FH_PULSE if pacing is enabled for this interrupt." group.long 0x1840++0xF line.long 0x0 "CPSW_REGS_INT_SS_C1_TH_THRESH_PULSE_EN_REG,Core 1 THost Threshold Pulse Interrupt Enable Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_EN,Core 1 THost Threshold Enable - Each bit in this register corresponds to the bit in the THost threshold interrupt that is enabled to generate an interrupt on C1_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C1_TH_PULSE_EN_REG,Core 1 THost Pulse Interrupt Enable Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_EN,Core 1 THost Enable - Each bit in this register corresponds to the bit in the THost interrupt that is enabled to generate an interrupt on C1_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C1_FH_PULSE_EN_REG,Core 1 FHost Pulse Interrupt Enable Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_EN,Core 1 FHost Interrupt Enable - Each bit in this register corresponds to the bit in the FHost interrupt that is enabled to generate an interrupt on C1_FH_PULSE." line.long 0xC "CPSW_REGS_INT_SS_C1_MISC_EN_REG,Core 1 Misc Interrupt Enable Register" bitfld.long 0xC 6. "DED_PEND_EN,Core 1 MISC DED Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" bitfld.long 0xC 5. "SEC_PEND_EN,Core 1 MISC SEC Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" newline bitfld.long 0xC 4. "EVNT_PEND_EN,Core 1 MISC CPTS Event Interrupt Enable - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" bitfld.long 0xC 3. "STAT_PEND_EN,Core 1 MISC Statistics Interrupt Enable - Logical OR of all port statistics bits (bits n downto 0) - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" newline bitfld.long 0xC 2. "HOST_PEND_EN,Core 1 MISC Host Interrupt Enable - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" bitfld.long 0xC 1. "MDIO_LINKINT_EN,Core 1 MISC MDIO linkint - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" newline bitfld.long 0xC 0. "MDIO_USERINT_EN,Core 1 MISC_MDIO userint interrupt enable - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C1_Misc_PULSE" "0,1" rgroup.long 0x1850++0xB line.long 0x0 "CPSW_REGS_INT_SS_C1_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_STATUS,Core 1 THost Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the THost threshold interrupt that is enabled and generating an interrupt on C1_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C1_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_STATUS,Core 1 THost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on C1_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C1_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_STATUS,Core 1 FHost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on C1_FH_PULSE ." group.long 0x185C++0xB line.long 0x0 "CPSW_REGS_INT_SS_C1_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted" bitfld.long 0x0 6. "DED_PEND,Core 1 MISC DED Memory Protect Error Interrupt" "0,1" bitfld.long 0x0 5. "SEC_PEND,Core 1 MISC SEC Memory Protect Error Interrupt" "0,1" newline bitfld.long 0x0 4. "EVNT_PEND,Core 1 MISC CPTS Event Interrupt" "0,1" bitfld.long 0x0 3. "STAT_PEND,Core 1 MISC Statistics Interrupt - Logical OR of bits n downto 0" "0,1" newline bitfld.long 0x0 2. "HOST_PEND,Core 1 MISC Host Interrupt Enable" "0,1" bitfld.long 0x0 1. "MDIO_LINKINT,Core 1 MISC MDIO linkint - Logical OR of bits 1 and 0" "0,1" newline bitfld.long 0x0 0. "MDIO_USERINT,Core 1 MISC_MDIO userint interrupt - Logical OR of bits 1 and 0" "0,1" line.long 0x4 "CPSW_REGS_INT_SS_C1_TH_IMAX_REG,Core 1 THost Interrupt Max Register Register" hexmask.long.byte 0x4 0.--5. 1. "TH_IMAX,Core 1 THost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C1_TH_PULSE if pacing is enabled for this interrupt." line.long 0x8 "CPSW_REGS_INT_SS_C1_FH_IMAX_REG,Core 1 FHost Interrupt Max Register Register" hexmask.long.byte 0x8 0.--5. 1. "FH_IMAX,Core 1 FHost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C1_FH_PULSE if pacing is enabled for this interrupt." group.long 0x1880++0xF line.long 0x0 "CPSW_REGS_INT_SS_C2_TH_THRESH_PULSE_EN_REG,Core 2 THost Threshold Pulse Interrupt Enable Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_EN,Core 2 THost Threshold Enable - Each bit in this register corresponds to the bit in the THost threshold interrupt that is enabled to generate an interrupt on C2_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C2_TH_PULSE_EN_REG,Core 2 THost Pulse Interrupt Enable Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_EN,Core 2 THost Enable - Each bit in this register corresponds to the bit in the THost interrupt that is enabled to generate an interrupt on C2_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C2_FH_PULSE_EN_REG,Core 2 FHost Pulse Interrupt Enable Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_EN,Core 2 FHost Interrupt Enable - Each bit in this register corresponds to the bit in the FHost interrupt that is enabled to generate an interrupt on C2_FH_PULSE." line.long 0xC "CPSW_REGS_INT_SS_C2_MISC_EN_REG,Core 2 Misc Interrupt Enable Register" bitfld.long 0xC 6. "DED_PEND_EN,Core 2 MISC DED Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" bitfld.long 0xC 5. "SEC_PEND_EN,Core 2 MISC SEC Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" newline bitfld.long 0xC 4. "EVNT_PEND_EN,Core 2 MISC CPTS Event Interrupt Enable - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" bitfld.long 0xC 3. "STAT_PEND_EN,Core 2 MISC Statistics Interrupt Enable - Logical OR of all port statistics bits (bits n downto 0) - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" newline bitfld.long 0xC 2. "HOST_PEND_EN,Core 2 MISC Host Interrupt Enable - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" bitfld.long 0xC 1. "MDIO_LINKINT_EN,Core 2 MISC MDIO linkint - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" newline bitfld.long 0xC 0. "MDIO_USERINT_EN,Core 2 MISC_MDIO userint interrupt enable - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C2_Misc_PULSE" "0,1" rgroup.long 0x1890++0xB line.long 0x0 "CPSW_REGS_INT_SS_C2_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_STATUS,Core 2 THost Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the THost threshold interrupt that is enabled and generating an interrupt on C2_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C2_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_STATUS,Core 2 THost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on C2_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C2_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_STATUS,Core 2 FHost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on C2_FH_PULSE ." group.long 0x189C++0xB line.long 0x0 "CPSW_REGS_INT_SS_C2_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted" bitfld.long 0x0 6. "DED_PEND,Core 2 MISC DED Memory Protect Error Interrupt" "0,1" bitfld.long 0x0 5. "SEC_PEND,Core 2 MISC SEC Memory Protect Error Interrupt" "0,1" newline bitfld.long 0x0 4. "EVNT_PEND,Core 2 MISC CPTS Event Interrupt" "0,1" bitfld.long 0x0 3. "STAT_PEND,Core 2 MISC Statistics Interrupt - Logical OR of bits n downto 0" "0,1" newline bitfld.long 0x0 2. "HOST_PEND,Core 2 MISC Host Interrupt Enable" "0,1" bitfld.long 0x0 1. "MDIO_LINKINT,Core 2 MISC MDIO linkint - Logical OR of bits 1 and 0" "0,1" newline bitfld.long 0x0 0. "MDIO_USERINT,Core 2 MISC_MDIO userint interrupt - Logical OR of bits 1 and 0" "0,1" line.long 0x4 "CPSW_REGS_INT_SS_C2_TH_IMAX_REG,Core 2 THost Interrupt Max Register Register" hexmask.long.byte 0x4 0.--5. 1. "TH_IMAX,Core 2 THost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C2_TH_PULSE if pacing is enabled for this interrupt." line.long 0x8 "CPSW_REGS_INT_SS_C2_FH_IMAX_REG,Core 2 FHost Interrupt Max Register Register" hexmask.long.byte 0x8 0.--5. 1. "FH_IMAX,Core 2 FHost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C2_FH_PULSE if pacing is enabled for this interrupt." group.long 0x18C0++0xF line.long 0x0 "CPSW_REGS_INT_SS_C3_TH_THRESH_PULSE_EN_REG,Core 3 THost Threshold Pulse Interrupt Enable Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_EN,Core 3 THost Threshold Enable - Each bit in this register corresponds to the bit in the THost threshold interrupt that is enabled to generate an interrupt on C3_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C3_TH_PULSE_EN_REG,Core 3 THost Pulse Interrupt Enable Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_EN,Core 3 THost Enable - Each bit in this register corresponds to the bit in the THost interrupt that is enabled to generate an interrupt on C3_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C3_FH_PULSE_EN_REG,Core 3 FHost Pulse Interrupt Enable Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_EN,Core 3 FHost Interrupt Enable - Each bit in this register corresponds to the bit in the FHost interrupt that is enabled to generate an interrupt on C3_FH_PULSE." line.long 0xC "CPSW_REGS_INT_SS_C3_MISC_EN_REG,Core 3 Misc Interrupt Enable Register" bitfld.long 0xC 6. "DED_PEND_EN,Core 3 MISC DED Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" bitfld.long 0xC 5. "SEC_PEND_EN,Core 3 MISC SEC Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" newline bitfld.long 0xC 4. "EVNT_PEND_EN,Core 3 MISC CPTS Event Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" bitfld.long 0xC 3. "STAT_PEND_EN,Core 3 MISC Statistics Interrupt Enable - Logical OR of all port statistics bits (bits n downto 0) - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" newline bitfld.long 0xC 2. "HOST_PEND_EN,Core 3 MISC Host Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" bitfld.long 0xC 1. "MDIO_LINKINT_EN,Core 3 MISC MDIO linkint - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" newline bitfld.long 0xC 0. "MDIO_USERINT_EN,Core 3 MISC_MDIO userint interrupt enable - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C3_Misc_PULSE" "0,1" rgroup.long 0x18D0++0xB line.long 0x0 "CPSW_REGS_INT_SS_C3_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register" hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_STATUS,Core 3 THost Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the THost threshold interrupt that is enabled and generating an interrupt on C3_TH_THRESH_PULSE." line.long 0x4 "CPSW_REGS_INT_SS_C3_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register" hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_STATUS,Core 3 THost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on C3_TH_PULSE." line.long 0x8 "CPSW_REGS_INT_SS_C3_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register" hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_STATUS,Core 3 FHost Pulse Interrupt Status Register - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on C3_FH_PULSE ." group.long 0x18DC++0xB line.long 0x0 "CPSW_REGS_INT_SS_C3_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted" bitfld.long 0x0 6. "DED_PEND,Core 3 MISC DED Memory Protect Error Interrupt" "0,1" bitfld.long 0x0 5. "SEC_PEND,Core 3 MISC SEC Memory Protect Error Interrupt" "0,1" newline bitfld.long 0x0 4. "EVNT_PEND,Core 3 MISC CPTS Event Interrupt" "0,1" bitfld.long 0x0 3. "STAT_PEND,Core 3 MISC Statistics Interrupt - Logical OR of bits n downto 0" "0,1" newline bitfld.long 0x0 2. "HOST_PEND,Core 3 MISC Host Interrupt Enable" "0,1" bitfld.long 0x0 1. "MDIO_LINKINT,Core 3 MISC MDIO linkint - Logical OR of bits 1 and 0" "0,1" newline bitfld.long 0x0 0. "MDIO_USERINT,Core 3 MISC_MDIO userint interrupt - Logical OR of bits 1 and 0" "0,1" line.long 0x4 "CPSW_REGS_INT_SS_C3_TH_IMAX_REG,Core 3 THost Interrupt Max Register Register" hexmask.long.byte 0x4 0.--5. 1. "TH_IMAX,Core 3 THost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C3_TH_PULSE if pacing is enabled for this interrupt." line.long 0x8 "CPSW_REGS_INT_SS_C3_FH_IMAX_REG,Core 3 FHost Interrupt Max Register Register" hexmask.long.byte 0x8 0.--5. 1. "FH_IMAX,Core 3 FHost Interrupts per millisecond - The maximum number of interrupts per millisecond generated on C3_FH_PULSE if pacing is enabled for this interrupt." rgroup.long 0x20000++0x3 line.long 0x0 "CPSW_NC_VER_REG,CPSW ID Version" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor Version Value" group.long 0x20004++0x3 line.long 0x0 "CPSW_NC_CONTROL_REG,CPSW Switch Control" bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode - 0 - ECC errors induced through the ECC aggregator flip bits in the packet headers (not in packet data). 1 - ECC errors induced through the ECC aggregator flip bits in the packet data (not in the packet headers)." "0,1" bitfld.long 0x0 18. "EST_ENABLE,Enhanced Scheduled Traffic enable (EST) - 0 - EST is disabled. 1 - EST is enabled" "0,1" newline bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable - 0 - Energy Efficient Ethernet is disabled. 1 - Energy Efficient Ethernet is enabled." "0,1" bitfld.long 0x0 15. "P0_FH_PASS_CRC_ERR,Port 0 Pass Received CRC errors - 0 - Packets received with CRC errors on port 0 are dropped. 1 - Packets received with CRC errors on port 0 are transferred to the destination ports." "0,1" newline bitfld.long 0x0 14. "P0_FH_PAD,Port 0 Receive Short Packet Pad - 0 - short packets are dropped. 1 - short packets are padded to 64-bytes (with pad and added CRC) if the CRC is not passed in. Short packets are dropped if the CRC is passed (in the Info0 word)." "0,1" bitfld.long 0x0 13. "P0_TH_CRC_REMOVE,Port 0 Transmit CRC remove - 0 - Do not remove the CRC on Port 0 THost (egress) packets. 1 - Remove the CRC on all Port 0 THost (egress) packets." "0,1" newline bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P8_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P7_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" newline bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P6_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P5_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" newline bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P4_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P3_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" newline bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P2_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P1_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" newline bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P0_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged." "0,1" bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable - 0 - Port 0 is disabled 1 - Port 0 is enabled" "0,1" newline bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode - 0 - CPSW_NU is in the VLAN unaware mode. 1 - CPSW_NU is in the VLAN aware mode." "0,1" bitfld.long 0x0 0. "S_CN_SWITCH,Service or Customer VLAN switch. 0 - Customer switch. VLAN processing uses the inner_vlan_ltype. 1 - Service switch. VLAN processing uses the outer_vlan_ltype." "0,1" rgroup.long 0x2000C++0x3 line.long 0x0 "CPSW_NC_STATUS_REG,CPSW Status" bitfld.long 0x0 0. "CPPI_IDLE,CPPI Idle - Indicates when set that the CPPI port transmit and receive are idle." "0,1" group.long 0x20010++0x17 line.long 0x0 "CPSW_NC_EM_CONTROL_REG,CPSW Emulation Control" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_NC_STAT_PORT_EN_REG,CPSW Statistics Port Enable" bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" newline bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" newline bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" newline bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" newline bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable 0 - Statistics are disabled for the port. 1 - Statistics are enabled for the port." "0,1" line.long 0x8 "CPSW_NC_PTYPE_REG,CPSW Transmit Priority Type" bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" newline bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" newline bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" newline bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" newline bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate - 0 - Priority Type Fixed. 1 - Priority Type Escalate" "0,1" hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value - When a port is in escalate priority this is the number of higher priority packets sent before the next lower priority is allowed to send a packet. Escalate priority allows lower priority packets to be sent.." line.long 0xC "CPSW_NC_SOFT_IDLE_REG,CPSW Software Idle" bitfld.long 0xC 0. "SOFT_IDLE,Software Idle - 0 - Software idle not commanded. 1 - Command CPSW software idle. When set port 0 packet DMA operations stop at the next packet boundary." "0,1" line.long 0x10 "CPSW_NC_THRU_RATE_REG,CPSW Thru Rate" hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,This is not a field intended to be changed by software" hexmask.long.byte 0x10 0.--3. 1. "P0_FH_THRU_RATE,This is not a field intended to be changed by software" line.long 0x14 "CPSW_NC_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold" hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Ethernet Port Short Gap Threshold - This is the Ethernet port associated FIFO transmit block usage value for triggering transmit short gap (when short gap is enabled)." group.long 0x2002C++0x1B line.long 0x0 "CPSW_NC_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value" hexmask.long.word 0x0 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Prescale count load value - This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero. The EEE counters are enabled to decrement each time the pre-scale counter reaches.." line.long 0x4 "CPSW_NC_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set" hexmask.long.byte 0x4 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" hexmask.long.byte 0x4 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" newline hexmask.long.byte 0x4 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" hexmask.long.byte 0x4 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" newline hexmask.long.byte 0x4 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" hexmask.long.byte 0x4 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x4 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" hexmask.long.byte 0x4 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x8 "CPSW_NC_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear" hexmask.long.byte 0x8 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" hexmask.long.byte 0x8 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" newline hexmask.long.byte 0x8 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" hexmask.long.byte 0x8 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" newline hexmask.long.byte 0x8 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" hexmask.long.byte 0x8 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x8 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" hexmask.long.byte 0x8 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0xC "CPSW_NC_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low" hexmask.long.byte 0xC 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" hexmask.long.byte 0xC 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" newline hexmask.long.byte 0xC 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" hexmask.long.byte 0xC 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x10 "CPSW_NC_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High" hexmask.long.byte 0x10 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" hexmask.long.byte 0x10 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" newline hexmask.long.byte 0x10 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" hexmask.long.byte 0x10 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" line.long 0x14 "CPSW_NC_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low" hexmask.long.byte 0x14 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" hexmask.long.byte 0x14 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" newline hexmask.long.byte 0x14 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" hexmask.long.byte 0x14 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x18 "CPSW_NC_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High" hexmask.long.byte 0x18 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" hexmask.long.byte 0x18 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" newline hexmask.long.byte 0x18 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" hexmask.long.byte 0x18 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" group.long 0x20050++0x7 line.long 0x0 "CPSW_NC_VLAN_LTYPE_REG,VLAN Length/type" hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType" hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType" line.long 0x4 "CPSW_NC_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain" hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic domain. This value is used as the domain in the CPTS event to indicate that the event came from EST." group.long 0x20100++0x1F line.long 0x0 "CPSW_NC_TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length" hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 0 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0x4 "CPSW_NC_TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length" hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 1 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0x8 "CPSW_NC_TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length" hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 2 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0xC "CPSW_NC_TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length" hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 3 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0x10 "CPSW_NC_TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length" hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 4 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0x14 "CPSW_NC_TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length" hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 5 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0x18 "CPSW_NC_TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length" hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 6 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." line.long 0x1C "CPSW_NC_TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length" hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,This value determines the maximum packet length that will be transmitted on priority 7 Ethernet egress for all Ethernet ports. The packet length compared to the maximum length value is the ingress packet length (not the actual egress.." group.long 0xF80++0x7 line.long 0x0 "CPSW_MDIO_USER_GROUP_USER_ACCESS_REG_j,MDIO User Access Register" bitfld.long 0x0 31. "GO,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state.." "0,1" bitfld.long 0x0 30. "WRITE,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write otherwise it is a register read." "0,1" newline bitfld.long 0x0 29. "ACK,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address. This field specifies the PHY register to be accessed for this transaction in clause 22 mode or the MMD value in clause 45 mode." newline hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address. This field specifies the PHY to be accessed for this transaction." hexmask.long.word 0x0 0.--15. 1. "DATA,User data. The data value read from or to be written to the specified PHY register." line.long 0x4 "CPSW_MDIO_USER_GROUP_USER_PHY_SEL_REG_j,MDIO User PHY Select Register" bitfld.long 0x4 7. "LINKSEL,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is to be monitored." group.long 0x21004++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_CONTROL_REG,CPPI Port 0 Control" bitfld.long 0x0 18. "FH_REMAP_DSCP_V6,Port 0 FHost (ingress) remap priority to DSCP IPV6 priority (see packet priority handling section for details). 0 - Hardware switch priority IPV6 DSCP priority remapping is disabled. 1 - Hardware switch priority IPV6 DSCP.." "0,1" bitfld.long 0x0 17. "FH_REMAP_DSCP_V4,Port 0 FHost (ingress) remap priority to DSCP IPV4 priority (see packet priority handling section for details). 0 - Hardware switch priority IPV4 DSCP priority remapping is disabled. 1 - Hardware switch priority IPV4 DSCP.." "0,1" newline bitfld.long 0x0 16. "FH_REMAP_VLAN,Port 0 receive (ingress) remap priority to VLAN. See priority remapping section for details." "0,1" bitfld.long 0x0 15. "FH_ECC_ERR_EN,Port 0 FHost ECC Error Enable. This bit must be set to enable FHost ECC error operations" "0,1" newline bitfld.long 0x0 14. "TH_ECC_ERR_EN,Port 0 THost ECC Error Enable. This bit must be set to enable THost ECC error operations." "0,1" bitfld.long 0x0 3. "TH_CHECKSUM_EN,Port 0 THost (egress) Checksum Enable 0 - THost checksum is disabled. 1 - THost checksum is enabled. IPV4/V6 Packets have checksum information (4-bytes) included at the end of the packet data when the chksum_encap descriptor.." "0,1" newline bitfld.long 0x0 2. "FH_DSCP_IPV6_EN,Port 0 FHost IPv6 DSCP enable 0 - Ipv6 DSCP priority mapping is disabled. 1 - Ipv6 DSCP priority mapping is enabled." "0,1" bitfld.long 0x0 1. "FH_DSCP_IPV4_EN,Port 0 FHost IPv4 DSCP enable 0 - Ipv4 DSCP priority mapping is disabled. 1 - Ipv4 DSCP priority mapping is enabled." "0,1" newline bitfld.long 0x0 0. "FH_CHECKSUM_EN,Port 0 FHost (port 0 ingress) Checksum Enable 0 - FHost checksum is disabled. 1 - FHost checksum is enabled. Four bytes of checksum information can be included at the start of the packet data to be used for checksum packet.." "0,1" rgroup.long 0x21010++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count" hexmask.long.byte 0x0 8.--12. 1. "TH_BLK_CNT,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues. note: for N=2 this field is always zero (no transmit FIFO)." hexmask.long.byte 0x0 0.--5. 1. "FH_BLK_CNT,Port 0 Receive Block Count Usage - This value is the number of blocks allocated in the receive FIFO." group.long 0x21014++0x17 line.long 0x0 "CPSW_NC_CPPI_P0_PORT_VLAN_REG,CPPI Port 0 VLAN" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_NC_CPPI_P0_TH_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping" bitfld.long 0x4 28.--30. "PRI7,Priority 7 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PRI6,Priority 6 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "PRI5,Priority 5 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PRI4,Priority 4 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "PRI2,Priority 2 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "PRI1,Priority 1 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "PRI0,Priority 0 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NC_CPPI_P0_PRI_CTL_REG,CPPI Port 0 Priority Control" hexmask.long.byte 0x8 16.--23. 1. "FH_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority). Note: for N=2 this field should remain zero." bitfld.long 0x8 8. "FH_PTYPE,Receive Priority Type" "0,1" line.long 0xC "CPSW_NC_CPPI_P0_FH_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map" bitfld.long 0xC 28.--30. "PRI7,Priority 7 - A packet priority of 0x7 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "PRI6,Priority 6 - A packet priority of 0x6 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "PRI5,Priority 5 - A packet priority of 0x5 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "PRI4,Priority 4 - A packet priority of 0x4 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3 - A packet priority of 0x3 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "PRI2,Priority 2 - A packet priority of 0x2 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "PRI1,Priority 1 - A packet priority of 0x1 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "PRI0,Priority 0 - A packet priority of 0x0 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_NC_CPPI_P0_FH_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length" hexmask.long.word 0x10 0.--13. 1. "FH_MAXLEN,Port 0 Ingress Maximum Frame Length - This field determines the maximum length of a received frame. The reset value is 1518 (dec). Frames with byte counts greater than p0_fh_maxlen are long frames. Long frames with no errors are oversized.." line.long 0x14 "CPSW_NC_CPPI_P0_TH_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority" hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks" hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks" newline hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks" hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks" newline hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks" hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks" hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks" group.long 0x21030++0x7 line.long 0x0 "CPSW_NC_CPPI_P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit is not idle. Port 0 enters the transmit LPI state when this counter.." line.long 0x4 "CPSW_NC_CPPI_P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 0 LPI to wake counter. Transmit packet operations may begin (resume) when the LPI.." rgroup.long 0x21038++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_EEE_STATUS_REG,Port 0 EEE status" bitfld.long 0x0 6. "TH_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1" bitfld.long 0x0 5. "FH_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1" newline bitfld.long 0x0 4. "TH_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1" bitfld.long 0x0 3. "TH_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1" newline bitfld.long 0x0 2. "TH_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1" bitfld.long 0x0 1. "FH_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1" newline bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1" rgroup.long 0x21050++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_FIFO_STATUS_REG,Port 0 FIFO Status" hexmask.long.byte 0x0 0.--7. 1. "TH_PRI_ACTIVE,Port 0 Transmit FIFO Priority Active. Each bit indicates whether the corresponding FIFO priority has one or more queued packets on it or not. note: for N=2 this field is always zero (there is no transmit FIFO)." group.long 0x21120++0x3 line.long 0x0 "CPSW_NC_CPPI_FH_DSCP_MAP_REG_j,CPPI Receive IPV4/IPV6 DSCP Map N" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS 7 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS 6 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS 5 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS 4 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS 3 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS 2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS 1 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS 0 is mapped to this received priority" "0,1,2,3,4,5,6,7" group.long 0x21140++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_PRI_CIR_REG_j,CPPI Port 0 Rx Priority P Committed Information Rate" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N Committed Information Rate" group.long 0x21160++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_PRI_EIR_REG_j,CPPI Port 0 Rx Priority P Excess Information Rate" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate" group.long 0x21180++0x1F line.long 0x0 "CPSW_NC_CPPI_P0_TH_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_NC_CPPI_P0_TH_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_NC_CPPI_P0_TH_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_NC_CPPI_P0_TH_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_NC_CPPI_P0_TH_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_NC_CPPI_P0_TH_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_NC_CPPI_P0_TH_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_NC_CPPI_P0_TH_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" group.long 0x21300++0x7 line.long 0x0 "CPSW_NC_CPPI_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A" hexmask.long.byte 0x0 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value" hexmask.long.byte 0x0 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x0 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value" hexmask.long.byte 0x0 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value" line.long 0x4 "CPSW_NC_CPPI_P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B" hexmask.long.byte 0x4 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value" hexmask.long.byte 0x4 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value" newline hexmask.long.byte 0x4 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value" hexmask.long.byte 0x4 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value" group.long 0x21320++0x3 line.long 0x0 "CPSW_NC_CPPI_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority" hexmask.long.byte 0x0 28.--31. 1. "PRI7,Priority 7 Host Blocks" hexmask.long.byte 0x0 24.--27. 1. "PRI6,Priority 6 Host Blocks" newline hexmask.long.byte 0x0 20.--23. 1. "PRI5,Priority 5 Host Blocks" hexmask.long.byte 0x0 16.--19. 1. "PRI4,Priority 4 Host Blocks" newline hexmask.long.byte 0x0 12.--15. 1. "PRI3,Priority 3 Host Blocks" hexmask.long.byte 0x0 8.--11. 1. "PRI2,Priority 2 Host Blocks" newline hexmask.long.byte 0x0 4.--7. 1. "PRI1,Priority 1 Host Blocks" hexmask.long.byte 0x0 0.--3. 1. "PRI0,Priority 0 Host Blocks" group.long 0x22004++0x7 line.long 0x0 "CPSW_NC_ETH_MAC_PN_CONTROL_REG_j,Enet Port N Control" bitfld.long 0x0 17. "EST_PORT_EN,EST Port Enable 0 - EST is disabled on the port. 1 - EST is enabled on the port (Does not take effect until the CPSW level est_en is set)." "0,1" bitfld.long 0x0 15. "RX_ECC_ERR_EN,This bit must be set to enable receive ECC error operations on the port." "0,1" newline bitfld.long 0x0 14. "TX_ECC_ERR_EN,This bit must be set to enable transmit ECC error operations on the port." "0,1" bitfld.long 0x0 12. "TX_LPI_CLKSTOP_EN,Transmit LPI Clock Stop Enable - When set this bit causes the transmit output clock (GMII_GMTCLK_O) to be stopped when the transmit LPI state is entered if EEE is enabled." "0,1" newline bitfld.long 0x0 2. "DSCP_IPV6_EN,IPv6 DSCP enable 0 - Ipv6 DSCP priority mapping is disabled. 1 - Ipv6 DSCP priority mapping is enabled." "0,1" bitfld.long 0x0 1. "DSCP_IPV4_EN,IPv4 DSCP enable 0 - Ipv4 DSCP priority mapping is disabled. 1 - Ipv4 DSCP priority mapping is enabled." "0,1" line.long 0x4 "CPSW_NC_ETH_MAC_PN_MAX_BLKS_REG_j,Enet Port N FIFO Max Blocks" hexmask.long.byte 0x4 8.--15. 1. "TX_MAX_BLKS,Transmit Max Blocks - The maximum number of blocks allowed on all transmit FIFO priorities combined. If (fifo_oneram = 1) then blocks should be moved from transmit to receive when flow control is enabled to allow for flow control runout." hexmask.long.byte 0x4 0.--7. 1. "RX_MAX_BLKS,Receive Max Blocks - The maximum number of blocks allowed on the express and prempt receive FIFOs (transmit and receive FIFOs combined when fifo_oneram = 1)" rgroup.long 0x22010++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_BLK_CNT_REG_j,Enet Port N FIFO Block Usage Count" hexmask.long.byte 0x0 16.--21. 1. "RX_BLK_CNT_P,Receive Express Block Count Usage - This value is the number of blocks allocated to the port FIFO prempt receive queue. No blocks are allocated until the iet_en in the CPSW_Control register is set." hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Transmit Block Count Usage - This value is the number of blocks allocated to the port FIFO logical transmit queues." newline hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT_E,Receive Express Block Count Usage - This value is the number of blocks allocated to the ports FIFO express receive queue." group.long 0x22014++0x17 line.long 0x0 "CPSW_NC_ETH_MAC_PN_PORT_VLAN_REG_j,Enet Port N VLAN" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_NC_ETH_MAC_PN_TX_PRI_MAP_REG_j,Enet Port N Tx Header Pri to Switch Pri Mapping" bitfld.long 0x4 28.--30. "PRI7,Priority 7 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PRI6,Priority 6 - A packet header priority of 0x6 is given this switch queue priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "PRI5,Priority 5 - A packet header priority of 0x5 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PRI4,Priority 4 - A packet header priority of 0x4 is given this switch queue priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3 - A packet header priority of 0x3 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "PRI2,Priority 2 - A packet header priority of 0x2 is given this switch queue priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "PRI1,Priority 1 - A packet header priority of 0x1 is given this switch queue priority." "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "PRI0,Priority 0 - A packet header priority of 0x0 is given this switch queue priority." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NC_ETH_MAC_PN_PRI_CTL_REG_j,Enet Port N Priority Control" hexmask.long.byte 0x8 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)" hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)" newline hexmask.long.byte 0x8 12.--15. 1. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" line.long 0xC "CPSW_NC_ETH_MAC_PN_RX_PRI_MAP_REG_j,Enet Port N RX Pkt Pri to Header Pri Map" bitfld.long 0xC 28.--30. "PRI7,Priority 7 - A packet priority of 7 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "PRI6,Priority 6 - A packet priority of 6 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "PRI5,Priority 5 - A packet priority of 5 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--18. "PRI4,Priority 4 - A packet priority of 4 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3 - A packet priority of 3 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "PRI2,Priority 2 - A packet priority of 2 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "PRI1,Priority 1 - A packet priority of 1 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "PRI0,Priority 0 - A packet priority of 0 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_NC_ETH_MAC_PN_RX_MAXLEN_REG_j,Enet Port N Receive Frame Max Length" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length - This field determines the maximum length of a received frame. The reset value is 1518 (dec). Frames with byte counts greater than pn_rx_maxlen are long frames. Long frames with no errors are oversized frames. Long.." line.long 0x14 "CPSW_NC_ETH_MAC_PN_TX_BLKS_PRI_REG_j,Enet Port N Transmit Block Sub Per Priority" hexmask.long.byte 0x14 28.--31. 1. "PRI7,Transmit Blocks Per Priority 7 (subtract value)" hexmask.long.byte 0x14 24.--27. 1. "PRI6,Transmit Blocks Per Priority 6 (subtract value)" newline hexmask.long.byte 0x14 20.--23. 1. "PRI5,Transmit Blocks Per Priority 5 (subtract value)" hexmask.long.byte 0x14 16.--19. 1. "PRI4,Transmit Blocks Per Priority 4 (subtract value)" newline hexmask.long.byte 0x14 12.--15. 1. "PRI3,Transmit Blocks Per Priority 3 (subtract value)" hexmask.long.byte 0x14 8.--11. 1. "PRI2,Transmit Blocks Per Priority 2 (subtract value)" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Transmit Blocks Per Priority 1 (subtract value)" hexmask.long.byte 0x14 0.--3. 1. "PRI0,Transmit Blocks Per Priority 0 (subtract value)" group.long 0x22030++0x7 line.long 0x0 "CPSW_NC_ETH_MAC_PN_IDLE2LPI_REG_j,Enet Port N EEE Idle to LPI counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port idle to LPI counter on each clock that the port transmit is not idle. The port enters the transmit LPI state when this counter decrements to.." line.long 0x4 "CPSW_NC_ETH_MAC_PN_LPI2WAKE_REG_j,Enet Port N EEE LPI to wake counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the LPI to wake counter. Transmit packet operations may begin (resume) when the LPI to wake count.." rgroup.long 0x22038++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_EEE_STATUS_REG_j,Enet Port N EEE status" bitfld.long 0x0 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1" bitfld.long 0x0 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1" bitfld.long 0x0 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1" newline bitfld.long 0x0 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1" bitfld.long 0x0 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1" newline bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1" rgroup.long 0x22050++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_FIFO_STATUS_REG_j,Enet Port N FIFO STATUS" bitfld.long 0x0 18. "EST_BUFACT,EST RAM active buffer - Indicates the active 64-word fetch buffer when pn_est_onebuf is cleared to zero. Indicates the fetch ram address MSB when pn_est_onebuf set to one." "0,1" bitfld.long 0x0 17. "EST_ADD_ERR,EST Address Error - Indicates that the fetch ram was read again after the previous maximum buffer address read (the previous fetch from the maximum address is reused)." "0,1" newline bitfld.long 0x0 16. "EST_CNT_ERR,EST Fetch Count Error - Indicates that insufficient clocks were programmed into the fetch count and that another fetch was commanded before the previous fetch finished." "0,1" hexmask.long.byte 0x0 8.--15. 1. "TX_E_MAC_ALLOW,Transmit mac allow - Bus that indicates the actual priorities assigned to the express queue (and inversely the priorities assigned to the prempt queue). The pn_mac_prempt[7:0] field in the Enet_Pn_IET_Control register indicates which.." newline hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Transmit Priority Active - Bus that indicates which priorities have packets (non-empty) at the time of the register read." group.long 0x22060++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_EST_CONTROL_REG_j,Enet Port N EST CONTROL" hexmask.long.word 0x0 16.--25. 1. "EST_FILL_MARGIN,EST Fill Margin - Sets the fill margin (in bytes) required to ensure that the Ethernet wire is clear so that the timed EST express packet can egress at the correct required time. Setting this value too high will put an unnecessary gap on.." hexmask.long.byte 0x0 9.--15. 1. "EST_PREMPT_COMP,EST Prempt Comparison Value - When the count in a zero allow is less than or equal to this value in bytes (times 8) prempt packets are cleared from the wire. This is the prempt clear margin value." newline bitfld.long 0x0 8. "EST_FILL_EN,EST Fill Enable - Enable EST fill mode when set." "0,1" bitfld.long 0x0 5.--7. "EST_TS_PRI,EST Timestamp Express Priority - Selects the express priority that timestamp(s) will be generated on when pn_est_ts_onepri is set." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "EST_TS_ONEPRI,EST Timestamp One Express Priority - When set timestamps are only enabled on packets on the express priority selected by pn_est_ts_pri. When cleared to zero express packet selection for timestamps is independent of priority." "0,1" bitfld.long 0x0 3. "EST_TS_FIRST,EST Timestamp First Express Packet only - Generate a timestamp only on the first selected express packet in each EST time interval when express timestamps are enabled. (If pn_est_ts_onepri is also set then the timestamp is generated only on.." "0,1" newline bitfld.long 0x0 2. "EST_TS_EN,EST Timestamp Enable - Enable express timestamps (when est_en and pn_est_port_en are set)." "0,1" bitfld.long 0x0 1. "EST_BUFSEL,EST Buffer Select - If pn_est_onebuf is cleared this bit selects the upper (when set) or the lower (when cleared) 64-word fetch buffer. The actual fetch buffer used changes only at the start of the EST time interval and can be read in the.." "0,1" newline bitfld.long 0x0 0. "EST_ONEBUF,EST One Fetch Buffer - When set indicates that all 128 fetch words are used in one buffer. When cleared indicates that the 128 fetch words are split into two 64-word fetch buffers. The pn_est_bufsel selects the buffer to be used when.." "0,1" group.long 0x22120++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_FH_DSCP_MAP_REG_j_k,Enet Port N Receive IPV4/IPV6 DSCP Map N" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS 7 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS 6 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS 5 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS 4 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS 3 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS 2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS 1 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS 0 is mapped to this received priority" "0,1,2,3,4,5,6,7" group.long 0x22140++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_PRI_CIR_REG_j_k,Enet Port N Rx Priority P Committed Information Rate Value" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N committed information rate" group.long 0x22160++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_PRI_EIR_REG_j_k,Enet Port N Rx Priority P Excess Informatoin Rate Value" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count" group.long 0x22180++0x1F line.long 0x0 "CPSW_NC_ETH_MAC_PN_TX_D_THRESH_SET_L_REG_j,Enet Port N Tx PFC Destination Threshold Set Low" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_NC_ETH_MAC_PN_TX_D_THRESH_SET_H_REG_j,Enet Port N Tx PFC Destination Threshold Set High" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_NC_ETH_MAC_PN_TX_D_THRESH_CLR_L_REG_j,Enet Port N Tx PFC Destination Threshold Clr Low" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_NC_ETH_MAC_PN_TX_D_THRESH_CLR_H_REG_j,Enet Port N Tx PFC Destination Threshold Clr High" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_NC_ETH_MAC_PN_TX_G_BUF_THRESH_SET_L_REG_j,Enet Port N Tx PFC Global Buffer Threshold Set Low" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" newline hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_NC_ETH_MAC_PN_TX_G_BUF_THRESH_SET_H_REG_j,Enet Port N Tx PFC Global Buffer Threshold Set High" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" newline hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_NC_ETH_MAC_PN_TX_G_BUF_THRESH_CLR_L_REG_j,Enet Port N Tx PFC Global Buffer Threshold Clr Low" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" newline hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_NC_ETH_MAC_PN_TX_G_BUF_THRESH_CLR_H_REG_j,Enet Port N Tx PFC Global Buffer Threshold Clr High" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" newline hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" group.long 0x22300++0x23 line.long 0x0 "CPSW_NC_ETH_MAC_PN_TX_D_OFLOW_ADDVAL_L_REG_j,Enet Port N Tx Destination Out Flow Add Values Low" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" newline hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" line.long 0x4 "CPSW_NC_ETH_MAC_PN_TX_D_OFLOW_ADDVAL_H_REG_j,Enet Port N Tx Destination Out Flow Add Values High" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" newline hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" line.long 0x8 "CPSW_NC_ETH_MAC_PN_SA_L_REG_j,Enet Port N Tx Pause Frame Source Address Low" hexmask.long.byte 0x8 8.--15. 1. "MACSRCADDR_7_0,Source Address bits 7:0" hexmask.long.byte 0x8 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8" line.long 0xC "CPSW_NC_ETH_MAC_PN_SA_H_REG_j,Enet Port N Tx Pause Frame Source Address High" hexmask.long.byte 0xC 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16" hexmask.long.byte 0xC 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24" newline hexmask.long.byte 0xC 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32" hexmask.long.byte 0xC 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40" line.long 0x10 "CPSW_NC_ETH_MAC_PN_TS_CTL_REG_j,Enet Port N Time Sync Control" hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1" newline bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Synce Transmit Annex E Enable" "0,1" bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Synce Receive Annex E Enable" "0,1" newline bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 Enable (transmit and receive)" "0,1" bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Synce Transmit Annex D Enable" "0,1" newline bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable" "0,1" bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable" "0,1" newline bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Synce Transmit Annex F Enable" "0,1" bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Synce Receive Annex D Enable" "0,1" newline bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable" "0,1" bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable" "0,1" newline bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Synce Receive Annex F Enable" "0,1" line.long 0x14 "CPSW_NC_ETH_MAC_PN_TS_SEQ_LTYPE_REG_j,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)" hexmask.long.byte 0x14 16.--21. 1. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset - This is the number of octets that the sequence ID is offset in the tx and rx time sync message header. The minimum value is 6." hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1 - This is the port time sync LTYPE1 value" line.long 0x18 "CPSW_NC_ETH_MAC_PN_TS_VLAN_LTYPE_REG_j,Enet Port N Time Sync VLAN2 and VLAN2" hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2" hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1" line.long 0x1C "CPSW_NC_ETH_MAC_PN_TS_CTL_LTYPE2_REG_j,Enet Port N Time Sync Control and LTYPE 2" bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1" bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1" newline bitfld.long 0x1C 22. "TS_320,Time Sync Destination Port Number 320 Enable" "0,1" bitfld.long 0x1C 21. "TS_319,Time Sync Destination Port Number 319 Enable" "0,1" newline bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1" bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1" newline bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1" bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1" newline bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1" hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2 value" line.long 0x20 "CPSW_NC_ETH_MAC_PN_TS_CTL2_REG_j,Enet Port N Time Sync Control 2" hexmask.long.byte 0x20 16.--21. 1. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable" group.long 0x22330++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_CONTROL_REG_j,Enet Port N Mac Control" bitfld.long 0x0 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory. MAC control frames are normally acted upon (if enabled) but not copied/transferred to memory. MAC control frames that are pause frames will be acted.." "0,1" bitfld.long 0x0 23. "RX_CSF_EN,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be sent to the host. Frames transferred to the host due to pn_rx_csf_en will have the fragment or undersized bit set in their buffer descriptor. Short and.." "0,1" newline bitfld.long 0x0 22. "RX_CEF_EN,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame receive buffer descriptor. Frames containing errors will be filtered when this bit is not set." "0,1" bitfld.long 0x0 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable - When set this bit limits the number of short gap packets transmitted to 100ppm. The pn_tx_short_gap_en bit must also be set. Each time a short gap packet is sent a counter is loaded with 10 000 and.." "0,1" newline bitfld.long 0x0 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable - Enables the pn_tx_flow_en to be selected from the EXT_TX_FLOW_EN input signal and not from the pn_tx_flow_en bit in this register." "0,1" bitfld.long 0x0 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable - Enables the pn_rx_flow_en to be selected from the EXT_RX_FLOW_EN input signal and not from the pn_rx_flow_en bit in this register." "0,1" newline bitfld.long 0x0 18. "EXT_EN,External Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the pn_fullduplex and pn_gig bits in this register. The FULLDUPLEX_MODE bit reflects the actual.." "0,1" bitfld.long 0x0 17. "GIG_FORCE,Gigabit Mode Force - This bit is used to force the Enet Mac into gigabit mode if the input GMII_MTCLK has been stopped by the PHY. 0 - GIG mode not forced 1 - GIG mode forced regardless of transmit clock" "0,1" newline bitfld.long 0x0 16. "IFCTL_B,Interface Control B - Intended as a general purpose output bit to be used to control external gaskets associated with the GMII (GMII to RGMII etc)." "0,1" bitfld.long 0x0 15. "IFCTL_A,Interface Control A - Intended as a general purpose output bit to be used to control external gaskets associated with the GMII (GMII to RGMII etc)." "0,1" newline bitfld.long 0x0 12. "CRC_TYPE,Port CRC Type - 0 - Ethernet CRC. 1 - Castagnoli CRC." "0,1" bitfld.long 0x0 11. "CMD_IDLE,Command Idle - 0 - Idle not commanded. 1 - Idle Commanded (read pn_idle in Enet_Pn_Mac_Status)." "0,1" newline bitfld.long 0x0 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable 0 - Transmit with a short IPG is disabled. 1 - Transmit with a short IPG is enabled." "0,1" bitfld.long 0x0 7. "GIG,Gigabit Mode - 0 - 10/100 mode. 1 - Gigabit mode (full duplex only) The GIG_OUT output is the value of this bit. This bit is a don't care when pn_xgig is set." "0,1" newline bitfld.long 0x0 6. "TX_PACE,Transmit Pacing Enable - 0 - Transmit Pacing Disabled. 1 - Transmit Pacing Enabled" "0,1" bitfld.long 0x0 5. "GMII_EN,GMII Enable - 0 - GMII RX and TX held in reset. 1 - GMII RX and TX released from reset. This bit should be written with a logic high before the other bits in this register are written." "0,1" newline bitfld.long 0x0 4. "TX_FLOW_EN,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode regardless of this bit setting. The RX_MBP_Enable bits determine whether or.." "0,1" bitfld.long 0x0 3. "RX_FLOW_EN,Receive Flow Control Enable - 0 - Receive Flow Control Disabled: Half-duplex mode - No flow control generated collisions are sent. Full-duplex mode - No outgoing pause frames are sent. 1 - Receive Flow Control Enabled:.." "0,1" newline bitfld.long 0x0 2. "MTEST,Manufacturing Test mode - This bit must be set to allow writes to the Backoff_Test and PauseTimer registers." "0,1" bitfld.long 0x0 1. "LOOPBACK,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the pn_fullduplex bit is set or not. The pn_loopback bit should be changed only when pn_gmii_en is de-asserted. Loopback is used only with GMII (not XGMII)." "0,1" newline bitfld.long 0x0 0. "FULLDUPLEX,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the pn_fullduplex bit is set or not. The FULLDUPLEX_OUT output is the value of this register bit. 0 - half duplex mode. 1 - full duplex mode." "0,1" rgroup.long 0x22334++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_STATUS_REG_j,Enet Port N Mac Status" bitfld.long 0x0 31. "IDLE,Enet IDLE - The Ethernet port (express and prempt) is in the idle state when high." "0,1" bitfld.long 0x0 30. "E_IDLE,Express MAC is idle when high" "0,1" newline bitfld.long 0x0 28. "MAC_TX_IDLE,Mac Transmit Idle - Both Prempt (if iet_incl) and Express MAC Transmit are in idle state.The transmit clock must be running for this to go idle." "0,1" bitfld.long 0x0 27. "TORF,Top of receive FIFO flow control trigger occurred. This bit is write one to clear." "0,1" newline bitfld.long 0x0 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear. This field is write 0x7 to clear." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--23. 1. "TX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)." newline hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)." bitfld.long 0x0 6. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable - This is the value of the EXT_TX_FLOW_EN input bit." "0,1" newline bitfld.long 0x0 5. "EXT_RX_FLOW_EN,External Receive Flow Control Enable - This is the value of the EXT_RX_FLOW_EN input bit." "0,1" bitfld.long 0x0 4. "EXT_GIG,External GIG - This is the value of the EXT_GIG input bit." "0,1" newline bitfld.long 0x0 3. "EXT_FULLDUPLEX,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit." "0,1" bitfld.long 0x0 1. "RX_FLOW_ACT,Receive Flow Control Active - When asserted indicates that receive flow control is enabled and triggered." "0,1" newline bitfld.long 0x0 0. "TX_FLOW_ACT,Transmit Flow Control Active - When asserted this bit indicates that the pause time period is being observed for a received pause frame. No new transmissions will begin while this bit is asserted except for the transmission of pause frames." "0,1" group.long 0x22338++0xB line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_SOFT_RESET_REG_j,Enet Port N Mac Soft Reset" bitfld.long 0x0 0. "SOFT_RESET,Software reset" "0,1" line.long 0x4 "CPSW_NC_ETH_MAC_PN_MAC_BOFFTEST_REG_j,Enet Port N Mac Backoff Test" hexmask.long.byte 0x4 26.--30. 1. "PACEVAL,Pacing Current Value - A non-zero value in this field indicates that transmit pacing is active. A transmit frame collision or deferral causes paceval to loaded with decimal 31 good frame transmissions (with no collisions or deferrals) cause.." hexmask.long.word 0x4 16.--25. 1. "RNDNUM,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only). This field can be written only when pn_mtest has previously been set. Reading this field returns the generator's.." newline hexmask.long.byte 0x4 12.--15. 1. "COLL_COUNT,Collision Count - The number of collisions the current frame has experienced." hexmask.long.word 0x4 0.--9. 1. "TX_BACKOFF,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes. This field is loaded automatically according to the backoff algorithm and is decremented by one for each slot time after the.." line.long 0x8 "CPSW_NC_ETH_MAC_PN_MAC_RX_PAUSETIMER_REG_j,Enet Port N 802.3 Receive Pause Timer" hexmask.long.word 0x8 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode). The receive pause timer is loaded with 0xFF00 when the Enet port sends an outgoing pause frame (with pause time of.." group.long 0x22350++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_RXN_PAUSETIMER_REG_j_k,Enet Port N PFC Priority 0 Rx Pause Timer" hexmask.long.word 0x0 0.--15. 1. "RX0_PAUSETIMER,Rx N Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode). The receive pause timer is loaded with 0xFF00 when the Enet port sends an outgoing pause frame (with pause time.." group.long 0x22370++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_TX_PAUSETIMER_REG_j,Enet Port N 802.3 Tx Pause Timer" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,802.3 Tx Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode). The transmit pause timer is loaded by a received (incoming) pause frame and then decremented at slottime.." group.long 0x22380++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_TX0_PAUSETIMER_REG_j_k,Enet Port N PFC Priority 0 Tx Pause Timer" hexmask.long.word 0x0 0.--15. 1. "TX0_PAUSETIMER,PFC Tx N Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode). The transmit pause timer is loaded by a received (incoming) pause frame and then decremented at slottime.." group.long 0x223A0++0x7 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_EMCONTROL_REG_j,Enet Port N Emulation Control" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_NC_ETH_MAC_PN_MAC_TX_GAP_REG_j,Enet Port N Tx Inter Packet Gap" hexmask.long.word 0x4 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap - GMII modes - This is the default gap value and only bits 8:0 are used. This can be increased from 12 to increase the gap between packets. XGMII mode - In 10 gigabit mode this is the short gap rate and should be.." rgroup.long 0x223A8++0x3 line.long 0x0 "CPSW_NC_ETH_MAC_PN_MAC_PORT_CONFIG_j,Enet Port N Port Configuration" bitfld.long 0x0 9. "IET,IET support" "0,1" bitfld.long 0x0 8. "XGMII,No XGMII support on this port" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "INTERVLAN_ROUTES,The number of InterVLAN routes supported on this port (egress)" group.long 0x223AC++0x13 line.long 0x0 "CPSW_NC_ETH_MAC_PN_INTERVLAN_OPX_POINTER_REG_j,Enet Port N Tx Egress InterVLAN Operation Pointer" bitfld.long 0x0 0.--1. "POINTER,InterVLAN location pointer - This field points to the InterVLAN location that will be read/written by accesses to Enet_Pn_InterVLANx_A/B/C (the InterVLAN locations are accessed by a maibox). Valid pointer locations are 1 to x (where x is the.." "0,1,2,3" line.long 0x4 "CPSW_NC_ETH_MAC_PN_INTERVLAN_OPX_A_REG_j,Enet Port N Tx Egress InterVLAN A" hexmask.long.byte 0x4 24.--31. 1. "DA_23_16,Destination Address bits 23:16" hexmask.long.byte 0x4 16.--23. 1. "DA_31_24,Destination Address bits 31:24" newline hexmask.long.byte 0x4 8.--15. 1. "DA_39_32,Destination Address bits 39:32" hexmask.long.byte 0x4 0.--7. 1. "DA_47_40,Destination Address bits 47:40" line.long 0x8 "CPSW_NC_ETH_MAC_PN_INTERVLAN_OPX_B_REG_j,Enet Port N Tx Egress InterVLAN B" hexmask.long.byte 0x8 24.--31. 1. "SA_39_32,Source Address bits 39:32" hexmask.long.byte 0x8 16.--23. 1. "SA_47_40,Source Address bits 47:40" newline hexmask.long.byte 0x8 8.--15. 1. "DA_7_0,Destination Address bits 7:0" hexmask.long.byte 0x8 0.--7. 1. "DA_15_8,Destination Address bits 15:8" line.long 0xC "CPSW_NC_ETH_MAC_PN_INTERVLAN_OPX_C_REG_j,Enet Port N Tx Egress InterVLAN C" hexmask.long.byte 0xC 24.--31. 1. "SA_7_0,Source Address bits 7:0" hexmask.long.byte 0xC 16.--23. 1. "SA_15_8,Source Address bits 15:8" newline hexmask.long.byte 0xC 8.--15. 1. "SA_23_16,Source Address bits 23:16" hexmask.long.byte 0xC 0.--7. 1. "SA_31_24,Source Address bits 31:24" line.long 0x10 "CPSW_NC_ETH_MAC_PN_INTERVLAN_OPX_D_REG_j,Enet Port N Tx Egress InterVLAN D" bitfld.long 0x10 15. "DECREMENT_TTL,Decrement Time To Live - When set the Time To Live (TTL) field in the header is decremented. IPV4 - Decrement the TTL byte and update the Header Checksum. IPV6 - Decrement the Hop Limit. note: When this bit is set the.." "0,1" bitfld.long 0x10 14. "DEST_FORCE_UNTAGGED_EGRESS,Destination VLAN Force Untagged Egress - When set this bit indicates that the VLAN should be removed on egress for the routed packet. The replace_vid bit should be set for this bit to be used otherwise force untagged egress.." "0,1" newline bitfld.long 0x10 13. "REPLACE_DA_SA,Replace Destination Address and Source Address - When set this bit indicates that the routed packet destination address should be replaced by da[47:0] and the source address should be replaced by sa[47:0]." "0,1" bitfld.long 0x10 12. "REPLACE_VID,Replace VLAN ID - When set this bit indicates that the VLAN ID should be replaced for the routed packet." "0,1" newline hexmask.long.word 0x10 0.--11. 1. "VID,VLAN ID" group.long 0x32000++0x3 line.long 0x0 "CPSW_NC_EST_FETCH_LOC,The Revision Register contains the ID and revision information." hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location" rgroup.long 0x34000++0x3 line.long 0x0 "CPSW_NC_CPDMA_REGS_FH_IDVER_REG,CPDMA FHost IDVER" hexmask.long 0x0 0.--31. 1. "FH_IDVER,CPDMA FHost IDVER" group.long 0x34004++0xB line.long 0x0 "CPSW_NC_CPDMA_REGS_FH_CONTROL_REG,CPDMA FHost Control Register" bitfld.long 0x0 0. "FH_EN,FHost Enable 0 - Disabled 1 - Enabled" "0,1" line.long 0x4 "CPSW_NC_CPDMA_REGS_FH_TEARDOWN_REG,CPDMA FHost Teardown Register" bitfld.long 0x4 0.--2. "FH_TDN_CH,CPDMA FHost Teardown Channel - FHost channel teardown is commanded by writing the encoded value of the channel to be torn down. The teardown register is read as zero. 000 - teardown channel 0 ... 111 - teardown channel 7" "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NC_CPDMA_REGS_FH_CONTROL2_REG,CPDMA FHost Control Two Register" hexmask.long.byte 0x8 0.--7. 1. "FH_EOQ_INT,FHost Interrupt on EOQ only - When set a corresponding channel issues an FH_PEND[7:0] interrupt only on end of queue (EOQ). When clear a corresponding channel issues an interrupt at every end of packet (EOP)." rgroup.long 0x34010++0x3 line.long 0x0 "CPSW_NC_CPDMA_REGS_TH_IDVER_REG,CPDMA THost IDVER" hexmask.long 0x0 0.--31. 1. "TH_IDVER,CPDMA THost IDVER" group.long 0x34014++0xF line.long 0x0 "CPSW_NC_CPDMA_REGS_TH_CONTROL_REG,CPDMA THost Control Register" bitfld.long 0x0 0. "TH_EN,THost DMA Enable 0 - Disabled 1 - Enabled" "0,1" line.long 0x4 "CPSW_NC_CPDMA_REGS_TH_TEARDOWN_REG,CPDMA THost Teardown Register" bitfld.long 0x4 0.--2. "TH_TDN_CH,THost Teardown Channel - THost channel teardown is commanded by writing the encoded value of the channel to be torn down. The teardown register is read as zero. 000 - teardown channel 0 ... 111 - teardown channel 7" "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NC_CPDMA_REGS_SOFT_RESET_REG,CPDMA Soft Reset Register" bitfld.long 0x8 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the entire CPSW logic to be reset. Software reset occurs when the DMA Controllers are in an idle state to avoid locking up the VBUSP bus. After writing a one to this bit it may be polled to.." "0,1" line.long 0xC "CPSW_NC_CPDMA_REGS_CONTROL_REG,CPDMA Control Register" bitfld.long 0xC 8. "FH_OWNERSHIP,CPDMA FHost Ownership Write Bit Value. 0 - The CPDMA writes the FHost buffer descriptor ownership bit to zero at the end of packet processing as specified in CPPI 3.0. 1 - The CPDMA writes the FHost buffer descriptor ownership bit to one.." "0,1" bitfld.long 0xC 7. "TH_CH_OVERRIDE,CPDMA THost Channel Classification Match Override Enable 0 - The THost channel is not overridden with the ALE classification match. 1 - The THOST channel is overridden with the lower 3-bits of the ALE classification match value (if a.." "0,1" newline bitfld.long 0xC 6. "TH_TS_ENCAP,CPDMA THost Packet Timestamp Encapsulation 0 - THost packets do not contain a 64-bit timestamp 1 - THost packets contain a 64-bit timestamp prepended to the packet data (32-bit lsword first)." "0,1" bitfld.long 0xC 5. "TH_VLAN_ENCAP,CPDMA THost Packet VLAN Encapsulation 0 - THost packets are not VLAN encapsulated 1 - THost packets are VLAN encapsulated" "0,1" newline bitfld.long 0xC 4. "TH_CEF,CPDMA THost Copy Error Frames Enable - Enables THost DMA overrun frames to be transferred to memory (up to the point of buffer overrun). The overrun error bit will be set in the frame EOP buffer descriptor. Overrun frame data will be filtered.." "0,1" bitfld.long 0xC 3. "CMD_IDLE,CPDMA Command Idle 0 - Idle not commanded 1 - Idle Commanded (read idle in CPDMA_Status register)" "0,1" newline bitfld.long 0xC 2. "TH_OFFLEN_BLOCK,CPDMA THost Offset/Length word write block 0 - Do not block the DMA writes to the THost buffer descriptor offset/buffer length word. The offset/buffer length word is written as specified in CPPI 3.0. 1 - Block all CPDMA DMA.." "0,1" bitfld.long 0xC 1. "TH_OWNERSHIP,CPDMA THost Ownership Write Bit Value 0 - The CPDMA writes the THost buffer descriptor ownership bit to zero at the end of packet processing as specified in CPPI 3.0. 1 - The CPDMA writes the THost buffer descriptor ownership bit to one at.." "0,1" newline bitfld.long 0xC 0. "FH_PTYPE,CPDMA FHost Queue Priority Type 0 - The queue uses a round robin scheme to select the next channel. 1 - The queue uses a fixed (channel 7 highest priority) priority scheme to select the next channel." "0,1" rgroup.long 0x34024++0x3 line.long 0x0 "CPSW_NC_CPDMA_REGS_STATUS_REG,CPDMA Status Register" bitfld.long 0x0 31. "IDLE,CPDMA Idle Status Bit - Indicates when set that the CPDMA is not transferring a packet FHost or THost." "0,1" hexmask.long.byte 0x0 20.--23. 1. "FH_HOST_ERROR_CODE,CPDMA FHost Error Code - This field is set to indicate CPDMA detected FHost DMA related host errors. The host should read this field after a HOST_ERR_INT to determine the error. Host error Interrupts require hardware reset in order.." newline bitfld.long 0x0 16.--18. "FH_ERR_CH,CPDMA FHost Error Channel - This field indicates the FHost channel that had a host error. 000 - The host error occurred on TX channel 0 ... 111 - The host error occurred on TX channel 7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 12.--15. 1. "TH_HOST_ERROR_CODE,CPDMA THost Error Code - This field is set to indicate CPDMA detected RX DMA related host errors. The host should read this field after a HOST_ERR_INT to determine the error. Host error Interrupts require hardware reset in order to.." newline bitfld.long 0x0 8.--10. "TH_ERR_CH,CPDMA THost Host Error Channel - This field indicates which THost channel had a host error. 000 - The host error occurred on THost channel 0 ... 111 - The host error occurred on RX channel 7" "0,1,2,3,4,5,6,7" group.long 0x34028++0x7 line.long 0x0 "CPSW_NC_CPDMA_REGS_TH_BUFFER_OFFSET_REG,CPDMA THost Buffer Offset Register" hexmask.long.word 0x0 0.--11. 1. "TH_BUFFER_OFFSET,CPDMA THost Buffer Offset Value - The thost_buffer_offset will be written by the port into each frame SOP buffer descriptor buffer_offset field. The frame data will begin after the thost_buffer_offset value of bytes. A value of 0x0.." line.long 0x4 "CPSW_NC_CPDMA_REGS_EMULATION_CONTROL_REG,CPDMA Emulation Control Register" bitfld.long 0x4 1. "FREE,CPDMA Free bit" "0,1" bitfld.long 0x4 0. "SOFT,CPDMA Soft bit" "0,1" rgroup.long 0x34080++0x7 line.long 0x0 "CPSW_NC_CPDMA_INT_FH_INTSTAT_RAW_REG,CPDMA FHost Interrupt Status RAW" bitfld.long 0x0 7. "FH7_PEND_RAW,CPDMA FHost Channel 7 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 6. "FH6_PEND_RAW,CPDMA FHost Channel 6 Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 5. "FH5_PEND_RAW,CPDMA FHost Channel 5 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 4. "FH4_PEND_RAW,CPDMA FHost Channel 4 Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 3. "FH3_PEND_RAW,CPDMA FHost Channel 3 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 2. "FH2_PEND_RAW,CPDMA FHost Channel 2 Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 1. "FH1_PEND_RAW,CPDMA FHost Channel 1 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 0. "FH0_PEND_RAW,CPDMA FHost Channel 0 Interrupt Pending RAW read (before mask)" "0,1" line.long 0x4 "CPSW_NC_CPDMA_INT_FH_INTSTAT_MASKED_REG,CPDMA FHost Interrupt Status MASKED" bitfld.long 0x4 7. "FH7_PEND_MASKED,CPDMA FHost Channel 7 Interrupt Pending MASKED interrupt read" "0,1" bitfld.long 0x4 6. "FH6_PEND_MASKED,CPDMA FHost Channel 6 Interrupt Pending MASKED interrupt read" "0,1" newline bitfld.long 0x4 5. "FH5_PEND_MASKED,CPDMA FHost Channel 5 Interrupt Pending MASKED interrupt read" "0,1" bitfld.long 0x4 4. "FH4_PEND_MASKED,CPDMA FHost Channel 4 Interrupt Pending MASKED interrupt read" "0,1" newline bitfld.long 0x4 3. "FH3_PEND_MASKED,CPDMA FHost Channel 3 Interrupt Pending MASKED interrupt read" "0,1" bitfld.long 0x4 2. "FH2_PEND_MASKED,CPDMA FHost Channel 2 Interrupt Pending MASKED interrupt read" "0,1" newline bitfld.long 0x4 1. "FH1_PEND_MASKED,CPDMA FHost Channel 1 Interrupt Pending MASKED interrupt read" "0,1" bitfld.long 0x4 0. "FH0_PEND_MASKED,CPDMA FHost Channel 0 Interrupt Pending MASKED interrupt read" "0,1" group.long 0x34088++0x7 line.long 0x0 "CPSW_NC_CPDMA_INT_FH_INTMASK_SET_REG,CPDMA FHost Interrupt Masked SET" bitfld.long 0x0 7. "FH7_PEND_MASKED_SET,CPDMA FHost Channel 7 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" bitfld.long 0x0 6. "FH6_PEND_MASKED_SET,CPDMA FHost Channel 6 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" newline bitfld.long 0x0 5. "FH5_PEND_MASKED_SET,CPDMA FHost Channel 5 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" bitfld.long 0x0 4. "FH4_PEND_MASKED_SET,CPDMA FHost Channel 4 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" newline bitfld.long 0x0 3. "FH3_PEND_MASKED_SET,CPDMA FHost Channel 3 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" bitfld.long 0x0 2. "FH2_PEND_MASKED_SET,CPDMA FHost Channel 2 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" newline bitfld.long 0x0 1. "FH1_PEND_MASKED_SET,CPDMA FHost Channel 1 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" bitfld.long 0x0 0. "FH0_PEND_MASKED_SET,CPDMA FHost Channel 0 Interrupt Pending MASKED Set - write one to enable interrupt" "0,1" line.long 0x4 "CPSW_NC_CPDMA_INT_FH_INTMASK_CLEAR_REG,CPDMA FHost Interrupt Masked CLR" bitfld.long 0x4 7. "FH7_PEND_MASKED_CLR,CPDMA FHost Channel 7 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" bitfld.long 0x4 6. "FH6_PEND_MASKED_CLR,CPDMA FHost Channel 6 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" newline bitfld.long 0x4 5. "FH5_PEND_MASKED_CLR,CPDMA FHost Channel 5 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" bitfld.long 0x4 4. "FH4_PEND_MASKED_CLR,CPDMA FHost Channel 4 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" newline bitfld.long 0x4 3. "FH3_PEND_MASKED_CLR,CPDMA FHost Channel 3 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" bitfld.long 0x4 2. "FH2_PEND_MASKED_CLR,CPDMA FHost Channel 2 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" newline bitfld.long 0x4 1. "FH1_PEND_MASKED_CLR,CPDMA FHost Channel 1 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" bitfld.long 0x4 0. "FH0_PEND_MASKED_CLR,CPDMA FHost Channel 0 Interrupt Pending MASKED Clr - write one to disable interrupt" "0,1" rgroup.long 0x34090++0x3 line.long 0x0 "CPSW_NC_CPDMA_INT_IN_VECTOR_REG,CPDMA DMA IN Vector" hexmask.long 0x0 0.--31. 1. "DMA_IN_VECTOR,The value of CPDMA_In_Vector is reset to zero but will change to the IN_VECTOR input bus value one clock after reset is deasserted. Thereafter this value will change to a new IN_VECTOR input value one clock after the IN_VECTOR value.." group.long 0x34094++0x3 line.long 0x0 "CPSW_NC_CPDMA_INT_EOI_VECTOR_REG,The CPDMA_EOI_VECTOR(4:0) output bus reflects the value written to this location one VBUSP_GCLK cycle after a write to this location. The EOI_WR signal is asserted for a single clock cycle after a latency of two.." hexmask.long.byte 0x0 0.--4. 1. "DMA_EOI_VECTOR,CPDMA DMA EOI Vector" rgroup.long 0x340A0++0x7 line.long 0x0 "CPSW_NC_CPDMA_INT_TH_INTSTAT_RAW_REG,CPDMA Receive Interrupt Status RAW" bitfld.long 0x0 15. "TH7_THRESH_PEND_RAW,CPDMA Receive Channel 7 Threshold Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 14. "TH6_THRESH_PEND_RAW,CPDMA Receive Channel 6 Threshold Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 13. "TH5_THRESH_PEND_RAW,CPDMA Receive Channel 5 Threshold Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 12. "TH4_THRESH_PEND_RAW,CPDMA Receive Channel 4 Threshold Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 11. "TH3_THRESH_PEND_RAW,CPDMA Receive Channel 3 Threshold Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 10. "TH2_THRESH_PEND_RAW,CPDMA Receive Channel 2 Threshold Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 9. "TH1_THRESH_PEND_RAW,CPDMA Receive Channel 1 Threshold Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 8. "TH0_THRESH_PEND_RAW,CPDMA Receive Channel 0 Threshold Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 7. "TH7_PEND_RAW,CPDMA Receive Channel 7 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 6. "TH6_PEND_RAW,CPDMA Receive Channel 6 Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 5. "TH5_PEND_RAW,CPDMA Receive Channel 5 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 4. "TH4_PEND_RAW,CPDMA Receive Channel 4 Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 3. "TH3_PEND_RAW,CPDMA Receive Channel 3 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 2. "TH2_PEND_RAW,CPDMA Receive Channel 2 Interrupt Pending RAW read (before mask)" "0,1" newline bitfld.long 0x0 1. "TH1_PEND_RAW,CPDMA Receive Channel 1 Interrupt Pending RAW read (before mask)" "0,1" bitfld.long 0x0 0. "TH0_PEND_RAW,CPDMA Receive Channel 0 Interrupt Pending RAW read (before mask)" "0,1" line.long 0x4 "CPSW_NC_CPDMA_INT_TH_INTSTAT_MASKED_REG,CPDMA Receive Interrupt Status MASKED" bitfld.long 0x4 15. "TH7_THRESH_PEND_MASKED,CPDMA Receive Channel 7 Threshold Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 14. "TH6_THRESH_PEND_MASKED,CPDMA Receive Channel 6 Threshold Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 13. "TH5_THRESH_PEND_MASKED,CPDMA Receive Channel 5 Threshold Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 12. "TH4_THRESH_PEND_MASKED,CPDMA Receive Channel 4 Threshold Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 11. "TH3_THRESH_PEND_MASKED,CPDMA Receive Channel 3 Threshold Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 10. "TH2_THRESH_PEND_MASKED,CPDMA Receive Channel 2 Threshold Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 9. "TH1_THRESH_PEND_MASKED,CPDMA Receive Channel 1 Threshold Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 8. "TH0_THRESH_PEND_MASKED,CPDMA Receive Channel 0 Threshold Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 7. "TH7_PEND_MASKED,CPDMA Receive Channel 7 Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 6. "TH6_PEND_MASKED,CPDMA Receive Channel 6 Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 5. "TH5_PEND_MASKED,CPDMA Receive Channel 5 Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 4. "TH4_PEND_MASKED,CPDMA Receive Channel 4 Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 3. "TH3_PEND_MASKED,CPDMA Receive Channel 3 Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 2. "TH2_PEND_MASKED,CPDMA Receive Channel 2 Interrupt Pending MASKED read" "0,1" newline bitfld.long 0x4 1. "TH1_PEND_MASKED,CPDMA Receive Channel 1 Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 0. "TH0_PEND_MASKED,CPDMA Receive Channel 0 Interrupt Pending MASKED read" "0,1" group.long 0x340A8++0x7 line.long 0x0 "CPSW_NC_CPDMA_INT_TH_INTMASK_SET_REG,CPDMA THost Interrupt Masked SET" bitfld.long 0x0 15. "TH7_THRESH_PEND_MASKED_SET,CPDMA THost Channel 7 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 14. "TH6_THRESH_PEND_MASKED_SET,CPDMA THost Channel 6 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 13. "TH5_THRESH_PEND_MASKED_SET,CPDMA THost Channel 5 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 12. "TH4_THRESH_PEND_MASKED_SET,CPDMA THost Channel 4 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 11. "TH3_THRESH_PEND_MASKED_SET,CPDMA THost Channel 3 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 10. "TH2_THRESH_PEND_MASKED_SET,CPDMA THost Channel 2 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 9. "TH1_THRESH_PEND_MASKED_SET,CPDMA THost Channel 1 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 8. "TH0_THRESH_PEND_MASKED_SET,CPDMA THost Channel 0 Threshold Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 7. "TH7_PEND_MASKED_SET,CPDMA THost Channel 7 Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 6. "TH6_PEND_MASKED_SET,CPDMA THost Channel 6 Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 5. "TH5_PEND_MASKED_SET,CPDMA THost Channel 5 Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 4. "TH4_PEND_MASKED_SET,CPDMA THost Channel 4 Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 3. "TH3_PEND_MASKED_SET,CPDMA THost Channel 3 Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 2. "TH2_PEND_MASKED_SET,CPDMA THost Channel 2 Interrupt Pending SET - write one to enable interrupt" "0,1" newline bitfld.long 0x0 1. "TH1_PEND_MASKED_SET,CPDMA THost Channel 1 Interrupt Pending SET - write one to enable interrupt" "0,1" bitfld.long 0x0 0. "TH0_PEND_MASKED_SET,CPDMA THost Channel 0 Interrupt Pending SET - write one to enable interrupt" "0,1" line.long 0x4 "CPSW_NC_CPDMA_INT_TH_INTMASK_CLEAR_REG,CPDMA THost Interrupt Masked CLR" bitfld.long 0x4 15. "TH7_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 7 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 14. "TH6_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 6 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 13. "TH5_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 5 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 12. "TH4_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 4 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 11. "TH3_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 3 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 10. "TH2_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 2 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 9. "TH1_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 1 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 8. "TH0_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 0 Threshold Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 7. "TH7_PEND_MASKED_CLR,CPDMA THost Channel 7 Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 6. "TH6_PEND_MASKED_CLR,CPDMA THost Channel 6 Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 5. "TH5_PEND_MASKED_CLR,CPDMA THost Channel 5 Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 4. "TH4_PEND_MASKED_CLR,CPDMA THost Channel 4 Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 3. "TH3_PEND_MASKED_CLR,CPDMA THost Channel 3 Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 2. "TH2_PEND_MASKED_CLR,CPDMA THost Channel 2 Interrupt Pending CLR - write one to disable interrupt" "0,1" newline bitfld.long 0x4 1. "TH1_PEND_MASKED_CLR,CPDMA THost Channel 1 Interrupt Pending CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 0. "TH0_PEND_MASKED_CLR,CPDMA THost Channel 0 Interrupt Pending CLR - write one to disable interrupt" "0,1" rgroup.long 0x340B0++0x7 line.long 0x0 "CPSW_NC_CPDMA_INT_INTSTAT_RAW_REG,CPDMA DMA Interrupt Status RAW" bitfld.long 0x0 1. "HOST_PEND_RAW,CPDMA HOST Interrupt Pending RAW - read (before mask)" "0,1" bitfld.long 0x0 0. "STAT_PEND_RAW,CPDMA Statistics Interrupt Pending RAW - read (before mask)" "0,1" line.long 0x4 "CPSW_NC_CPDMA_INT_INTSTAT_MASKED_REG,CPDMA DMA Interrupt Status MASKED" bitfld.long 0x4 1. "HOST_PEND,CPDMA HOST Interrupt Pending MASKED read" "0,1" bitfld.long 0x4 0. "STAT_PEND,CPDMA Statistics Interrupt Pending MASKED read" "0,1" group.long 0x340B8++0x47 line.long 0x0 "CPSW_NC_CPDMA_INT_INTMASK_SET_REG,CPDMA DMA Interrupt Status SET" bitfld.long 0x0 1. "HOST_PEND_MASKED_SET,CPDMA HOST Interrupt Masked SET - write one to enable interrupt" "0,1" bitfld.long 0x0 0. "STAT_PEND_MASKED_SET,CPDMA Statistics Interrupt Masked SET - write one to enable interrupt" "0,1" line.long 0x4 "CPSW_NC_CPDMA_INT_INTMASK_CLEAR_REG,CPDMA DMA Interrupt Status CLR" bitfld.long 0x4 1. "HOST_PEND_MASKED_CLR,CPDMA HOST Interrupt Masked CLR - write one to disable interrupt" "0,1" bitfld.long 0x4 0. "STAT_PEND_MASKED_CLR,CPDMA Statistics Interrupt Masked CLR - write one to disable interrupt" "0,1" line.long 0x8 "CPSW_NC_CPDMA_INT_TH0_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x8 0.--7. 1. "TH0_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0xC "CPSW_NC_CPDMA_INT_TH1_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0xC 0.--7. 1. "TH1_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x10 "CPSW_NC_CPDMA_INT_TH2_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x10 0.--7. 1. "TH2_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x14 "CPSW_NC_CPDMA_INT_TH3_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x14 0.--7. 1. "TH3_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x18 "CPSW_NC_CPDMA_INT_TH4_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x18 0.--7. 1. "TH4_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x1C "CPSW_NC_CPDMA_INT_TH5_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x1C 0.--7. 1. "TH5_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x20 "CPSW_NC_CPDMA_INT_TH6_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x20 0.--7. 1. "TH6_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x24 "CPSW_NC_CPDMA_INT_TH7_PENDTHRESH_REG,CPDMA THost Threshold Pending Register" hexmask.long.byte 0x24 0.--7. 1. "TH7_PENDTHRESH,This field contains the threshold value for issuing threshold pending interrupts (when enabled)" line.long 0x28 "CPSW_NC_CPDMA_INT_TH0_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x28 0.--15. 1. "TH0_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x2C "CPSW_NC_CPDMA_INT_TH1_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x2C 0.--15. 1. "TH1_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x30 "CPSW_NC_CPDMA_INT_TH2_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x30 0.--15. 1. "TH2_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x34 "CPSW_NC_CPDMA_INT_TH3_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x34 0.--15. 1. "TH3_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x38 "CPSW_NC_CPDMA_INT_TH4_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x38 0.--15. 1. "TH4_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x3C "CPSW_NC_CPDMA_INT_TH5_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x3C 0.--15. 1. "TH5_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x40 "CPSW_NC_CPDMA_INT_TH6_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x40 0.--15. 1. "TH6_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." line.long 0x44 "CPSW_NC_CPDMA_INT_TH7_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register" hexmask.long.word 0x44 0.--15. 1. "TH7_FREEBUFFER,This field contains the count of host free buffers available. The th(0..7)_pendthresh value is compared with this field to determine if the THost threshold pending interrupt should be asseted (if enabled). This is a write to increment.." group.long 0x34200++0x7F line.long 0x0 "CPSW_NC_CPDMA_SRAM_FH0_HDP_REG,CPDMA FHost Channel 0 Head Descriptor Pointer" hexmask.long 0x0 0.--31. 1. "FH0_HDP,CPDMA FHost Channel 0 Head Descriptor Pointer" line.long 0x4 "CPSW_NC_CPDMA_SRAM_FH1_HDP_REG,CPDMA FHost Channel 1 Head Descriptor Pointer" hexmask.long 0x4 0.--31. 1. "FH1_HDP,CPDMA FHost Channel 1 Head Descriptor Pointer" line.long 0x8 "CPSW_NC_CPDMA_SRAM_FH2_HDP_REG,CPDMA FHost Channel 2 Head Descriptor Pointer" hexmask.long 0x8 0.--31. 1. "FH2_HDP,CPDMA FHost Channel 2 Head Descriptor Pointer" line.long 0xC "CPSW_NC_CPDMA_SRAM_FH3_HDP_REG,CPDMA FHost Channel 3 Head Descriptor Pointer" hexmask.long 0xC 0.--31. 1. "FH3_HDP,CPDMA FHost Channel 3 Head Descriptor Pointer" line.long 0x10 "CPSW_NC_CPDMA_SRAM_FH4_HDP_REG,CPDMA FHost Channel 4 Head Descriptor Pointer" hexmask.long 0x10 0.--31. 1. "FH4_HDP,CPDMA FHost Channel 4 Head Descriptor Pointer" line.long 0x14 "CPSW_NC_CPDMA_SRAM_FH5_HDP_REG,CPDMA FHost Channel 5 Head Descriptor Pointer" hexmask.long 0x14 0.--31. 1. "FH5_HDP,CPDMA FHost Channel 5 Head Descriptor Pointer" line.long 0x18 "CPSW_NC_CPDMA_SRAM_FH6_HDP_REG,CPDMA FHost Channel 6 Head Descriptor Pointer" hexmask.long 0x18 0.--31. 1. "FH6_HDP,CPDMA FHost Channel 6 Head Descriptor Pointer" line.long 0x1C "CPSW_NC_CPDMA_SRAM_FH7_HDP_REG,CPDMA FHost Channel 7 Head Descriptor Pointer" hexmask.long 0x1C 0.--31. 1. "FH7_HDP,CPDMA FHost Channel 7 Head Descriptor Pointer" line.long 0x20 "CPSW_NC_CPDMA_SRAM_TH0_HDP_REG,CPDMA THost Channel 0 Head Descriptor Pointer" hexmask.long 0x20 0.--31. 1. "TH0_HDP,CPDMA THost Channel 0 Head Descriptor Pointer" line.long 0x24 "CPSW_NC_CPDMA_SRAM_TH1_HDP_REG,CPDMA THost Channel 1 Head Descriptor Pointer" hexmask.long 0x24 0.--31. 1. "TH1_HDP,CPDMA THost Channel 1 Head Descriptor Pointer" line.long 0x28 "CPSW_NC_CPDMA_SRAM_TH2_HDP_REG,CPDMA THost Channel 2 Head Descriptor Pointer" hexmask.long 0x28 0.--31. 1. "TH2_HDP,CPDMA THost Channel 2 Head Descriptor Pointer" line.long 0x2C "CPSW_NC_CPDMA_SRAM_TH3_HDP_REG,CPDMA THost Channel 3 Head Descriptor Pointer" hexmask.long 0x2C 0.--31. 1. "TH3_HDP,CPDMA THost Channel 3 Head Descriptor Pointer" line.long 0x30 "CPSW_NC_CPDMA_SRAM_TH4_HDP_REG,CPDMA THost Channel 4 Head Descriptor Pointer" hexmask.long 0x30 0.--31. 1. "TH4_HDP,CPDMA THost Channel 4 Head Descriptor Pointer" line.long 0x34 "CPSW_NC_CPDMA_SRAM_TH5_HDP_REG,CPDMA THost Channel 5 Head Descriptor Pointer" hexmask.long 0x34 0.--31. 1. "TH5_HDP,CPDMA THost Channel 5 Head Descriptor Pointer" line.long 0x38 "CPSW_NC_CPDMA_SRAM_TH6_HDP_REG,CPDMA THost Channel 6 Head Descriptor Pointer" hexmask.long 0x38 0.--31. 1. "TH6_HDP,CPDMA THost Channel 6 Head Descriptor Pointer" line.long 0x3C "CPSW_NC_CPDMA_SRAM_TH7_HDP_REG,CPDMA THost Channel 7 Head Descriptor Pointer" hexmask.long 0x3C 0.--31. 1. "TH7_HDP,CPDMA THost Channel 7 Head Descriptor Pointer" line.long 0x40 "CPSW_NC_CPDMA_SRAM_FH0_CP_REG,CPDMA FHost Channel 0 Completion Pointer" hexmask.long 0x40 0.--31. 1. "FH0_CP,CPDMA FHost Channel 0 Completion Pointer" line.long 0x44 "CPSW_NC_CPDMA_SRAM_FH1_CP_REG,CPDMA FHost Channel 1 Completion Pointer" hexmask.long 0x44 0.--31. 1. "FH1_CP,CPDMA FHost Channel 1 Completion Pointer" line.long 0x48 "CPSW_NC_CPDMA_SRAM_FH2_CP_REG,CPDMA FHost Channel 2 Completion Pointer" hexmask.long 0x48 0.--31. 1. "FH2_CP,CPDMA FHost Channel 2 Completion Pointer" line.long 0x4C "CPSW_NC_CPDMA_SRAM_FH3_CP_REG,CPDMA FHost Channel 3 Completion Pointer" hexmask.long 0x4C 0.--31. 1. "FH3_CP,CPDMA FHost Channel 3 Completion Pointer" line.long 0x50 "CPSW_NC_CPDMA_SRAM_FH4_CP_REG,CPDMA FHost Channel 4 Completion Pointer" hexmask.long 0x50 0.--31. 1. "FH4_CP,CPDMA FHost Channel 4 Completion Pointer" line.long 0x54 "CPSW_NC_CPDMA_SRAM_FH5_CP_REG,CPDMA FHost Channel 5 Completion Pointer" hexmask.long 0x54 0.--31. 1. "FH5_CP,CPDMA FHost Channel 5 Completion Pointer" line.long 0x58 "CPSW_NC_CPDMA_SRAM_FH6_CP_REG,CPDMA FHost Channel 6 Completion Pointer" hexmask.long 0x58 0.--31. 1. "FH6_CP,CPDMA FHost Channel 6 Completion Pointer" line.long 0x5C "CPSW_NC_CPDMA_SRAM_FH7_CP_REG,CPDMA FHost Channel 7 Completion Pointer" hexmask.long 0x5C 0.--31. 1. "FH7_CP,CPDMA FHost Channel 7 Completion Pointer" line.long 0x60 "CPSW_NC_CPDMA_SRAM_TH0_CP_REG,CPDMA THost Channel 0 Completion Pointer" hexmask.long 0x60 0.--31. 1. "TH0_CP,CPDMA THost Channel 0 Completion Pointer" line.long 0x64 "CPSW_NC_CPDMA_SRAM_TH1_CP_REG,CPDMA THost Channel 1 Completion Pointer" hexmask.long 0x64 0.--31. 1. "TH1_CP,CPDMA THost Channel 1 Completion Pointer" line.long 0x68 "CPSW_NC_CPDMA_SRAM_TH2_CP_REG,CPDMA THost Channel 2 Completion Pointer" hexmask.long 0x68 0.--31. 1. "TH2_CP,CPDMA THost Channel 2 Completion Pointer" line.long 0x6C "CPSW_NC_CPDMA_SRAM_TH3_CP_REG,CPDMA THost Channel 3 Completion Pointer" hexmask.long 0x6C 0.--31. 1. "TH3_CP,CPDMA THost Channel 3 Completion Pointer" line.long 0x70 "CPSW_NC_CPDMA_SRAM_TH4_CP_REG,CPDMA THost Channel 4 Completion Pointer" hexmask.long 0x70 0.--31. 1. "TH4_CP,CPDMA THost Channel 4 Completion Pointer" line.long 0x74 "CPSW_NC_CPDMA_SRAM_TH5_CP_REG,CPDMA THost Channel 5 Completion Pointer" hexmask.long 0x74 0.--31. 1. "TH5_CP,CPDMA THost Channel 5 Completion Pointer" line.long 0x78 "CPSW_NC_CPDMA_SRAM_TH6_CP_REG,CPDMA THost Channel 6 Completion Pointer" hexmask.long 0x78 0.--31. 1. "TH6_CP,CPDMA THost Channel 6 Completion Pointer" line.long 0x7C "CPSW_NC_CPDMA_SRAM_TH7_CP_REG,CPDMA THost Channel 7 Completion Pointer" hexmask.long 0x7C 0.--31. 1. "TH7_CP,CPDMA THost Channel 7 Completion Pointer" group.long 0x34300++0x7F line.long 0x0 "CPSW_NC_CPDMA_SRAM_TEST_FH0_HDP_REG,Test CPDMA FHost Channel 0 Head Descriptor Pointer" hexmask.long 0x0 0.--31. 1. "TEST_FH0_HDP,Test CPDMA FHost Channel 0 Head Descriptor Pointer" line.long 0x4 "CPSW_NC_CPDMA_SRAM_TEST_FH1_HDP_REG,Test CPDMA FHost Channel 1 Head Descriptor Pointer" hexmask.long 0x4 0.--31. 1. "TEST_FH1_HDP,Test CPDMA FHost Channel 1 Head Descriptor Pointer" line.long 0x8 "CPSW_NC_CPDMA_SRAM_TEST_FH2_HDP_REG,Test CPDMA FHost Channel 2 Head Descriptor Pointer" hexmask.long 0x8 0.--31. 1. "TEST_FH2_HDP,Test CPDMA FHost Channel 2 Head Descriptor Pointer" line.long 0xC "CPSW_NC_CPDMA_SRAM_TEST_FH3_HDP_REG,Test CPDMA FHost Channel 3 Head Descriptor Pointer" hexmask.long 0xC 0.--31. 1. "TEST_FH3_HDP,Test CPDMA FHost Channel 3 Head Descriptor Pointer" line.long 0x10 "CPSW_NC_CPDMA_SRAM_TEST_FH4_HDP_REG,Test CPDMA FHost Channel 4 Head Descriptor Pointer" hexmask.long 0x10 0.--31. 1. "TEST_FH4_HDP,Test CPDMA FHost Channel 4 Head Descriptor Pointer" line.long 0x14 "CPSW_NC_CPDMA_SRAM_TEST_FH5_HDP_REG,Test CPDMA FHost Channel 5 Head Descriptor Pointer" hexmask.long 0x14 0.--31. 1. "TEST_FH5_HDP,Test CPDMA FHost Channel 5 Head Descriptor Pointer" line.long 0x18 "CPSW_NC_CPDMA_SRAM_TEST_FH6_HDP_REG,Test CPDMA FHost Channel 6 Head Descriptor Pointer" hexmask.long 0x18 0.--31. 1. "TEST_FH6_HDP,Test CPDMA FHost Channel 6 Head Descriptor Pointer" line.long 0x1C "CPSW_NC_CPDMA_SRAM_TEST_FH7_HDP_REG,Test CPDMA FHost Channel 7 Head Descriptor Pointer" hexmask.long 0x1C 0.--31. 1. "TEST_FH7_HDP,Test CPDMA FHost Channel 7 Head Descriptor Pointer" line.long 0x20 "CPSW_NC_CPDMA_SRAM_TEST_TH0_HDP_REG,Test CPDMA THost Channel 0 Head Descriptor Pointer" hexmask.long 0x20 0.--31. 1. "TEST_TH0_HDP,Test CPDMA THost Channel 0 Head Descriptor Pointer" line.long 0x24 "CPSW_NC_CPDMA_SRAM_TEST_TH1_HDP_REG,Test CPDMA THost Channel 1 Head Descriptor Pointer" hexmask.long 0x24 0.--31. 1. "TEST_TH1_HDP,Test CPDMA THost Channel 1 Head Descriptor Pointer" line.long 0x28 "CPSW_NC_CPDMA_SRAM_TEST_TH2_HDP_REG,Test CPDMA THost Channel 2 Head Descriptor Pointer" hexmask.long 0x28 0.--31. 1. "TEST_TH2_HDP,Test CPDMA THost Channel 2 Head Descriptor Pointer" line.long 0x2C "CPSW_NC_CPDMA_SRAM_TEST_TH3_HDP_REG,Test CPDMA THost Channel 3 Head Descriptor Pointer" hexmask.long 0x2C 0.--31. 1. "TEST_TH3_HDP,Test CPDMA THost Channel 3 Head Descriptor Pointer" line.long 0x30 "CPSW_NC_CPDMA_SRAM_TEST_TH4_HDP_REG,Test CPDMA THost Channel 4 Head Descriptor Pointer" hexmask.long 0x30 0.--31. 1. "TEST_TH4_HDP,Test CPDMA THost Channel 4 Head Descriptor Pointer" line.long 0x34 "CPSW_NC_CPDMA_SRAM_TEST_TH5_HDP_REG,Test CPDMA THost Channel 5 Head Descriptor Pointer" hexmask.long 0x34 0.--31. 1. "TEST_TH5_HDP,Test CPDMA THost Channel 5 Head Descriptor Pointer" line.long 0x38 "CPSW_NC_CPDMA_SRAM_TEST_TH6_HDP_REG,Test CPDMA THost Channel 6 Head Descriptor Pointer" hexmask.long 0x38 0.--31. 1. "TEST_TH6_HDP,Test CPDMA THost Channel 6 Head Descriptor Pointer" line.long 0x3C "CPSW_NC_CPDMA_SRAM_TEST_TH7_HDP_REG,Test CPDMA THost Channel 7 Head Descriptor Pointer" hexmask.long 0x3C 0.--31. 1. "TEST_TH7_HDP,Test CPDMA THost Channel 7 Head Descriptor Pointer" line.long 0x40 "CPSW_NC_CPDMA_SRAM_TEST_FH0_CP_REG,Test CPDMA FHost Channel 0 Completion Pointer" hexmask.long 0x40 0.--31. 1. "TEST_FH0_CP,Test CPDMA FHost Channel 0 Completion Pointer" line.long 0x44 "CPSW_NC_CPDMA_SRAM_TEST_FH1_CP_REG,Test CPDMA FHost Channel 1 Completion Pointer" hexmask.long 0x44 0.--31. 1. "TEST_FH1_CP,Test CPDMA FHost Channel 1 Completion Pointer" line.long 0x48 "CPSW_NC_CPDMA_SRAM_TEST_FH2_CP_REG,Test CPDMA FHost Channel 2 Completion Pointer" hexmask.long 0x48 0.--31. 1. "TEST_FH2_CP,Test CPDMA FHost Channel 2 Completion Pointer" line.long 0x4C "CPSW_NC_CPDMA_SRAM_TEST_FH3_CP_REG,Test CPDMA FHost Channel 3 Completion Pointer" hexmask.long 0x4C 0.--31. 1. "TEST_FH3_CP,Test CPDMA FHost Channel 3 Completion Pointer" line.long 0x50 "CPSW_NC_CPDMA_SRAM_TEST_FH4_CP_REG,Test CPDMA FHost Channel 4 Completion Pointer" hexmask.long 0x50 0.--31. 1. "TEST_FH4_CP,Test CPDMA FHost Channel 4 Completion Pointer" line.long 0x54 "CPSW_NC_CPDMA_SRAM_TEST_FH5_CP_REG,Test CPDMA FHost Channel 5 Completion Pointer" hexmask.long 0x54 0.--31. 1. "TEST_FH5_CP,Test CPDMA FHost Channel 5 Completion Pointer" line.long 0x58 "CPSW_NC_CPDMA_SRAM_TEST_FH6_CP_REG,Test CPDMA FHost Channel 6 Completion Pointer" hexmask.long 0x58 0.--31. 1. "TEST_FH6_CP,Test CPDMA FHost Channel 6 Completion Pointer" line.long 0x5C "CPSW_NC_CPDMA_SRAM_TEST_FH7_CP_REG,Test CPDMA FHost Channel 7 Completion Pointer" hexmask.long 0x5C 0.--31. 1. "TEST_FH7_CP,Test CPDMA FHost Channel 7 Completion Pointer" line.long 0x60 "CPSW_NC_CPDMA_SRAM_TEST_TH0_CP_REG,Test CPDMA THost Channel 0 Completion Pointer" hexmask.long 0x60 0.--31. 1. "TEST_TH0_CP,Test CPDMA THost Channel 0 Completion Pointer" line.long 0x64 "CPSW_NC_CPDMA_SRAM_TEST_TH1_CP_REG,Test CPDMA THost Channel 1 Completion Pointer" hexmask.long 0x64 0.--31. 1. "TEST_TH1_CP,Test CPDMA THost Channel 1 Completion Pointer" line.long 0x68 "CPSW_NC_CPDMA_SRAM_TEST_TH2_CP_REG,Test CPDMA THost Channel 2 Completion Pointer" hexmask.long 0x68 0.--31. 1. "TEST_TH2_CP,Test CPDMA THost Channel 2 Completion Pointer" line.long 0x6C "CPSW_NC_CPDMA_SRAM_TEST_TH3_CP_REG,Test CPDMA THost Channel 3 Completion Pointer" hexmask.long 0x6C 0.--31. 1. "TEST_TH3_CP,Test CPDMA THost Channel 3 Completion Pointer" line.long 0x70 "CPSW_NC_CPDMA_SRAM_TEST_TH4_CP_REG,Test CPDMA THost Channel 4 Completion Pointer" hexmask.long 0x70 0.--31. 1. "TEST_TH4_CP,Test CPDMA THost Channel 4 Completion Pointer" line.long 0x74 "CPSW_NC_CPDMA_SRAM_TEST_TH5_CP_REG,Test CPDMA THost Channel 5 Completion Pointer" hexmask.long 0x74 0.--31. 1. "TEST_TH5_CP,Test CPDMA THost Channel 5 Completion Pointer" line.long 0x78 "CPSW_NC_CPDMA_SRAM_TEST_TH6_CP_REG,Test CPDMA THost Channel 6 Completion Pointer" hexmask.long 0x78 0.--31. 1. "TEST_TH6_CP,Test CPDMA THost Channel 6 Completion Pointer" line.long 0x7C "CPSW_NC_CPDMA_SRAM_TEST_TH7_CP_REG,Test CPDMA THost Channel 7 Completion Pointer" hexmask.long 0x7C 0.--31. 1. "TEST_TH7_CP,Test CPDMA THost Channel 7 Completion Pointer" group.long 0x3A000++0xDF line.long 0x0 "CPSW_NC_STAT_RXGOODFRAMES_j,Total number of good frames received" hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received" line.long 0x4 "CPSW_NC_STAT_RXBROADCASTFRAMES_j,Total number of good broadcast frames received" hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received" line.long 0x8 "CPSW_NC_STAT_RXMULTICASTFRAMES_j,Total number of good multicast frames received" hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received" line.long 0xC "CPSW_NC_STAT_RXPAUSEFRAMES_j,Total number of pause frames received" hexmask.long 0xC 0.--31. 1. "COUNT,Total number of pause frames received" line.long 0x10 "CPSW_NC_STAT_RXCRCERRORS_j,Total number of CRC errors frames received" hexmask.long 0x10 0.--31. 1. "COUNT,Total number of CRC errors frames received" line.long 0x14 "CPSW_NC_STAT_RXALIGNCODEERRORS_j,Total number of alignment/code errors received" hexmask.long 0x14 0.--31. 1. "COUNT,Total number of alignment/code errors received" line.long 0x18 "CPSW_NC_STAT_RXOVERSIZEDFRAMES_j,Total number of oversized frames received" hexmask.long 0x18 0.--31. 1. "COUNT,Total number of oversized frames received" line.long 0x1C "CPSW_NC_STAT_RXJABBERFRAMES_j,Total number of jabber frames received" hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of jabber frames received" line.long 0x20 "CPSW_NC_STAT_RXUNDERSIZEDFRAMES_j,Total number of undersized frames received" hexmask.long 0x20 0.--31. 1. "COUNT,Total number of undersized frames received" line.long 0x24 "CPSW_NC_STAT_RXFRAGMENTS_j,Total number of fragmented frames received" hexmask.long 0x24 0.--31. 1. "COUNT,Total number of fragmented frames received" line.long 0x28 "CPSW_NC_STAT_ALE_DROP_j,Total number of frames dropped by the ALE" hexmask.long 0x28 0.--31. 1. "COUNT,Total number of frames dropped by the ALE" line.long 0x2C "CPSW_NC_STAT_ALE_OVERRUN_DROP_j,Total number of overrun frames dropped by the ALE" hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE" line.long 0x30 "CPSW_NC_STAT_RXOCTETS_j,Total number of received bytes in good frames" hexmask.long 0x30 0.--31. 1. "COUNT,Total number of received bytes in good frames" line.long 0x34 "CPSW_NC_STAT_TXGOODFRAMES_j,Total number of good frames transmitted" hexmask.long 0x34 0.--31. 1. "COUNT,Total number of good frames transmitted" line.long 0x38 "CPSW_NC_STAT_TXBROADCASTFRAMES_j,Total number of good broadcast frames transmitted" hexmask.long 0x38 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted" line.long 0x3C "CPSW_NC_STAT_TXMULTICASTFRAMES_j,Total number of good multicast frames transmitted" hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted" line.long 0x40 "CPSW_NC_STAT_TXPAUSEFRAMES_j,Total number of pause frames transmitted" hexmask.long 0x40 0.--31. 1. "COUNT,Total number of pause frames transmitted" line.long 0x44 "CPSW_NC_STAT_TXDEFERREDFRAMES_j,Total number of deferred frames transmitted" hexmask.long 0x44 0.--31. 1. "COUNT,Total number of deferred frames transmitted" line.long 0x48 "CPSW_NC_STAT_TXCOLLISIONFRAMES_j,Total number of transmitted frames experiencing a collision" hexmask.long 0x48 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a collision" line.long 0x4C "CPSW_NC_STAT_TXSINGLECOLLFRAMES_j,Total number of transmitted frames experiencing a single collision" hexmask.long 0x4C 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a single collision" line.long 0x50 "CPSW_NC_STAT_TXMULTCOLLFRAMES_j,Total number of transmitted frames experiencing multiple collisions" hexmask.long 0x50 0.--31. 1. "COUNT,Total number of transmitted frames experiencing multiple collisions" line.long 0x54 "CPSW_NC_STAT_TXEXCESSIVECOLLISIONS_j,Total number of transmitted frames abandoned due to excessive collisions" hexmask.long 0x54 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to excessive collisions" line.long 0x58 "CPSW_NC_STAT_TXLATECOLLISIONS_j,Total number of transmitted frames abandoned due to a late collision" hexmask.long 0x58 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to a late collision" line.long 0x5C "CPSW_NC_STAT_RXIPGERROR_j,Total number of receive inter-packet gap errors (10G only)" hexmask.long 0x5C 0.--31. 1. "COUNT,Total number of receive inter-packet gap errors (10G only)" line.long 0x60 "CPSW_NC_STAT_TXCARRIERSENSEERRORS_j,Total number of transmitted frames that experienced a carrier loss" hexmask.long 0x60 0.--31. 1. "COUNT,Total number of transmitted frames that experienced a carrier loss" line.long 0x64 "CPSW_NC_STAT_TXOCTETS_j,Total number of bytes in all good frames transmitted" hexmask.long 0x64 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted" line.long 0x68 "CPSW_NC_STAT_OCTETFRAMES64_j,Total number of 64-byte frames received and transmitted" hexmask.long 0x68 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted" line.long 0x6C "CPSW_NC_STAT_OCTETFRAMES65T127_j,Total number of frames of size 65 to 127 bytes received and transmitted" hexmask.long 0x6C 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted" line.long 0x70 "CPSW_NC_STAT_OCTETFRAMES128T255_j,Total number of frames of size 128 to 255 bytes received and transmitted" hexmask.long 0x70 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted" line.long 0x74 "CPSW_NC_STAT_OCTETFRAMES256T511_j,Total number of frames of size 256 to 511 bytes received and transmitted" hexmask.long 0x74 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted" line.long 0x78 "CPSW_NC_STAT_OCTETFRAMES512T1023_j,Total number of frames of size 512 to 1023 bytes received and transmitted" hexmask.long 0x78 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted" line.long 0x7C "CPSW_NC_STAT_OCTETFRAMES1024TUP_j,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" hexmask.long 0x7C 0.--31. 1. "COUNT,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" line.long 0x80 "CPSW_NC_STAT_NETOCTETS_j,Total number of bytes received and transmitted" hexmask.long 0x80 0.--31. 1. "COUNT,Total number of bytes received and transmitted" line.long 0x84 "CPSW_NC_STAT_RX_BOTTOM_OF_FIFO_DROP_j,Receive Bottom of FIFO Drop" hexmask.long 0x84 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop" line.long 0x88 "CPSW_NC_STAT_PORTMASK_DROP_j,Total number of dropped frames received due to portmask" hexmask.long 0x88 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask" line.long 0x8C "CPSW_NC_STAT_RX_TOP_OF_FIFO_DROP_j,Receive Top of FIFO Drop" hexmask.long 0x8C 0.--31. 1. "COUNT,Receive Top of FIFO Drop" line.long 0x90 "CPSW_NC_STAT_ALE_RATE_LIMIT_DROP_j,Total number of dropped frames due to ALE Rate Limiting" hexmask.long 0x90 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting" line.long 0x94 "CPSW_NC_STAT_ALE_VID_INGRESS_DROP_j,Total number of dropped frames due to ALE VID Ingress" hexmask.long 0x94 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress" line.long 0x98 "CPSW_NC_STAT_ALE_DA_EQ_SA_DROP_j,Total number of dropped frames due to DA=SA" hexmask.long 0x98 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA" line.long 0x9C "CPSW_NC_STAT_ALE_BLOCK_DROP_j,Total number of dropped frames due to ALE Block Mode" hexmask.long 0x9C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode" line.long 0xA0 "CPSW_NC_STAT_ALE_SECURE_DROP_j,Total number of dropped frames due to ALE Secure Mode" hexmask.long 0xA0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode" line.long 0xA4 "CPSW_NC_STAT_ALE_AUTH_DROP_j,Total number of dropped frames due to ALE Authentication" hexmask.long 0xA4 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication" line.long 0xA8 "CPSW_NC_STAT_ALE_UNKN_UNI_j,ALE Receive Unknown Unicast" hexmask.long 0xA8 0.--31. 1. "COUNT,ALE Receive Unknown Unicast" line.long 0xAC "CPSW_NC_STAT_ALE_UNKN_UNI_BCNT_j,ALE Receive Unknown Unicast Bytecount" hexmask.long 0xAC 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount" line.long 0xB0 "CPSW_NC_STAT_ALE_UNKN_MLT_j,ALE Receive Unknown Multicast" hexmask.long 0xB0 0.--31. 1. "COUNT,ALE Receive Unknown Multicast" line.long 0xB4 "CPSW_NC_STAT_ALE_UNKN_MLT_BCNT_j,ALE Receive Unknown Multicast Bytecount" hexmask.long 0xB4 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount" line.long 0xB8 "CPSW_NC_STAT_ALE_UNKN_BRD_j,ALE Receive Unknown Broadcast" hexmask.long 0xB8 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast" line.long 0xBC "CPSW_NC_STAT_ALE_UNKN_BRD_BCNT_j,ALE Receive Unknown Broadcast Bytecount" hexmask.long 0xBC 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount" line.long 0xC0 "CPSW_NC_STAT_ALE_POL_MATCH_j,ALE Policer Matched" hexmask.long 0xC0 0.--31. 1. "COUNT,ALE Policer Matched" line.long 0xC4 "CPSW_NC_STAT_ALE_POL_MATCH_RED_j,ALE Policer Matched and Condition Red" hexmask.long 0xC4 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red" line.long 0xC8 "CPSW_NC_STAT_ALE_POL_MATCH_YELLOW_j,ALE Policer Matched and Condition Yellow" hexmask.long 0xC8 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow" line.long 0xCC "CPSW_NC_STAT_ALE_MULT_SA_DROP_j,ALE Multicast Source Address Drop" hexmask.long 0xCC 0.--31. 1. "COUNT,ALE Multicast Source Address drop" line.long 0xD0 "CPSW_NC_STAT_ALE_DUAL_VLAN_DROP_j,ALE Dual VLAN Drop" hexmask.long 0xD0 0.--31. 1. "COUNT,ALE Dual VLAN drop" line.long 0xD4 "CPSW_NC_STAT_ALE_LEN_ERROR_DROP_j,ALE Length Error Drop" hexmask.long 0xD4 0.--31. 1. "COUNT,ALE Length Error drop" line.long 0xD8 "CPSW_NC_STAT_ALE_IP_NEXT_HDR_DROP_j,ALE IP Next Header Drop" hexmask.long 0xD8 0.--31. 1. "COUNT,ALE Next Header drop" line.long 0xDC "CPSW_NC_STAT_ALE_IPV4_FRAG_DROP_j,ALE IPV4 Frag Drop" hexmask.long 0xDC 0.--31. 1. "COUNT,ALE IPV4 Fragment drop" group.long 0x3A17C++0x7 line.long 0x0 "CPSW_NC_STAT_TX_MEMORY_PROTECT_ERROR_j,Transmit Memory Protect CRC Error" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error" line.long 0x4 "CPSW_NC_STAT_ENET_PN_TX_PRI_REG_j_k,ENET Port n PRIORITY N Packet Count" hexmask.long 0x4 0.--31. 1. "PN_TX_PRIN,ENET TX Priority Packet Count" group.long 0x3A1A0++0x3 line.long 0x0 "CPSW_NC_STAT_ENET_PN_TX_PRI_BCNT_REG_j_k,ENET Port n PRIORITY N Packet Byte Count" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_BCNT,ENET Port n PRIORITY N Packet Byte Count" group.long 0x3A1C0++0x3 line.long 0x0 "CPSW_NC_STAT_ENET_PN_TX_PRI_DROP_REG_j_k,ENET Port n PRIORITY N Packet Drop Count" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP,ENET Port n PRIORITY N Packet Drop Count" group.long 0x3A1E0++0x3 line.long 0x0 "CPSW_NC_STAT_ENET_PN_TX_PRI_DROP_BCNT_REG_j_k,ENET Port n PRIORITY N Packet Drop Byte Count" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP_BCNT,ENET Port n PRIORITY N Packet Drop Byte Count" rgroup.long 0x3D000++0x3 line.long 0x0 "CPSW_NC_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x3D004++0x7 line.long 0x0 "CPSW_NC_CPTS_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select - 0000 - TS_SYNC disabled. 0001 - TS_SYNC is timestamp counter bit 17 0010 - TS_SYNC is timestamp counter bit 18 ... 1110 - TS_SYNC is timestamp counter bit 30 1111 - TS_SYNC is.." bitfld.long 0x0 17. "TS_GENF_CLR_EN,GENF (and ESTF) Clear Enable - 0 - A TS_GENFn output is not cleared when the associated ts_genf_length[31:0] is cleared to zero. 1 - A TS_GENFn output is cleared when the associated ts_genf_length[31:0] is cleared to zero." "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events - 0 - Ethernet receive timesync events enabled. 1 - Ethernet receive timesync events disabled." "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" newline bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" newline bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" newline bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x0 7. "TS_PPM_DIR,PPM Correction Direction - 0 - Increase the time_stamp[63:0] value by the PPM value. 1 - Decrease the time_stamp[63:0] value by the PPM value." "0,1" newline bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode - 0 - TS_COMP is in non-toggle mode. 1 - TS_COMP is in toggle mode." "0,1" bitfld.long 0x0 5. "MODE,64-Bit Mode - 0 - The timestamp is 32-bits with the upper 32-bits forced to zero. 1 - The timestamp is 64-bits." "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable - 0 - The timestamp value increments with the selected RFTCLK (normal operation). 1 - The timestamp for received packets is the sequence number of the received packet (first packet is 1 second packet is 2 etc). This can.." "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable - 0 - Timestamps are disabled on received packets to host. 1 - Timestamps enabled on received packets to host (cpts_en must be set)." "0,1" newline bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP Polarity 0 - TS_COMP is asserted low 1 - TS_COMP is asserted high" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt Test - When set this bit allows the raw interrupt to be written to facilitate interrupt test." "0,1" newline bitfld.long 0x0 0. "CPTS_EN,Time Sync Enable - When disabled (cleared to zero) the CPTS RCLK domain is held in reset." "0,1" line.long 0x4 "CPSW_NC_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference Clock Select - This signal is used to control an external multiplexor that selects one of up to 32 clocks for time sync reference (RFTCLK). This rftclk_sel value can be written only when the cpts_en bit and the tstamp_en bit are.." wgroup.long 0x3D00C++0x3 line.long 0x0 "CPSW_NC_CPTS_TS_PUSH_REG,Time Stamp Event Push Register" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO. The time stamp value is the time of the write of this register not the time of the event read. The time stamp value can then be.." "0,1" group.long 0x3D010++0x3 line.long 0x0 "CPSW_NC_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time Stamp Load Low Value - Writing the ts_load_en bit causes ts_load[63:0] to be written into the time stamp. The time stamp value is read by initiating a time stamp push event not by reading this register. When reading this register the.." wgroup.long 0x3D014++0x3 line.long 0x0 "CPSW_NC_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register" bitfld.long 0x0 0. "TS_LOAD_EN,Time Stamp Load - Writing a one to this bit enables the time stamp value to be written with the value in ts_load[63:0]. This bit is write only and will be cleared by the hardware after one clock. The upper 32-bits of the timestamp are forced.." "0,1" group.long 0x3D018++0xB line.long 0x0 "CPSW_NC_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time Stamp Comparison Low Value - Writing a non-zero value to the TS_Comp_Length[31:0] register causes a pulse of TS_Comp_Length RCLK periods on the TS_COMP output and a comparison event when the time_stamp counter value is equivalent to.." line.long 0x4 "CPSW_NC_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time Stamp Comparison Length - Writing a non-zero value to this field enables the time stamp comparison event and output. This value should be zero when the TS_Comp_Low and TS_Comp_High registers are written." line.long 0x8 "CPSW_NC_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable). Writable when int_test = 1 A one in this bit indicates that there are one or more events in the event FIFO." "0,1" rgroup.long 0x3D024++0x3 line.long 0x0 "CPSW_NC_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" group.long 0x3D028++0x7 line.long 0x0 "CPSW_NC_CPTS_INT_ENABLE_REG,Interrupt Enable Register" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "CPSW_NC_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,Timestamp Comparison Nudge Value - This two's complement number is added to the ts_comp_length[31:0] value to increase or decrease the TS_COMP length by the ts_comp_nudge amount. Only a single high or low time is adjusted and the ts_comp_nudge.." wgroup.long 0x3D030++0x3 line.long 0x0 "CPSW_NC_CPTS_EVENT_POP_REG,Event Pop Register" bitfld.long 0x0 0. "EVENT_POP,Event Pop - When a logic high is written to this bit an event is popped off the event FIFO. The event FIFO pop occurs as part of the interrupt process after the event has been read from the Event_0-3 registers. Popping an event discards the.." "0,1" rgroup.long 0x3D034++0xF line.long 0x0 "CPSW_NC_CPTS_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp lower 32-bits - The timestamp is valid for transmit receive and time stamp push event types. The timestamp value is not valid for counter roll event types." line.long 0x4 "CPSW_NC_CPTS_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt Queue (iet_incl = 1) - 0 - The packet was received/transmitted on the express queue. 1 - The packet was received/transmitted on the prempt queue." "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port Number - indicates the port number (encoded) of an Ethernet event or the encoded hardware timestamp number." newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Time Sync Event Type - 0000 - Time Stamp Push Event 0001 - Time Stamp Rollover Event 0010 - Time Stamp Half Rollover Event 0011 - Hardware Time Stamp Push Event 0100 - Ethernet Receive Event 0101 - Ethernet Transmit Event 0110 -.." hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type - The message type value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events." newline hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID - The 16-bit sequence id is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events." line.long 0x8 "CPSW_NC_CPTS_EVENT_2_REG,Event 2 Register" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain - The 8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events." line.long 0xC "CPSW_NC_CPTS_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp - The timestamp upper 32-bits are valid for transmit receive and time stamp push event types. This value is zero in 32-bit mode." group.long 0x3D044++0x17 line.long 0x0 "CPSW_NC_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time Stamp Load high Value - Writing the ts_load_en bit causes the value contained in this register (and the ts_load[63:0]) to be written into the time stamp. The time stamp value is read by initiating a time stamp push event not by reading.." line.long 0x4 "CPSW_NC_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time Stamp Comparison High Value - Writing a non-zero value to the TS_Comp_Length[31:0] register causes a pulse of TS_Comp_Length RCLK periods on the TS_COMP output and a comparison event when the time_stamp counter value is equivalent.." line.long 0x8 "CPSW_NC_CPTS_TS_ADD_VAL_REG,TS Add Value Register" bitfld.long 0x8 0.--2. "ADD_VAL,The ts_add_value[2:0] is added to 1 to comprise the timestamp increment value. The timestamp increment value is added to the current timestamp (time_stamp[63:0]) on each RCLK. The timestamp increment value can be adjusted by nudge and ppm also." "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_NC_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time Stamp PPM Low Value - The 64-bit PPM value takes effect when this low value is written. The high value should be written first. Note: There should be at least 10 clocks in between writes to the low register to ensure that the.." line.long 0x10 "CPSW_NC_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time Stamp PPM High Value - This value should be written first (before the low value is written). The minimum value of the ts_ppm is 0x400 (all 42 bits)." line.long 0x14 "CPSW_NC_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Timestamp Nudge Value - This two's complement number is added to the time_stamp[63:0] value to increase or decrease the timestamp value by the ts_nudge amount. The ts_nudge value is cleared to zero when the nudge has occurred." rgroup.long 0x3D0D0++0x3 line.long 0x0 "CPSW_NC_CPTS_TS_CONFIG,Time Stamp Configuration Read" hexmask.long.byte 0x0 8.--15. 1. "EVNT_FIFO_DEPTH,This is the configured value for the depth of the event FIFO. This parameter is passed in at module generation." hexmask.long.byte 0x0 0.--7. 1. "NUM_GENF,This is the configured value for the number of GENF outputs. This parameter is passed in at module generation." rgroup.long 0x3E000++0x7 line.long 0x0 "CPSW_NC_ALE_MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE_3g512e module." hexmask.long.word 0x0 16.--31. 1. "MODULE_ID,ALE_3g512e module ID." hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." line.long 0x4 "CPSW_NC_ALE_STATUS,The ALE status provides information on the ALE configuration and state. The ramdepth is used to determine how IPv6 entries are stored in the table. IPv6 entries are stored in two entries where IPv6 Entry Hi is designated by the odd.." bitfld.long 0x4 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table." "0,1" bitfld.long 0x4 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "POLCNTDIV8,This is the number of Classifiers the ALE implements divided by 8. A value of 4 indicates 32 policer engines total." bitfld.long 0x4 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1" newline bitfld.long 0x4 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1" hexmask.long.byte 0x4 0.--4. 1. "KLUENTRIES,This is the number of table entries total divided by 1024. A value of 1 indicates 1024 table entries. A value of 8 indicates 8192 table entries." group.long 0x3E008++0xF line.long 0x0 "CPSW_NC_ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports." bitfld.long 0x0 31. "ENABLE_ALE,Enable ALE 0 - Drop all packets 1 - Enable ALE packet processing" "0,1" bitfld.long 0x0 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero. Software must perform a clear table operation as part of the ALE setup/configuration process. Setting this bit causes all ALE accesses.." "0,1" newline bitfld.long 0x0 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit. This bit is cleared when the age out process has completed. This bit may be read. The age out.." "0,1" bitfld.long 0x0 24.--25. "MIRROR_DP,Mirror Destination Port - This field defines the port to which destination traffic destined will be duplicated. That is all traffic that is forwarded to this port will also be mirrored to the mirror_top port." "0,1,2,3" newline bitfld.long 0x0 21.--23. "UPD_BW_CTRL,The upd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur. At frequencies of 350Mhz the table update rate should be at it lowest or 5 Million updates per second. When.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--17. "MIRROR_TOP,Mirror To Port - This field defines the destination port for the mirror traffic. If the traffic is received or transmitted on the mirror destination port it will not be duplicated. Traffic defined as mirror traffic only may be dropped by the.." "0,1,2,3" newline bitfld.long 0x0 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable. When clear this bit will prevent any static entry (agable bit clear) from being updated due to port change. When set it allows static entries (agable bit clear) to update.." "0,1" bitfld.long 0x0 14. "LRN_HOST_DST,Learn Host Destination - This field is set to only learn unicast packet source addresses that are destined to the host port. This bit is only valid for 3 port switches and allows the ALE table to only contain addresses the host port is.." "0,1" newline bitfld.long 0x0 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled." "0,1" bitfld.long 0x0 12. "MIRROR_MEN,Mirror Match Entry Enable - This field enables the match mirror option. When this bit is set any traffic whose destination source VLAN or OUI matches the mirror_midx entry index will have that traffic also sent to the mirror_top port." "0,1" newline bitfld.long 0x0 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option. When this bit is set any traffic destined for the mirror_dp port will have its transmit traffic also sent to the mirror_top port." "0,1" bitfld.long 0x0 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option. When this bit is set any port with the pX_mirror_sp set in the ALE Port Control registers set will have its received traffic also sent to the mirror_top port." "0,1" newline bitfld.long 0x0 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host 0 - unknown unicast packets are not sent to the host 1 - unknown unicast packets flood to host port as well as other ports" "0,1" bitfld.long 0x0 7. "LEARN_NO_VLANID,Learn No VID - 0 - VID is learned with the source address 1 - VID is not learned with the source address (source address is not tied to VID). Determines the entry type." "0,1" newline bitfld.long 0x0 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode 0 - Process the priority tagged packet with VID = PORT_VLAN[11:0]. 1 - Process the priority tagged packet with VID = 0." "0,1" bitfld.long 0x0 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry. When cleared any packet source.." "0,1" newline bitfld.long 0x0 4. "ENABLE_BYPASS,ALE Bypass - When set packets received on non-host ports are sent to the host. It is expected that packets from the host are directed to the particular port. 0 - no bypass 1 - bypass the ALE" "0,1" bitfld.long 0x0 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode 0 - Broadcast and multicast rate limit counters are received port based 1 - Broadcast and multicast rate limit counters are transmit port based" "0,1" newline bitfld.long 0x0 2. "ALE_VLAN_AWARE,ALE VLAN Aware - Determines how traffic is forwarded using VLAN rules. 0 - Simple switch rules packets forwarded to all ports for unknown destinations. 1 - VLAN Aware rules packets forwarded based on VLAN members" "0,1" bitfld.long 0x0 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software. There is no auto learning of addresses in authorization mode and the packet will be dropped if the source address is not.." "0,1" newline bitfld.long 0x0 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit 0 - Broadcast/Multicast rates not limited 1 - Broadcast/Multicast packet reception limited to the port control register rate limit fields." "0,1" line.long 0x4 "CPSW_NC_ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports." bitfld.long 0x4 31. "TRK_EN_DST,Trunk Enable Destination Address - This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 30. "TRK_EN_SRC,Trunk Enable Source Address - This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 29. "TRK_EN_PRI,Trunk Enable Priority - This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. In the event that DSCP mapping is enabled and there is no VLAN the.." "0,1" bitfld.long 0x4 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN - This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 25. "TRK_EN_SIP,Trunk Enable Source IP Address - This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN tagged .." "0,1" bitfld.long 0x4 24. "TRK_EN_DIP,Trunk Enable Destination IP Address - This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN.." "0,1" newline bitfld.long 0x4 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet. Ethertypes 0-1500 are 802.3 lengths all others are Ether types." "0,1" bitfld.long 0x4 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set." "0,1" newline bitfld.long 0x4 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found." "0,1" bitfld.long 0x4 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the ALE_NXT_HDR register values." "0,1" newline bitfld.long 0x4 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value. Changing this value will cause the packet distribution on trunk ports to be changed. If all the trk_en_dst trk_en_src trk_en_pri and trk_en_vlan are '0' this value is used as the.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "MULTIHOST,The ~multihost allows host traffic to be sent bact to the host if the DA is market for the host port." "0,1" newline hexmask.long.word 0x4 0.--8. 1. "MIRROR_MIDX,Mirror Index - This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the mirror_top port. That is any VLAN ONU or address with or withou VLAN can be selected for traffic mirroring." line.long 0x8 "CPSW_NC_ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value." hexmask.long.tbyte 0x8 0.--19. 1. "ALE_PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters. The minimum operating value is 0x10. The prescaler is off when the value is zero." line.long 0xC "CPSW_NC_ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur. This value specifies the minimum time between aging starts." bitfld.long 0xC 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable - When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" bitfld.long 0xC 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable - When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" newline hexmask.long.tbyte 0xC 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer - This field specifies the number of clock cycles times 1 000 000 between aging operations." group.long 0x3E01C++0x7 line.long 0x0 "CPSW_NC_ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header. It is enabled via the ~iLmtNxtHdr bit in the VLAN entry. All four ~iip_nxt_hdr0-3 are compared when enabled. so if only one is.." hexmask.long.byte 0x0 24.--31. 1. "IP_NXT_HDR3,The ip_nxt_hdr3 is the forth protocol or next header compared when enabled." hexmask.long.byte 0x0 16.--23. 1. "IP_NXT_HDR2,The ip_nxt_hdr2 is the third protocol or next header compared when enabled." newline hexmask.long.byte 0x0 8.--15. 1. "IP_NXT_HDR1,The ip_nxt_hdr1 is the second protocol or next header compared when enabled." hexmask.long.byte 0x0 0.--7. 1. "IP_NXT_HDR0,The ip_nxt_hdr0 is the first protocol or next header compared when enabled." line.long 0x4 "CPSW_NC_ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries. After writing to this register any read or write to any ALE register will be stalled until the read or write operation completes." bitfld.long 0x4 31. "TABLEWR,Table Write - This bit is used to write the table words to the lookup table. 0 - Table Read Operation is performed. The contents of the TABLEIDX entry will be read into the ALE_TBLWx registers 1 - Table write operation is performed. This.." "0,1" hexmask.long.word 0x4 0.--8. 1. "TABLEIDX,The table index is used to determine which lookup table entry is read or written." group.long 0x3E034++0xF line.long 0x0 "CPSW_NC_ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry." hexmask.long.byte 0x0 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]" line.long 0x4 "CPSW_NC_ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry." hexmask.long 0x4 0.--31. 1. "TABLEWRD1,Table Entry bits [63:32]" line.long 0x8 "CPSW_NC_ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry." hexmask.long 0x8 0.--31. 1. "TABLEWRD0,Table Entry bits [31:0]" line.long 0xC "CPSW_NC_ALE_I0_PORTCTL0_j,The ALE Port Control Register sets the port specific modes of operation." hexmask.long.byte 0xC 24.--31. 1. "I0_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.." hexmask.long.byte 0xC 16.--23. 1. "I0_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.." newline bitfld.long 0xC 15. "I0_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN - When set cause any received packet with double VLANs to be dropped. That is if there are two ctag or two stag fields in the packet it will be dropped." "0,1" bitfld.long 0xC 14. "I0_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN - When set will cause any received packet with dual VLAN stag followed by ctag to be dropped." "0,1" newline bitfld.long 0xC 13. "I0_REG_P0_MACONLY_CAF,Mac Only Copy All Frames - When set a Mac Only port will transfer all received good frames to the host. When clear a Mac Only port will transfer packets to the host based on ALE destination address lookup operation (which operates.." "0,1" bitfld.long 0xC 12. "I0_REG_P0_DIS_PAUTHMOD,Disable Port authorization - When set will allow unknown addresses to arrive on a switch in authorization mode. It is intended for device to device network connection on ports which do not require MACSEC encryption." "0,1" newline bitfld.long 0xC 11. "I0_REG_P0_MACONLY,MAC Only - When set enables this port be treated like a MAC port for the host. All traffic received is only sent to the host. The host must direct traffic to this port as the lookup engine will not send traffic to the ports with the.." "0,1" bitfld.long 0xC 10. "I0_REG_P0_TRUNKEN,Trunk Enable - This field is used to enable a port into a trunk. Any port can be used as a trunk port any two or more ports with the p0_trunken its set and having the same p0_trunknum will be placed in the same trunk. There is no.." "0,1" newline bitfld.long 0xC 8.--9. "I0_REG_P0_TRUNKNUM,Trunk Number - This field is used as the trunk number when the p0_trunken is also set. Ports with the same trunk number that have the p0_trunken also set will have traffic distributed within the trunk based on the result of the hash.." "0,1,2,3" bitfld.long 0xC 7. "I0_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option. When this bit is set any traffic received on the port with the reg_p0_mirror_sp bit set will have its received traffic also sent to the mirror_top port." "0,1" newline bitfld.long 0xC 5. "I0_REG_P0_NO_SA_UPDATE,No Source Address Update - When set will not update the source addresses for this port." "0,1" bitfld.long 0xC 4. "I0_REG_P0_NO_LEARN,No Learn - When set will not learn the source addresses for this port." "0,1" newline bitfld.long 0xC 3. "I0_REG_P0_VID_INGRESS_CHECK,VLAN Ingress Check - When set if a packet received is not a member of the VLAN the packet will be dropped." "0,1" bitfld.long 0xC 2. "I0_REG_P0_DROP_UN_TAGGED,If Drop Untagged - When set will drop packets without a VLAN tag." "0,1" newline bitfld.long 0xC 0.--1. "I0_REG_P0_PORTSTATE,Port State - Defins the current port state used for lookup operations. 0 - Disabled 1 - Blocked 2 - Learning 3 - Forwarding" "0,1,2,3" group.long 0x3E090++0xF line.long 0x0 "CPSW_NC_ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID." bitfld.long 0x0 0.--2. "UVLAN_MEMBER_LIST,Unknown VLAN Member List - Each bit represents the port member status for unknown VLANs." "0,1,2,3,4,5,6,7" line.long 0x4 "CPSW_NC_ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID." bitfld.long 0x4 0.--2. "UVLAN_UNREG_MCAST_FLOOD_MASK,Unknown VLAN Unregister Multicast Flood Mask - Each bit represents the port to which unregistered multicast are sent for unregistered VLANs." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_NC_ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID." bitfld.long 0x8 0.--2. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask - Each bit represents the port to which registered multicast are sent for unregistered VLANs. This field is ANDed with the registered multicast mask to determine the destinations for.." "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_NC_ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed." bitfld.long 0xC 0.--2. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask - Each bit represents the port where the VLAN will be removed for unregistered VLANs." "0,1,2,3,4,5,6,7" group.long 0x3E0B4++0xB line.long 0x0 "CPSW_NC_ALE_FAST_LUT,The Fast LUT registers allows the ports to be placed in Fast LUT mode." bitfld.long 0x0 0.--2. "FAST_LUT,The ~Fast_LUT field alows any port to be Fast_LUT mode which will cause all lookup operations to start based on DA/SA and VLAN only. That is any data beyong the first 32 are not used in the lookup process." "0,1,2,3,4,5,6,7" line.long 0x4 "CPSW_NC_ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters. This register is for diagnostice only." bitfld.long 0x4 15. "PBCAST_DIAG,When set and the port_diag is set to zero will allow all ports to see the same stat diagnostic increment." "0,1" bitfld.long 0x4 8.--9. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received. For the selected Port. 0: Disabled 1: Destination Equal Source Drop Stat will count 2: VLAN Ingress Check Drop Stat will count 3: Source Multicast.." line.long 0x8 "CPSW_NC_ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port." bitfld.long 0x8 0.--2. "OAM_LB_CTRL,The oam_lb_ctrl allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an egressop of 0xFF which swaps the source and destination address. BPDUs will still flow through as normal so.." "0,1,2,3,4,5,6,7" group.long 0x3E0FC++0x17 line.long 0x0 "CPSW_NC_ALE_EGRESSOP,The Egress Operation register allows enabled classifiers with any match like IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions. If the packet was destined for the host or is destined to any.." hexmask.long.byte 0x0 24.--31. 1. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations 0: NOP : 1-n: Defines which egress Operation will be performed. This allows Inter VLAN routing to be configured for high bandwidth traffic reducing CPU.." bitfld.long 0x0 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well. The DA SA and VLAN are ignored for trunk generation on InterVLAN Routing so that this field is the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions. The packet will be routed to the host it was destined to." "0,1" bitfld.long 0x0 0.--2. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to. If a destination is a Trunk all the port bits for that trunck must be set." "0,1,2,3,4,5,6,7" line.long 0x4 "CPSW_NC_ALE_POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching." bitfld.long 0x4 31. "PORT_MEN,Port Match Enable - Enabled port match for the selected policing/classifier entry" "0,1" bitfld.long 0x4 30. "TRUNKID,Trunk ID - When set indicates the port number is a trunk group." "0,1" newline bitfld.long 0x4 25.--26. "PORT_NUM,Port Number - Specifies the port address to match for the selected policing/classifier entry" "0,1,2,3" bitfld.long 0x4 19. "PRI_MEN,Priority Match Enable - Enables frame priority match for the selected policing/classifier entry" "0,1" newline bitfld.long 0x4 16.--18. "PRI_VAL,Priority Value - Specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "ONU_MEN,OUI Match Enable - Enables frame ONU address match for the selected policing/classifier entry" "0,1" newline hexmask.long.word 0x4 0.--8. 1. "ONU_INDEX,OUI Table Entry Index - Specifies the ALE ONU address lookup table index to match for the selected policing/classifier entry" line.long 0x8 "CPSW_NC_ALE_POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses" bitfld.long 0x8 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1" hexmask.long.word 0x8 16.--24. 1. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0x8 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1" hexmask.long.word 0x8 0.--8. 1. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" line.long 0xC "CPSW_NC_ALE_POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses" bitfld.long 0xC 31. "OVLAN_MEN,Outer VLAN Match Enable - Enables frame Outer VLAN address match for the selected policing/classifier entry" "0,1" hexmask.long.word 0xC 16.--24. 1. "OVLAN_INDEX,Outer VLAN Table Entry Index - Specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0xC 15. "IVLAN_MEN,Inner VLAN Match Enable - Enables frame Inner VLAN address match for the selected policing/classifier entry" "0,1" hexmask.long.word 0xC 0.--8. 1. "IVLAN_INDEX,Inner VLAN Table Entry Index - Specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry" line.long 0x10 "CPSW_NC_ALE_POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address" bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable - Enables frame Ether Type match for the selected policing/classifier entry" "0,1" hexmask.long.word 0x10 16.--24. 1. "ETHERTYPE_INDEX,EtherType Table Entry Index - Specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable - Enables frame IP Source address match for the selected policing/classifier entry" "0,1" hexmask.long.word 0x10 0.--8. 1. "IPSRC_INDEX,IP Source Address Table Entry Index - Specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry" line.long 0x14 "CPSW_NC_ALE_POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address" bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable - Enables frame IP Destination address match for the selected policing/classifier entry" "0,1" hexmask.long.word 0x14 16.--24. 1. "IPDST_INDEX,IP Destination Address Table Entry Index - Specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry" group.long 0x3E118++0x13 line.long 0x0 "CPSW_NC_ALE_POLICECFG6,The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED. else it can.." hexmask.long 0x0 0.--31. 1. "PIR_IDLE_INC_VAL,Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle. If zero the PIR counter is disabled and packets will never be marked or processed as RED." line.long 0x4 "CPSW_NC_ALE_POLICECFG7,The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked GREEN..." hexmask.long 0x4 0.--31. 1. "CIR_IDLE_INC_VAL,Committed Information Idle Increment Value - The number added to the CIR counter every clock cycle. If zero the CIR counter is disabled and packets will never be marked or processed as YELLOW." line.long 0x8 "CPSW_NC_ALE_POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry. The selected policing/classifier entry is only read or written after this register is written based on the value of the ~iwrite_enable bit." bitfld.long 0x8 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG0-7 to the pol_tbl_idx selected policing/classifier entry. Clearing this bit will read the pol_tbl_idx selected policing/classifier entry into the POLICECFG0-7 registers." "0,1" hexmask.long.byte 0x8 0.--4. 1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written. When writing to this field without setting the write_enable=1 will cause the selected policing/classifier entry to be loaded into the.." line.long 0xC "CPSW_NC_ALE_POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules." bitfld.long 0xC 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities." "0,1" bitfld.long 0xC 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets." "0,1" newline bitfld.long 0xC 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the yellowthresh value. This field would normally not be used as to let the switch drop packets at a buffer threshold instead. In the event that the switch does not.." "0,1" bitfld.long 0xC 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the yellow_drop_en enable. 0-100% 1=50% 2-33% 3-25% 4=20% 5-17% 6-14% 7-13%" "?,1: 50% 2-33% 3-25%,?,?,4: 20% 5-17% 6-14% 7-13%,?,?,?" newline bitfld.long 0xC 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. 0 - No Hit packets are marked GREEN 1 - No Hit packets are marked YELLOW 2 - No Hit packets are marked RED 3 - No Hit.." "0,1,2,3" bitfld.long 0xC 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled." "0,1" newline bitfld.long 0xC 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports. That is the default thread will be {port priority}. If the traffic matches a classifier with a thread mapping the classifier thread mapping.." "0,1" line.long 0x10 "CPSW_NC_ALE_POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition." bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit." "0,1" bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a RED condition." "0,1" newline bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a YELLOW condition." "0,1" bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits. This bit is self clearing." "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written." rgroup.long 0x3E12C++0x3 line.long 0x0 "CPSW_NC_ALE_POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier." bitfld.long 0x0 31. "POL_HIT,Policer Hit - This indicates that the selected policing/classifier via the pol_test_idx field has been hit by a packet seen on any port that matches the policing/classifier entry match." "0,1" bitfld.long 0x0 30. "POL_REDHIT,Policer Hit RED - This indicates that the selected policing/classifier via the pol_test_idx field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match." "0,1" newline bitfld.long 0x0 29. "POL_YELLOWHIT,Policer Hit YELLOW - This indicates that the selected policing/classifier via the pol_test_idx field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match." "0,1" group.long 0x3E134++0xB line.long 0x0 "CPSW_NC_ALE_THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched." bitfld.long 0x0 15. "DEFTHREAD_EN,Default Tread Enable - When set the switch will use the defthreadval for the host interface thread ID if no classifier is matched. If clear the switch will generate its own thread ID based on port and priority if there is no classifier match." "0,1" hexmask.long.byte 0x0 0.--5. 1. "DEFTHREADVAL,Default Thread Value - This field specifies the default thread ID value." line.long 0x4 "CPSW_NC_ALE_THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host. This allows particular classifier matched traffic to be placed an a particular hosts queue." hexmask.long.byte 0x4 0.--4. 1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the THREADMAPVAL register." line.long 0x8 "CPSW_NC_ALE_THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry." bitfld.long 0x8 15. "THREAD_EN,Thread Enable - When set the switch will use the threadval for the selected classifier match. If clear the the thread ID will be determined by the THREADMAPDEF register settings." "0,1" hexmask.long.byte 0x8 0.--5. 1. "THREADVAL,Thread Value - This field is the thread ID value that is used to map a classifier hit to thread ID for host traffic." rgroup.long 0x3F000++0x3 line.long 0x0 "CPSW_NC_ECC_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x3F008++0x3 line.long 0x0 "CPSW_NC_ECC_VECTOR,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0x3F00C++0x3 line.long 0x0 "CPSW_NC_ECC_STAT,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x3F010++0x3 line.long 0x0 "CPSW_NC_ECC_RESERVED_SVBUS_j,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3F03C++0x7 line.long 0x0 "CPSW_NC_ECC_SEC_EOI_REG,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_NC_ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" newline bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" newline bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" newline bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" newline bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" newline bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" newline bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" newline bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" newline bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x3F080++0x3 line.long 0x0 "CPSW_NC_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" newline bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" newline bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" newline bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" newline bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x3F0C0++0x3 line.long 0x0 "CPSW_NC_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" newline bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" newline bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" newline bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" newline bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x3F13C++0x7 line.long 0x0 "CPSW_NC_ECC_DED_EOI_REG,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_NC_ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" newline bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" newline bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" newline bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" newline bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" newline bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" newline bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" newline bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" newline bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x3F180++0x3 line.long 0x0 "CPSW_NC_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" newline bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" newline bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" newline bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" newline bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x3F1C0++0x3 line.long 0x0 "CPSW_NC_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" newline bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" newline bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" newline bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" newline bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" newline bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" newline bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x3F200++0xF line.long 0x0 "CPSW_NC_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPSW_NC_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPSW_NC_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPSW_NC_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" group.long 0x3D0E0++0x1B line.long 0x0 "CPSW_NC_CPTS_TS_GENF_COMP_LOW_REG_j,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,GENFn comparison value lower 32-bits. This value should be written after the upper 32-bits. The ts_GENFn_comp high and low should only be written when the ts_GENFn_length value is zero." line.long 0x4 "CPSW_NC_CPTS_TS_GENF_COMP_HIGH_REG_j,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,GENFn comparison value upper 32-bits. This value should be written before the lower 32-bits are written. The ts_GENFn_comp high and low should only be written when the ts_GENFn_length value is zero." line.long 0x8 "CPSW_NC_CPTS_TS_GENF_CONTROL_REG_j,Time Stamp Generate Function Control" bitfld.long 0x8 1. "PPM_DIR,Generate function N PPM direction - 0 - A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1 - A single RCLK is subtracted.." "0,1" bitfld.long 0x8 0. "POLARITY_INV,Generate function N Polarity - 0 - The output TS_GENFn signal asserts high. 1 - The output TS_GENFn signal asserts low" "0,1" line.long 0xC "CPSW_NC_CPTS_TS_GENF_LENGTH_REG_j,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,GENFn length - The minimum operational value is decimal 5. Note: Software is advised to write and then read the comparison value before writing a non-zero value to the genf length to ensure that the comparison value is synchronized across.." line.long 0x10 "CPSW_NC_CPTS_TS_GENF_PPM_LOW_REG_j,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,GENFn PPM Low Value - The 64-bit PPM value takes effect when this low value is written. The high value should be written first." line.long 0x14 "CPSW_NC_CPTS_TS_GENF_PPM_HIGH_REG_j,Time Stamp Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,GENFn PPM High Value - This value should be written first (before the low value is written)." line.long 0x18 "CPSW_NC_CPTS_TS_GENF_NUDGE_REG_j,Time Stamp Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,GENFn Nudge Value - This two's complement number is added to the generate counter value to increase or decrease the length by the ts_genfN_nudge amount. Only a single high or low time is adjusted and the ts_genfN_nudge value is cleared to zero.." group.long 0x3D200++0x1B line.long 0x0 "CPSW_NC_CPTS_TS_ESTF_COMP_LOW_REG_j,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,ESTFn comparison value lower 32-bits. This value should be written after the upper 32-bits. The ts_ESTFn_comp high and low should only be written when the ts_ESTFn_length value is zero." line.long 0x4 "CPSW_NC_CPTS_TS_ESTF_COMP_HIGH_REG_j,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,ESTFn comparison value upper 32-bits. This value should be written before the lower 32-bits are written. The ts_ESTFn_comp high and low should only be written when the ts_ESTFn_length value is zero." line.long 0x8 "CPSW_NC_CPTS_TS_ESTF_CONTROL_REG_j,Time Stamp ESTF Generate Function Control" bitfld.long 0x8 1. "PPM_DIR,Generate function N PPM direction - 0 - A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1 - A single RCLK is subtracted.." "0,1" bitfld.long 0x8 0. "POLARITY_INV,Generate function N Polarity - 0 - The output TS_ESTFn signal asserts low. 1 - The output TS_ESTFn signal asserts high." "0,1" line.long 0xC "CPSW_NC_CPTS_TS_ESTF_LENGTH_REG_j,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,ESTFn length - The minimum operational value is decimal 5. Note: Software is advised to write and then read the comparison value before writing a non-zero value to the genf length to ensure that the comparison value is synchronized across.." line.long 0x10 "CPSW_NC_CPTS_TS_ESTF_PPM_LOW_REG_j,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,ESTFn PPM Low Value - The 64-bit PPM value takes effect when this low value is written. The high value should be written first." line.long 0x14 "CPSW_NC_CPTS_TS_ESTF_PPM_HIGH_REG_j,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,ESTFn PPM High Value - This value should be written first (before the low value is written)." line.long 0x18 "CPSW_NC_CPTS_TS_ESTF_NUDGE_REG_j,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,ESTFn Nudge Value - This two's complement number is added to the generate counter value to increase or decrease the length by the ts_estfN_nudge amount. Only a single high or low time is adjusted and the ts_estfN_nudge value is cleared to zero.." tree.end tree "DAC0" base ad:0x50260000 rgroup.word 0x0++0x1 line.word 0x0 "DAC_DACREV,DAC Revision Register." hexmask.word.byte 0x0 0.--7. 1. "REV,DAC Revision" group.word 0x2++0x1 line.word 0x0 "DAC_DACCTL_ALT2_,DAC Control Register." hexmask.word.byte 0x0 4.--8. 1. "SYNCSEL,DAC EPWMSYNCPER select. Determines which EPWMSYNCPER signal will update the DACVALA register. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2 EPWM3SYNCPER ..." bitfld.word 0x0 2. "LOADMODE,DACVALA load mode. Determines when the DACVALA register is updated with the value from DACVALS. 0 Load on next SYSCLK 1 Load on next EPWMSYNCPER specified by SYNCSEL" "0,1" bitfld.word 0x0 1. "MODE,DAC gain mode select. Selects the gain mode for the buffered output. The MODE value is only used when DACREFSEL=1 and internal ADC reference mode is selected. 0 Gain is 1 1 Gain is 2" "0,1" bitfld.word 0x0 0. "DACREFSEL,DAC reference select. Selects which voltage references are used by the DAC. 0 VDAC/VSSA are the reference voltages 1 ADC VREFHI/VSSA are the reference voltages" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "DAC_DACVALA,DAC Value Register - Active." hexmask.word 0x0 0.--11. 1. "DACVALA,Active output code currently driven by the DAC" group.word 0x6++0x5 line.word 0x0 "DAC_DACVALS,DAC Value Register - Shadow." hexmask.word 0x0 0.--11. 1. "DACVALS,Shadow output code to be loaded into DACVALA" line.word 0x2 "DAC_DACOUTEN,DAC Output Enable Register." bitfld.word 0x2 0. "DACOUTEN,DAC output enable 0 DAC output is disabled 1 DAC output is enabled" "0,1" line.word 0x4 "DAC_DACLOCK,DAC Lock Register." hexmask.word.byte 0x4 12.--15. 1. "KEY,Writes to this register succeed only if this field is written with a value of 0xA. Only 16-bit writes will succeed [provided the KEY matches]. Read-modify-writes to individual bits in this register will be ignored." bitfld.word 0x4 2. "DACOUTEN,Lock write-access to the DACOUTEN register. 0 DACOUTEN register is not locked. Write 0 to this bit has no effect. 1 DACOUTEN register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0x4 1. "DACVAL,Lock write-access to the DACVALS register. 0 DACVALS register is not locked. Write 0 to this bit has no effect. 1 DACVALS register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0x4 0. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0xE++0x1 line.word 0x0 "DAC_DACCONFIG,DAC Configuration Register." hexmask.word 0x0 0.--15. 1. "CONFIG,DAC Configuration. This bit field is used for TI internal testing/debugging." tree.end tree "DCC" base ad:0x0 tree "DCC0" base ad:0x52B00000 group.long 0x0++0x3 line.long 0x0 "MSS_DCC_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register.User privilege and debug mode (read):0101= the done signal is disabledothers = the done signal is enabledPrivilege and.." newline hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC.User privilege and debug mode (read):1010= stop counting when counter0 and valid0 both reach zero1011= stop counting when counter1 reaches zeroothers = continuously repeat.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read):0101= the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101= disable error signal generation others 1010.." newline hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc.User privilege and debug mode (read):0101= counters are stoppedothers = counters are runningPrivilege and debug mode (write):0101= stop counters and error-checkingothers 1010 = load the.." rgroup.long 0x4++0x3 line.long 0x0 "MSS_DCC_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01.Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained.User privilege and debug mode (read): 0x0Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented.User privilege and debug mode (read): 0x1Privilege and debug mode (write): Writes have no effect." newline bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module.User privilege and debug mode (read): 0x2Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software.User privilege and debug mode (read): 0x0Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module.User privilege and debug mode (read): 0x4Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "MSS_DCC_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0).User privilege and debug mode (read):Returns the current seed value for counter 0.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0x4 "MSS_DCC_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0.User privilege and debug mode (read):Returns the current seed value for VALID0.Privilege and debug mode (write):Sets the current seed.." line.long 0x8 "MSS_DCC_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1).User privilege and debug mode (read):Returns the current seed value for counter 1.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0xC "MSS_DCC_DCCSTATUS,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = single-shot mode is not done1 = single-shot mode is donePrivilege and debug mode (write):0 = no effect1.." "0: no effect1 = clear the done flag,?" newline bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = an error has not occurred1 = an error has occurredPrivilege and debug mode (write):0 = no effect1 = clear the error.." "0: no effect1 = clear the error flag,?" rgroup.long 0x18++0xB line.long 0x0 "MSS_DCC_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0.User privilege and debug mode (read):Returns either the current value of Count 0 or the Count 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):Writes have no.." line.long 0x4 "MSS_DCC_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0.User privilege and debug mode (read):Returns either the current value of Valid 0 or the Valid 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):writes.." line.long 0x8 "MSS_DCC_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1.User privilege and debug mode (read):Returns either the current value of Count 1 or the Count 1 FIFO location depending upon DCCGCTRL2.FIFO_READ 1.Privilege and debug mode (write):writes have no.." group.long 0x24++0xB line.long 0x0 "MSS_DCC_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC1.Privilege and debug mode (write):Sets the value of CLKSRC1." line.long 0x4 "MSS_DCC_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC0.Privilege and debug mode (write):Sets the value of CLKSRC0." line.long 0x8 "MSS_DCC_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Enable values:0101 Comparison and counter.." rgroup.long 0x30++0x3 line.long 0x0 "MSS_DCC_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full.User privilege and debug mode (read):0:Count1 FIFO is not full1:Count1 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full1:Count1 FIFO is full,?" newline bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full.User privilege and debug mode (read):0:Valid0 FIFO is not full1:Valid0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full1:Valid0 FIFO is full,?" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full.User privilege and debug mode (read):0:Count0 FIFO is not full1:Count0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full1:Count0 FIFO is full,?" newline bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty.User privilege and debug mode (read):0:Count1 FIFO is not empty1:Count1 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty1:Count1 FIFO is empty,?" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty.User privilege and debug mode (read):0:Valid0 FIFO is not empty1:Valid0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty1:Valid0 FIFO is empty,?" newline bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty.User privilege and debug mode (read):0:Count0 FIFO is not empty1:Count0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty1:Count0 FIFO is empty,?" group.long 0x34++0x3 line.long 0x0 "MSS_DCC_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC1" base ad:0x52B01000 group.long 0x0++0x3 line.long 0x0 "MSS_DCC_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register.User privilege and debug mode (read):0101= the done signal is disabledothers = the done signal is enabledPrivilege and.." newline hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC.User privilege and debug mode (read):1010= stop counting when counter0 and valid0 both reach zero1011= stop counting when counter1 reaches zeroothers = continuously repeat.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read):0101= the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101= disable error signal generation others 1010.." newline hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc.User privilege and debug mode (read):0101= counters are stoppedothers = counters are runningPrivilege and debug mode (write):0101= stop counters and error-checkingothers 1010 = load the.." rgroup.long 0x4++0x3 line.long 0x0 "MSS_DCC_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01.Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained.User privilege and debug mode (read): 0x0Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented.User privilege and debug mode (read): 0x1Privilege and debug mode (write): Writes have no effect." newline bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module.User privilege and debug mode (read): 0x2Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software.User privilege and debug mode (read): 0x0Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module.User privilege and debug mode (read): 0x4Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "MSS_DCC_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0).User privilege and debug mode (read):Returns the current seed value for counter 0.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0x4 "MSS_DCC_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0.User privilege and debug mode (read):Returns the current seed value for VALID0.Privilege and debug mode (write):Sets the current seed.." line.long 0x8 "MSS_DCC_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1).User privilege and debug mode (read):Returns the current seed value for counter 1.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0xC "MSS_DCC_DCCSTATUS,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = single-shot mode is not done1 = single-shot mode is donePrivilege and debug mode (write):0 = no effect1.." "0: no effect1 = clear the done flag,?" newline bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = an error has not occurred1 = an error has occurredPrivilege and debug mode (write):0 = no effect1 = clear the error.." "0: no effect1 = clear the error flag,?" rgroup.long 0x18++0xB line.long 0x0 "MSS_DCC_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0.User privilege and debug mode (read):Returns either the current value of Count 0 or the Count 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):Writes have no.." line.long 0x4 "MSS_DCC_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0.User privilege and debug mode (read):Returns either the current value of Valid 0 or the Valid 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):writes.." line.long 0x8 "MSS_DCC_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1.User privilege and debug mode (read):Returns either the current value of Count 1 or the Count 1 FIFO location depending upon DCCGCTRL2.FIFO_READ 1.Privilege and debug mode (write):writes have no.." group.long 0x24++0xB line.long 0x0 "MSS_DCC_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC1.Privilege and debug mode (write):Sets the value of CLKSRC1." line.long 0x4 "MSS_DCC_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC0.Privilege and debug mode (write):Sets the value of CLKSRC0." line.long 0x8 "MSS_DCC_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Enable values:0101 Comparison and counter.." rgroup.long 0x30++0x3 line.long 0x0 "MSS_DCC_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full.User privilege and debug mode (read):0:Count1 FIFO is not full1:Count1 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full1:Count1 FIFO is full,?" newline bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full.User privilege and debug mode (read):0:Valid0 FIFO is not full1:Valid0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full1:Valid0 FIFO is full,?" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full.User privilege and debug mode (read):0:Count0 FIFO is not full1:Count0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full1:Count0 FIFO is full,?" newline bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty.User privilege and debug mode (read):0:Count1 FIFO is not empty1:Count1 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty1:Count1 FIFO is empty,?" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty.User privilege and debug mode (read):0:Valid0 FIFO is not empty1:Valid0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty1:Valid0 FIFO is empty,?" newline bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty.User privilege and debug mode (read):0:Count0 FIFO is not empty1:Count0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty1:Count0 FIFO is empty,?" group.long 0x34++0x3 line.long 0x0 "MSS_DCC_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC2" base ad:0x52B02000 group.long 0x0++0x3 line.long 0x0 "MSS_DCC_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register.User privilege and debug mode (read):0101= the done signal is disabledothers = the done signal is enabledPrivilege and.." newline hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC.User privilege and debug mode (read):1010= stop counting when counter0 and valid0 both reach zero1011= stop counting when counter1 reaches zeroothers = continuously repeat.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read):0101= the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101= disable error signal generation others 1010.." newline hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc.User privilege and debug mode (read):0101= counters are stoppedothers = counters are runningPrivilege and debug mode (write):0101= stop counters and error-checkingothers 1010 = load the.." rgroup.long 0x4++0x3 line.long 0x0 "MSS_DCC_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01.Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained.User privilege and debug mode (read): 0x0Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented.User privilege and debug mode (read): 0x1Privilege and debug mode (write): Writes have no effect." newline bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module.User privilege and debug mode (read): 0x2Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software.User privilege and debug mode (read): 0x0Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module.User privilege and debug mode (read): 0x4Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "MSS_DCC_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0).User privilege and debug mode (read):Returns the current seed value for counter 0.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0x4 "MSS_DCC_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0.User privilege and debug mode (read):Returns the current seed value for VALID0.Privilege and debug mode (write):Sets the current seed.." line.long 0x8 "MSS_DCC_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1).User privilege and debug mode (read):Returns the current seed value for counter 1.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0xC "MSS_DCC_DCCSTATUS,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = single-shot mode is not done1 = single-shot mode is donePrivilege and debug mode (write):0 = no effect1.." "0: no effect1 = clear the done flag,?" newline bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = an error has not occurred1 = an error has occurredPrivilege and debug mode (write):0 = no effect1 = clear the error.." "0: no effect1 = clear the error flag,?" rgroup.long 0x18++0xB line.long 0x0 "MSS_DCC_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0.User privilege and debug mode (read):Returns either the current value of Count 0 or the Count 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):Writes have no.." line.long 0x4 "MSS_DCC_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0.User privilege and debug mode (read):Returns either the current value of Valid 0 or the Valid 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):writes.." line.long 0x8 "MSS_DCC_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1.User privilege and debug mode (read):Returns either the current value of Count 1 or the Count 1 FIFO location depending upon DCCGCTRL2.FIFO_READ 1.Privilege and debug mode (write):writes have no.." group.long 0x24++0xB line.long 0x0 "MSS_DCC_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC1.Privilege and debug mode (write):Sets the value of CLKSRC1." line.long 0x4 "MSS_DCC_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC0.Privilege and debug mode (write):Sets the value of CLKSRC0." line.long 0x8 "MSS_DCC_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Enable values:0101 Comparison and counter.." rgroup.long 0x30++0x3 line.long 0x0 "MSS_DCC_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full.User privilege and debug mode (read):0:Count1 FIFO is not full1:Count1 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full1:Count1 FIFO is full,?" newline bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full.User privilege and debug mode (read):0:Valid0 FIFO is not full1:Valid0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full1:Valid0 FIFO is full,?" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full.User privilege and debug mode (read):0:Count0 FIFO is not full1:Count0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full1:Count0 FIFO is full,?" newline bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty.User privilege and debug mode (read):0:Count1 FIFO is not empty1:Count1 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty1:Count1 FIFO is empty,?" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty.User privilege and debug mode (read):0:Valid0 FIFO is not empty1:Valid0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty1:Valid0 FIFO is empty,?" newline bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty.User privilege and debug mode (read):0:Count0 FIFO is not empty1:Count0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty1:Count0 FIFO is empty,?" group.long 0x34++0x3 line.long 0x0 "MSS_DCC_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC3" base ad:0x52B03000 group.long 0x0++0x3 line.long 0x0 "MSS_DCC_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register.User privilege and debug mode (read):0101= the done signal is disabledothers = the done signal is enabledPrivilege and.." newline hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC.User privilege and debug mode (read):1010= stop counting when counter0 and valid0 both reach zero1011= stop counting when counter1 reaches zeroothers = continuously repeat.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read):0101= the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101= disable error signal generation others 1010.." newline hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc.User privilege and debug mode (read):0101= counters are stoppedothers = counters are runningPrivilege and debug mode (write):0101= stop counters and error-checkingothers 1010 = load the.." rgroup.long 0x4++0x3 line.long 0x0 "MSS_DCC_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01.Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained.User privilege and debug mode (read): 0x0Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented.User privilege and debug mode (read): 0x1Privilege and debug mode (write): Writes have no effect." newline bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module.User privilege and debug mode (read): 0x2Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software.User privilege and debug mode (read): 0x0Privilege and debug mode (write): Writes have no effect." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module.User privilege and debug mode (read): 0x4Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "MSS_DCC_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0).User privilege and debug mode (read):Returns the current seed value for counter 0.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0x4 "MSS_DCC_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0.User privilege and debug mode (read):Returns the current seed value for VALID0.Privilege and debug mode (write):Sets the current seed.." line.long 0x8 "MSS_DCC_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1).User privilege and debug mode (read):Returns the current seed value for counter 1.Privilege and debug mode (write):Sets the current seed value for counter.." line.long 0xC "MSS_DCC_DCCSTATUS,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = single-shot mode is not done1 = single-shot mode is donePrivilege and debug mode (write):0 = no effect1.." "0: no effect1 = clear the done flag,?" newline bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag.User privilege and debug mode (read):0 = an error has not occurred1 = an error has occurredPrivilege and debug mode (write):0 = no effect1 = clear the error.." "0: no effect1 = clear the error flag,?" rgroup.long 0x18++0xB line.long 0x0 "MSS_DCC_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0.User privilege and debug mode (read):Returns either the current value of Count 0 or the Count 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):Writes have no.." line.long 0x4 "MSS_DCC_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0.User privilege and debug mode (read):Returns either the current value of Valid 0 or the Valid 0 FIFO location depending upon DCCGCTRL2.FIFO_READ.Privilege and debug mode (write):writes.." line.long 0x8 "MSS_DCC_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1.User privilege and debug mode (read):Returns either the current value of Count 1 or the Count 1 FIFO location depending upon DCCGCTRL2.FIFO_READ 1.Privilege and debug mode (write):writes have no.." group.long 0x24++0xB line.long 0x0 "MSS_DCC_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC1.Privilege and debug mode (write):Sets the value of CLKSRC1." line.long 0x4 "MSS_DCC_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0.User privilege and debug mode (read):Returns the current value of the key.Privilege and debug mode (write):Sets the key value.Key values:1010 The CLKSRC field selects the clock.." newline hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0 when the KEY field enables this feature.User privilege and debug mode (read):Returns the current value of CLKSRC0.Privilege and debug mode (write):Sets the value of CLKSRC0." line.long 0x8 "MSS_DCC_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Source values:0101.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition.User privilege and debug mode (read):Returns the current field value.Privilege and debug mode (write):Sets the value of field value.Enable values:0101 Comparison and counter.." rgroup.long 0x30++0x3 line.long 0x0 "MSS_DCC_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full.User privilege and debug mode (read):0:Count1 FIFO is not full1:Count1 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full1:Count1 FIFO is full,?" newline bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full.User privilege and debug mode (read):0:Valid0 FIFO is not full1:Valid0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full1:Valid0 FIFO is full,?" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full.User privilege and debug mode (read):0:Count0 FIFO is not full1:Count0 FIFO is full.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full1:Count0 FIFO is full,?" newline bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty.User privilege and debug mode (read):0:Count1 FIFO is not empty1:Count1 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty1:Count1 FIFO is empty,?" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty.User privilege and debug mode (read):0:Valid0 FIFO is not empty1:Valid0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty1:Valid0 FIFO is empty,?" newline bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty.User privilege and debug mode (read):0:Count0 FIFO is not empty1:Count0 FIFO is empty.Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty1:Count0 FIFO is empty,?" group.long 0x34++0x3 line.long 0x0 "MSS_DCC_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree.end tree "ECAP" base ad:0x0 tree "ECAP00" base ad:0x50240000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP01" base ad:0x50241000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP02" base ad:0x50242000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP03" base ad:0x50243000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP04" base ad:0x50244000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP05" base ad:0x50245000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP06" base ad:0x50246000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP07" base ad:0x50247000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP08" base ad:0x50248000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP09" base ad:0x50249000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP10" base ad:0x5024A000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP11" base ad:0x5024B000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP12" base ad:0x5024C000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP13" base ad:0x5024D000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP14" base ad:0x5024E000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP15" base ad:0x5024F000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCTR,Time-Stamp Counter." hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1] This register reads HRCOUNTER value and is not writable 2] can be reset using CTRFILTRESET 3] Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "ECAP_CTRPHS,Counter Phase Offset Value Register." hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "ECAP_CAP1,Capture 1 Register." hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes/initialization.3. APRD shadow register (ECAP_CAP3) when used in APWM mode." line.long 0xC "ECAP_CAP2,Capture 2 Register." hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:1. Time-Stamp (counter value) during a capture event.2. Software - may be useful for test purposes.3. ACMP shadow register (ECAP_CAP4) when used in APWM mode." line.long 0x10 "ECAP_CAP3,Capture 3 Register." hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register.In APMW mode this is the period shadow (APER) register.User updates the PWM period value via this register.In this mode the ECAP_CAP3 (APRD) register shadows the ECAP_CAP1 register." line.long 0x14 "ECAP_CAP4,Capture 4 Register." hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register.In APMW mode this is the compare shadow (ACMP) register.User updates the PWM Compare value via this register.In this mode the ECAP_CAP4 (ACMP) register shadows the ECAP_CAP2 register." group.long 0x24++0x3 line.long 0x0 "ECAP_ECCTL0,Capture Control Register 0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "ECAP_ECCTL1,Capture Control Register 1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0 TSCTR counter stops immediately on emulation suspend1 TSCTR counter runs until = 02 TSCTR counter is unaffected by emulation suspend (Run Free)3 TSCTR counter is unaffected by emulation.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0 Divide by 1 (i.e . no prescale by-pass the prescaler)1 Divide by 22 Divide by 43 Divide by 64 Divide by 85 Divide by 1030 Divide by 6031 Divide by 62" newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 Disable CAP1-4 register loads at capture event time.1 Enable CAP1-4 register loads at capture.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 Do not reset counter on Capture Event 4 (absolute time stamp operation)1 Reset counter after Capture Event 4 time- stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 Capture Event 4 triggered on a rising edge (RE)1 Capture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 Do not reset counter on Capture Event 3 (absolute time stamp)1 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge (RE)1 Capture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 (absolute time stamp)1 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 Capture Event 2 triggered on a rising edge (RE)1 Capture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 Do not reset counter on Capture Event 1 (absolute time stamp)1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 Capture Event 1 triggered on a rising edge (RE)1 Capture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "ECAP_ECCTL2,Capture Control Register 2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h[R] = No effect 1h[W] = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 Output is active high (Compare value defines high time)1 Output is active low (Compare value defines low time)" "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers -.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 Writing a zero has no.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0 sync out signal is SWSYNC1 Select CTR = PRD event to be the sync-out signal3 Disable sync out signal" "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter [TSCTR] Sync-In select mode 0 Disable sync-in option1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp [TSCTR] Counter Stop [freeze] Control 0 TSCTR stopped1 TSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 Has no effect (reading always returns a 0)1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control [applicable only in capture mode] 0 Operate in continuous mode1 Operate in one-Shot mode" "0,1" line.word 0x4 "ECAP_ECEINT,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers. The proper.." bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 Disable High Resolution Error as an Interrupt source1 Enable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 Disable Compare Equal as an Interrupt source1 Enable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 Disabled counter Overflow as an Interrupt source1 Enable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source1 Capture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 Disable Capture Event 3 as an Interrupt source1 Enable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 Disable Capture Event 2 as an Interrupt source1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 Disable Capture Event 1 as an Interrupt source1 Enable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "ECAP_ECFLG,Capture Interrupt Flag Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag 0 Indicates no event occurred1 Indicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the compare register value (ACMP)" "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) reached the period register value (APRD) and was reset." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0 Indicates no event occurred1 Indicates the counter (TSCTR) has made the transition from FFFFFFFF to 00000000" "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0 Indicates no event occurred1 Indicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0 Indicates no event occurred1 Indicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag 0 Indicates no event occurred1 Indicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "ECAP_ECCLR,Capture Interrupt Clear Register." bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 Writing a 0 has no effect. Always reads back a 01 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1" line.word 0x2 "ECAP_ECFRC,Capture Interrupt Force Register." bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 No effect. Always reads back a 0.1 Writing a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 No effect. Always reads back a 0.1 Sets the CEVT1 flag." "0,1" group.long 0x3C++0x3 line.long 0x0 "ECAP_ECAPSYNCINSEL,SYNC source select register." hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determine the source of SYNCIN signal. 0x0 : Reserved. 0x1: EPWM0.SYNCOUT 0x1: EPWM1.SYNCOUT 0x3: EPWM2.SYNCOUT ... 0x32: EPWM31.SYNCOUT 0x33-0x128: Reserved" group.long 0x80++0x3 line.long 0x0 "ECAP_MUNIT_COMMON_CTL,Control registers for monitoring unit {#}" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Reserved. 0x1 to 0x7F : Global load strobe from SOC level including EPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not effect signal monitoring. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and enabled when it is low" group.long 0xC0++0x7 line.long 0x0 "ECAP_MUNIT_1_CTL,Control registers for monitoring unit 1" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "ECAP_MUNIT_1_SHADOW_CTL,Shadow control registers for monitoring unit 1" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "ECAP_MUNIT_1_MIN,Min value for monitoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_1_MAX,Max value for monitoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_1_MIN_SHADOW,Shadow register for Min value of monitoring unit 1" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_1_MAX_SHADOW,Shadow register for Max value of monitoring unit 1" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "ECAP_MUNIT_1_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 1" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_1_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 1" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "ECAP_MUNIT_2_CTL,Control registers for monitoring unit 2" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 615 : Reserved [High Pulse width]" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "ECAP_MUNIT_2_SHADOW_CTL,Shadow control registers for monitoring unit 2" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "ECAP_MUNIT_2_MIN,Min value for monitoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "ECAP_MUNIT_2_MAX,Max value for monitoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "ECAP_MUNIT_2_MIN_SHADOW,Shadow register for Min value of monitoring unit 2" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "ECAP_MUNIT_2_MAX_SHADOW,Shadow register for Max value of monitoring unit 2" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "ECAP_MUNIT_2_DEBUG_RANGE_MIN,Observed Min value of check being enabled on minotoring unit 2" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "ECAP_MUNIT_2_DEBUG_RANGE_MAX,Observed Max value of check being enabled on minotoring unit 2" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree.end tree "ECC_AGGR" base ad:0x53010000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_AGGR_REVISION,The Revision Register contains the major and minor revisions for the ECC aggregator module. It does not support byte accesses." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial bus is complete" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Trigger a read operation to the specified read address that requires a serial bus access. In normal operation the trigger bit is only '1' for a single cycle and thus can not be read back." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x7 line.long 0x0 "ECC_AGGR_MISC_STATUS,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x4 "ECC_AGGR_ECC_WRAP_REVISION,Revision parameters." bitfld.long 0x4 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x4 28.--29. "BU,Business unit" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x4 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x4 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor version" group.long 0x14++0xF line.long 0x0 "ECC_AGGR_CONTROL,ECC Control Register." bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" bitfld.long 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x4 "ECC_AGGR_ERROR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_AGGR_ERROR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_AGGR_ERROR_STATUS1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the control register itself to clear this" "0,1" bitfld.long 0xC 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" bitfld.long 0xC 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGGR_ERROR_STATUS2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_AGGR_ERROR_STATUS3,ECC Error Status3 Register." bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" bitfld.long 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" rbitfld.long 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,Write of 1 to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. The bit is self clearing and will be read as a zero." "0,1" line.long 0x4 "ECC_AGGR_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 8. "MSS_L2SLV5_PEND,Interrupt Pending Status for mss_l2slv5_pend" "0,1" bitfld.long 0x4 7. "MSS_L2SLV4_PEND,Interrupt Pending Status for mss_l2slv4_pend" "0,1" bitfld.long 0x4 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1" newline bitfld.long 0x4 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1" bitfld.long 0x4 4. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1" bitfld.long 0x4 3. "MSS_L2SLV3_PEND,Interrupt Pending Status for mss_l2slv3_pend" "0,1" newline bitfld.long 0x4 2. "MSS_L2SLV2_PEND,Interrupt Pending Status for mss_l2slv2_pend" "0,1" bitfld.long 0x4 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1" bitfld.long 0x4 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "MSS_L2SLV5_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv5_pend" "0,1" bitfld.long 0x0 7. "MSS_L2SLV4_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv4_pend" "0,1" bitfld.long 0x0 6. "TPTC_A1_ENABLE_SETT,Interrupt Enable Set Register for tptc_a1_pend" "0,1" newline bitfld.long 0x0 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1" bitfld.long 0x0 4. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1" bitfld.long 0x0 3. "MSS_L2SLV3_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv3_pend" "0,1" newline bitfld.long 0x0 2. "MSS_L2SLV2_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv2_pend" "0,1" bitfld.long 0x0 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1" bitfld.long 0x0 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "MSS_L2SLV5_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv5_pend" "0,1" bitfld.long 0x0 7. "MSS_L2SLV4_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv4_pend" "0,1" bitfld.long 0x0 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1" newline bitfld.long 0x0 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1" bitfld.long 0x0 4. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1" bitfld.long 0x0 3. "MSS_L2SLV3_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv3_pend" "0,1" newline bitfld.long 0x0 2. "MSS_L2SLV2_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv2_pend" "0,1" bitfld.long 0x0 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1" bitfld.long 0x0 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,Write of 1 to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. The bit is self clearing and will be read as a zero." "0,1" line.long 0x4 "ECC_AGGR_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 8. "MSS_L2SLV5_PEND,Interrupt Pending Status for mss_l2slv5_pend" "0,1" bitfld.long 0x4 7. "MSS_L2SLV4_PEND,Interrupt Pending Status for mss_l2slv4_pend" "0,1" bitfld.long 0x4 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1" newline bitfld.long 0x4 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1" bitfld.long 0x4 4. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1" bitfld.long 0x4 3. "MSS_L2SLV3_PEND,Interrupt Pending Status for mss_l2slv3_pend" "0,1" newline bitfld.long 0x4 2. "MSS_L2SLV2_PEND,Interrupt Pending Status for mss_l2slv2_pend" "0,1" bitfld.long 0x4 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1" bitfld.long 0x4 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "MSS_L2SLV5_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv5_pend" "0,1" bitfld.long 0x0 7. "MSS_L2SLV4_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv4_pend" "0,1" bitfld.long 0x0 6. "TPTC_A1_ENABLE_SETT,Interrupt Enable Set Register for tptc_a1_pend" "0,1" newline bitfld.long 0x0 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1" bitfld.long 0x0 4. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1" bitfld.long 0x0 3. "MSS_L2SLV3_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv3_pend" "0,1" newline bitfld.long 0x0 2. "MSS_L2SLV2_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv2_pend" "0,1" bitfld.long 0x0 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1" bitfld.long 0x0 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "MSS_L2SLV5_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv5_pend" "0,1" bitfld.long 0x0 7. "MSS_L2SLV4_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv4_pend" "0,1" bitfld.long 0x0 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1" newline bitfld.long 0x0 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1" bitfld.long 0x0 4. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1" bitfld.long 0x0 3. "MSS_L2SLV3_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv3_pend" "0,1" newline bitfld.long 0x0 2. "MSS_L2SLV2_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv2_pend" "0,1" bitfld.long 0x0 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1" bitfld.long 0x0 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_AGGR_ENABLE_SET,Enable set register for aggregator interrupts." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_AGGR_ENABLE_CLR,Enable clear register for aggregator interrupts." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_AGGR_STATUS_SET,Status set register for aggregator interrupts." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout error has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_AGGR_STATUS_CLR,Status clear register for aggregator interrupts." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout error has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "EDMA" base ad:0x0 tree "EDMA0" tree "EDMA0_TPCC" base ad:0x52A00000 rgroup.long 0x0++0x7 line.long 0x0 "TPCC_PID,Peripheral ID Register" bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3" bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" line.long 0x4 "TPCC_CCCFG,CC Configuration Register" hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD" bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST =0 : No memory protection. MPEXIST =1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included" newline bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =0 : No Channel mapping. CHMAPEXIST =1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included" bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3" newline bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1" newline bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1" newline bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1" newline bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1" newline bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1" newline bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0x100++0x3 line.long 0x0 "TPCC_DCHMAPN,DMA Channel N mapping to PaRAM." hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD" hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PAENTRY points to the PaRAM Entry number for DMA Channel N" newline hexmask.long.byte 0x0 0.--4. 1. "RES100,RESERVE FIELD" group.long 0x200++0x3 line.long 0x0 "TPCC_QCHMAPN,QDMA Channel N Mapping Register" hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD" hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N." newline bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" group.long 0x240++0x3 line.long 0x0 "TPCC_DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1" bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1" bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1" bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1" bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1" bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1" bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1" bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1" bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x260++0x3 line.long 0x0 "TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1" bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1" bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1" bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1" bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1" bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1" bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1" bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1" bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x7 line.long 0x0 "TPCC_QUETCMAP,Queue to TC Mapping" hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD" bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1" bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" line.long 0x4 "TPCC_QUEPRI,Queue Priority" hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD" bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1" bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x7 line.long 0x0 "TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If.." bitfld.long 0x0 31. "E31,Event Missed #31" "0,1" bitfld.long 0x0 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x0 29. "E29,Event Missed #29" "0,1" bitfld.long 0x0 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x0 27. "E27,Event Missed #27" "0,1" bitfld.long 0x0 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x0 25. "E25,Event Missed #25" "0,1" bitfld.long 0x0 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x0 23. "E23,Event Missed #23" "0,1" bitfld.long 0x0 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x0 21. "E21,Event Missed #21" "0,1" bitfld.long 0x0 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x0 19. "E19,Event Missed #19" "0,1" bitfld.long 0x0 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x0 17. "E17,Event Missed #17" "0,1" bitfld.long 0x0 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x0 15. "E15,Event Missed #15" "0,1" bitfld.long 0x0 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x0 13. "E13,Event Missed #13" "0,1" bitfld.long 0x0 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x0 11. "E11,Event Missed #11" "0,1" bitfld.long 0x0 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x0 9. "E9,Event Missed #9" "0,1" bitfld.long 0x0 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x0 7. "E7,Event Missed #7" "0,1" bitfld.long 0x0 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x0 5. "E5,Event Missed #5" "0,1" bitfld.long 0x0 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x0 3. "E3,Event Missed #3" "0,1" bitfld.long 0x0 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x0 1. "E1,Event Missed #1" "0,1" bitfld.long 0x0 0. "E0,Event Missed #0" "0,1" line.long 0x4 "TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.." bitfld.long 0x4 31. "E63,Event Missed #63" "0,1" bitfld.long 0x4 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x4 29. "E61,Event Missed #61" "0,1" bitfld.long 0x4 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x4 27. "E59,Event Missed #59" "0,1" bitfld.long 0x4 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x4 25. "E57,Event Missed #57" "0,1" bitfld.long 0x4 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x4 23. "E55,Event Missed #55" "0,1" bitfld.long 0x4 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x4 21. "E53,Event Missed #53" "0,1" bitfld.long 0x4 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x4 19. "E51,Event Missed #51" "0,1" bitfld.long 0x4 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x4 17. "E49,Event Missed #49" "0,1" bitfld.long 0x4 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x4 15. "E47,Event Missed #47" "0,1" bitfld.long 0x4 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x4 13. "E45,Event Missed #45" "0,1" bitfld.long 0x4 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x4 11. "E43,Event Missed #43" "0,1" bitfld.long 0x4 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x4 9. "E41,Event Missed #41" "0,1" bitfld.long 0x4 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x4 7. "E39,Event Missed #39" "0,1" bitfld.long 0x4 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x4 5. "E37,Event Missed #37" "0,1" bitfld.long 0x4 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x4 3. "E35,Event Missed #35" "0,1" bitfld.long 0x4 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x4 1. "E33,Event Missed #33" "0,1" bitfld.long 0x4 0. "E32,Event Missed #32" "0,1" wgroup.long 0x308++0x7 line.long 0x0 "TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1" line.long 0x4 "TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x310++0x3 line.long 0x0 "TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including.." hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x0 6. "E6,Event Missed #6" "0,1" bitfld.long 0x0 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x0 4. "E4,Event Missed #4" "0,1" bitfld.long 0x0 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x0 2. "E2,Event Missed #2" "0,1" bitfld.long 0x0 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x0 0. "E0,Event Missed #0" "0,1" group.long 0x314++0x3 line.long 0x0 "TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x318++0x3 line.long 0x0 "TPCC_CCERR,CC Error Register" hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD" bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR =0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by Writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached" newline hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD" bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =0 : Watermark/threshold has not been exceeded. QTHRXCD7 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =0 : Watermark/threshold has not been exceeded. QTHRXCD6 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =0 : Watermark/threshold has not been exceeded. QTHRXCD5 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =0 : Watermark/threshold has not been exceeded. QTHRXCD4 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =0 : Watermark/threshold has not been exceeded. QTHRXCD3 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =0 : Watermark/threshold has not been exceeded. QTHRXCD2 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =0 : Watermark/threshold has not been exceeded. QTHRXCD1 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =0 : Watermark/threshold has not been exceeded. QTHRXCD0 =1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" group.long 0x31C++0x7 line.long 0x0 "TPCC_CCERRCLR,CC Error Clear Register" hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD" bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD" bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1" bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1" bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1" bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0,1" line.long 0x4 "TPCC_EEVAL,Error Eval Register" hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD" bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1" newline bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1" group.long 0x340++0x7 line.long 0x0 "TPCC_DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.." bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" line.long 0x4 "TPCC_DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.." bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x380++0x3 line.long 0x0 "TPCC_QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.." hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD" bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x3F line.long 0x0 "TPCC_QNE0,Event Queue Entry Diagram for Queue n - Entry 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD" bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x4 "TPCC_QNE1,Event Queue Entry Diagram for Queue n - Entry 1" hexmask.long.tbyte 0x4 8.--31. 1. "RES40,RESERVE FIELD" bitfld.long 0x4 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x8 "TPCC_QNE2,Event Queue Entry Diagram for Queue n - Entry 2" hexmask.long.tbyte 0x8 8.--31. 1. "RES41,RESERVE FIELD" bitfld.long 0x8 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0xC "TPCC_QNE3,Event Queue Entry Diagram for Queue n - Entry 3" hexmask.long.tbyte 0xC 8.--31. 1. "RES42,RESERVE FIELD" bitfld.long 0xC 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x10 "TPCC_QNE4,Event Queue Entry Diagram for Queue n - Entry 4" hexmask.long.tbyte 0x10 8.--31. 1. "RES43,RESERVE FIELD" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x10 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x14 "TPCC_QNE5,Event Queue Entry Diagram for Queue n - Entry 5" hexmask.long.tbyte 0x14 8.--31. 1. "RES44,RESERVE FIELD" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x14 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x18 "TPCC_QNE6,Event Queue Entry Diagram for Queue n - Entry 6" hexmask.long.tbyte 0x18 8.--31. 1. "RES45,RESERVE FIELD" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x18 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x1C "TPCC_QNE7,Event Queue Entry Diagram for Queue n - Entry 7" hexmask.long.tbyte 0x1C 8.--31. 1. "RES46,RESERVE FIELD" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x1C 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x20 "TPCC_QNE8,Event Queue Entry Diagram for Queue n - Entry 8" hexmask.long.tbyte 0x20 8.--31. 1. "RES47,RESERVE FIELD" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x20 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x24 "TPCC_QNE9,Event Queue Entry Diagram for Queue n - Entry 9" hexmask.long.tbyte 0x24 8.--31. 1. "RES48,RESERVE FIELD" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x28 "TPCC_QNE10,Event Queue Entry Diagram for Queue n - Entry 0" hexmask.long.tbyte 0x28 8.--31. 1. "RES49,RESERVE FIELD" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x2C "TPCC_QNE11,Event Queue Entry Diagram for Queue n - Entry 11" hexmask.long.tbyte 0x2C 8.--31. 1. "RES50,RESERVE FIELD" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x30 "TPCC_QNE12,Event Queue Entry Diagram for Queue n - Entry 12" hexmask.long.tbyte 0x30 8.--31. 1. "RES51,RESERVE FIELD" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x30 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x34 "TPCC_QNE13,Event Queue Entry Diagram for Queue n - Entry 13" hexmask.long.tbyte 0x34 8.--31. 1. "RES52,RESERVE FIELD" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x34 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x38 "TPCC_QNE14,Event Queue Entry Diagram for Queue n - Entry 14" hexmask.long.tbyte 0x38 8.--31. 1. "RES53,RESERVE FIELD" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x38 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." line.long 0x3C "TPCC_QNE15,Event Queue Entry Diagram for Queue n - Entry 15" hexmask.long.tbyte 0x3C 8.--31. 1. "RES54,RESERVE FIELD" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x3C 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events [ER/ESR/CER] ENUM will range between 0 and NUM_DMACH [up to 63]. For QDMA Channel events [QER] ENUM will range between 0 and.." rgroup.long 0x600++0x3 line.long 0x0 "TPCC_QSTATN,QSTATn Register Set" hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD" bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD =0 : Threshold specified by QWMTHR[A B].Qn has not been exceeded. THRXCD =1 : Threshold specified by QWMTHR[A B].Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR[A B],1: Threshold specified by QWMTHR[A B]" newline bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark [WM] was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 [empty] to 0x10.." newline bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 [empty] to 0x10 [full]" newline hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 [0th entry] to 0xF [15th entry]" group.long 0x620++0x3 line.long 0x0 "TPCC_QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values =.." hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD" hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value" newline rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value" rgroup.long 0x640++0x3 line.long 0x0 "TPCC_CCSTAT,CC Status Register" hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD" bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 =0 : No Evts are queued in Q7. QUEACTV7 =1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7" newline bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 =0 : No Evts are queued in Q6. QUEACTV6 =1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6" bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 =0 : No Evts are queued in Q5. QUEACTV5 =1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5" newline bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 =0 : No Evts are queued in Q4. QUEACTV4 =1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4" bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 =0 : No Evts are queued in Q3. QUEACTV3 =1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3" newline bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 =0 : No Evts are queued in Q2. QUEACTV2 =1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2" bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 =0 : No Evts are queued in Q1. QUEACTV1 =1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1" newline bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 =0 : No Evts are queued in Q0. QUEACTV0 =1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0" bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.." bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV =0 : Channel is idle. ACTV =1 : Channel is busy." "0: Channel is idle,1: Channel is busy" bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1" newline bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV =0 : Transfer Request processing/submission logic is inactive. TRACTV =1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.." bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV =0 : No enabled QDMA Events are active within the CC. QEVTACTV =1 : At least one enabled DMA Event [ER & EER ESR CER] is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event [ER & EER ESR.." newline bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV =0 : No enabled DMA Events are active within the CC. EVTACTV =1 : At least one enabled DMA Event [ER & EER ESR CER] is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event [ER & EER ESR.." group.long 0x700++0x3 line.long 0x0 "TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 31. "EN,AET Enable: EN =0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled" hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD" newline hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted [low]" rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1" newline bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE =0 : Event specified by STARTEVT applies to DMA Events [set by ER ESR or CER] TYPE =1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA..,1: Event specified by STARTEVT applies to QDMA Events" hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted [high]" rgroup.long 0x704++0x3 line.long 0x0 "TPCC_AETSTAT,Advanced Event Trigger Stat" hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD" bitfld.long 0x0 0. "STAT,AET Status: AETSTAT =0 : tpcc_aet is currently low. AETSTAT =1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high" group.long 0x708++0x3 line.long 0x0 "TPCC_AETCMD,AET Command" hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD" bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1" rgroup.long 0x1000++0x7 line.long 0x0 "TPCC_ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x1008++0xF line.long 0x0 "TPCC_ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC_ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect." bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect." bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x1018++0xF line.long 0x0 "TPCC_CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC_EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.." bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.." bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" wgroup.long 0x1028++0xF line.long 0x0 "TPCC_EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC_EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC_EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.." bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x7 line.long 0x0 "TPCC_SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x1040++0x7 line.long 0x0 "TPCC_SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x7 line.long 0x0 "TPCC_IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In.." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x1058++0xF line.long 0x0 "TPCC_IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x8 "TPCC_IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0xC "TPCC_IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.." bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1068++0x7 line.long 0x0 "TPCC_IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x1070++0x7 line.long 0x0 "TPCC_ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x3 line.long 0x0 "TPCC_IEVAL,Interrupt Eval Register" hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD" bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable [IERn] and status [IPRn]. CPU write of '0' has no effect." "0,1" newline bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts [IERn] are still pending [IPRn]. CPU write of '0' has no effect.." "0,1" rgroup.long 0x1080++0x7 line.long 0x0 "TPCC_QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register." hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.." hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" group.long 0x1088++0x7 line.long 0x0 "TPCC_QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.." hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.." hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x3 line.long 0x0 "TPCC_QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.." hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" group.long 0x1094++0x3 line.long 0x0 "TPCC_QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.." hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x7 line.long 0x0 "TPCC_ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x2008++0xF line.long 0x0 "TPCC_ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC_ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect." bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC_ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect." bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0xF line.long 0x0 "TPCC_CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC_EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note.." bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC_EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set.." bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" wgroup.long 0x2028++0xF line.long 0x0 "TPCC_EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC_EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC_EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.." bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x7 line.long 0x0 "TPCC_SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored.." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x2040++0x7 line.long 0x0 "TPCC_SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect." bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect." bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x7 line.long 0x0 "TPCC_IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In.." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x2058++0xF line.long 0x0 "TPCC_IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x8 "TPCC_IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0xC "TPCC_IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.." bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x7 line.long 0x0 "TPCC_IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x2070++0x7 line.long 0x0 "TPCC_ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC_ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x3 line.long 0x0 "TPCC_IEVAL_RN,Interrupt Eval Register" hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD" bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable [IERn] and status [IPRn]. CPU write of '0' has no effect." "0,1" newline bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts [IERn] are still pending [IPRn]. CPU write of '0' has no effect.." "0,1" rgroup.long 0x2080++0x7 line.long 0x0 "TPCC_QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register." hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1.." hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" group.long 0x2088++0x7 line.long 0x0 "TPCC_QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.." hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC_QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.." hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x3 line.long 0x0 "TPCC_QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event.." hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" group.long 0x2094++0x3 line.long 0x0 "TPCC_QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)." hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" group.long 0x4000++0x1F line.long 0x0 "TPCC_OPT,Options Parameter" rbitfld.long 0x0 31. "PRIV,Privilege level: privilege level [supervisor vs. user] for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via.." "0: User level privilege PRIV =,1: Supervisor level privilege" rbitfld.long 0x0 28.--30. "RES83,RESERVE FIELD" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "PRIVID,Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata.." bitfld.long 0x0 23. "ITCCHEN,Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled.1: Intermediate transfer complete chaining is enabled." "0: Intermediate transfer complete chaining is..,1: Intermediate transfer complete chaining is enabled" newline bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" bitfld.long 0x0 21. "ITCINTEN,Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled.1: Intermediate transfer complete interrupt is enabled [corresponding IER[TCC] bit must be set to 1 to generate interrupt]" "0: Intermediate transfer complete interrupt is..,1: Intermediate transfer complete interrupt is.." newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled [corresponding IER[TCC] bit must be set to 1 to generate interrupt]" "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled.." bitfld.long 0x0 19. "WIMODE,Backward compatibility mode: 0:Normal operation1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission [0 means 1 1 means 2 ... ] and forces ACNT to be treated as a word-count [left shifted by 2 by hardware to.." "0: Normal operation1 : WI Backwards Compatibility..,?" newline rbitfld.long 0x0 18. "RES84,RESERVE FIELD" "0,1" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER [bit CER[TCC]] for chaining or in IER [bit IER[TCC]] for interrupts." newline bitfld.long 0x0 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0:Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC.." "0: Normal Completion A transfer is considered..,1: Early Completion A transfer is considered.." bitfld.long 0x0 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 4.--7. 1. "RES85,RESERVE FIELD" bitfld.long 0x0 3. "STATIC,Static Entry: 0:Entry is updated as normal1:Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed." "0: Entry is updated as normal1:Entry is static..,?" newline bitfld.long 0x0 2. "SYNCDIM,Transfer Synchronization Dimension: 0:A-Sync Each event triggers the transfer of ACNT elements.1:AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements" "0: A-Sync Each event triggers the transfer of ACNT..,1: AB-Sync Each event triggers the transfer of BCNT.." bitfld.long 0x0 1. "DAM,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0:INCR Dst addressing within an array increments. Dst is not a FIFO.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." newline bitfld.long 0x0 0. "SAM,Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0:INCR Src addressing within an array increments. Source is not a FIFO.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPCC_SRC,Source Address" hexmask.long 0x4 0.--31. 1. "SRC,Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No.." line.long 0x8 "TPCC_ABCNT,A and B byte count" hexmask.long.word 0x8 16.--31. 1. "BCNT,BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a.." hexmask.long.word 0x8 0.--15. 1. "ACNT,ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is.." line.long 0xC "TPCC_DST,Destination Address" hexmask.long 0xC 0.--31. 1. "DST,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the.." line.long 0x10 "TPCC_BIDX,Register description is not available" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value [2's complement] used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value [2's complement] used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from.." line.long 0x14 "TPCC_LNK,Link and Reload parameters" hexmask.long.word 0x14 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on.." hexmask.long.word 0x14 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination [i.e. after count fields are decremented to '0'] with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the.." line.long 0x18 "TPCC_CIDX,Register description is not available" hexmask.long.word 0x18 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value [2's complement] used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of.." hexmask.long.word 0x18 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value [2's complement] used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current.." line.long 0x1C "TPCC_CCNT,C byte count" hexmask.long.word 0x1C 16.--31. 1. "RES86,RESERVE FIELD" hexmask.long.word 0x1C 0.--15. 1. "CCNT,CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 [64K-1.." tree.end tree "EDMA0_TPTC" base ad:0x52A40000 rgroup.long 0x0++0x7 line.long 0x0 "TPTC_PID,Peripheral ID Register." bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version" bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" line.long 0x4 "TPTC_TCCFG,TC Configuration Register." bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" newline bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x7 line.long 0x0 "TPTC_TCSTAT,TC Status Register." bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start PointerRepresents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3" bitfld.long 0x0 8. "ACTV,Channel ActiveChannel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.ACTV =0 : Channel is idle.ACTV =1 : Channel is busy." "0: Channel is idle,1: Channel is busy" newline bitfld.long 0x0 4.--6. "DSTACTV,Destination Active StateSpecifies the number of TRs that are resident in the Dst Register FIFO at a given instant.Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "WSACTV,Write Status ActiveWSACTV =0 : Write status is not pending. Write status has been received for all previously issued write commands.WSACTV =1 : Write Status is pending. Write status has not been received for all previously issued write commands." "0: Write status is not pending,1: Write Status is pending" newline bitfld.long 0x0 1. "SRCACTV,Source Active StateSRCACTV =0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].SRCACTV =1 : Source Active set is busy either performing.." "0: Source Active set is idle,1: Source Active set is busy either performing read.." bitfld.long 0x0 0. "PROGBUSY,Program Register Set BusyPROGBUSY =0 : Prog set idle and is available for programming.PROGBUSY =1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy" line.long 0x4 "TPTC_INTSTAT,Interrupt Status Register." bitfld.long 0x4 1. "TRDONE,TR Done Event Status:TRDONE =0 : Condition not detected.TRDONE =1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE.." "0: Condition not detected,1: Set when TC has completed a Transfer Request" bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status:PROGEMPTY =0 : Condition not detected.PROGEMPTY =1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.." group.long 0x108++0x3 line.long 0x0 "TPTC_INTEN,Interrupt Enable Register." bitfld.long 0x0 1. "TRDONE,TR Done Event Enable:INTEN.TRDONE =0 : TRDONE Event is disabled.INTEN.TRDONE =1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.." bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable:INTEN.PROGEMPTY =0 : PROGEMPTY Event is disabled.INTEN.PROGEMPTY =1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.." wgroup.long 0x10C++0x7 line.long 0x0 "TPTC_INTCLR,Interrupt Clear Register." bitfld.long 0x0 1. "TRDONE,TR Done Event Clear:INTCLR.TRDONE =0 : Writes of '0' have no effect.INTCLR.TRDONE =1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear:INTCLR.PROGEMPTY =0 : Writes of '0' have no effect.INTCLR.PROGEMPTY =1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" line.long 0x4 "TPTC_INTCMD,Interrupt Command Register." bitfld.long 0x4 1. "SET,Set TPTC interrupt:Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interruptWrite of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" rgroup.long 0x120++0x3 line.long 0x0 "TPTC_ERRSTAT,Error Status Register." bitfld.long 0x0 3. "MMRAERR,MMR Address Error:MMRAERR =0 : Condition not detected.MMRAERR =1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.." bitfld.long 0x0 2. "TRERR,TR Error:TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" newline bitfld.long 0x0 0. "BUSERR,Bus Error Event:BUSERR =0:Condition not detected.BUSERR =1:TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.." group.long 0x124++0x3 line.long 0x0 "TPTC_ERREN,Error Enable Register." bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR:ERREN.MMRAERR =0 : BUSERR is disabled.ERREN.MMRAERR =1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.." bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR:ERREN.TRERR =0 : BUSERR is disabled.ERREN.TRERR =1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.." newline bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR:ERREN.BUSERR =0 : BUSERR is disabled.ERREN.BUSERR =1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.." wgroup.long 0x128++0x3 line.long 0x0 "TPTC_ERRCLR,Error Clear Register." bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR:ERRCLR.MMRAERR =0 : Writes of '0' have no effect.ERRCLR.MMRAERR =1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR:ERRCLR.TRERR =0 : Writes of '0' have no effect.ERRCLR.TRERR =1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" newline bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR:ERRCLR.BUSERR =0 : Writes of '0' have no effect.ERRCLR.BUSERR =1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" rgroup.long 0x12C++0x3 line.long 0x0 "TPTC_ERRDET,Error Details Register." bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error." hexmask.long.byte 0x0 0.--3. 1. "STAT,Transaction Status:Stores the non-zero status/error code that was detected on the read status or write status bus.MS-bit effectively serves as the read vs. write error code.If read status and write status are returned on the same cycle then the TC.." wgroup.long 0x130++0x3 line.long 0x0 "TPTC_ERRCMD,Error Command Register." bitfld.long 0x0 1. "SET,Set TPTC error interrupt:Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interruptWrite of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" group.long 0x140++0x3 line.long 0x0 "TPTC_RDRATE,Read Rate Register." bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x0 "TPTC_POPT,Prog Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_PSRC,Prog Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set" line.long 0x8 "TPTC_PCNT,Prog Set Count." hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length." hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." line.long 0xC "TPTC_PDST,Prog Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set" line.long 0x10 "TPTC_PBIDX,Prog Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.." rgroup.long 0x214++0x3 line.long 0x0 "TPTC_PMPPRXY,Prog Set Mem Protect Proxy." bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x0 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.long 0x240++0x27 line.long 0x0 "TPTC_SAOPT,Src Actv Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_SASRC,Src Actv Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Source Active Register Set" line.long 0x8 "TPTC_SACNT,Src Actv Set A-Count." hexmask.long.tbyte 0x8 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." line.long 0xC "TPTC_SADST,Src Actv Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Source Active Register Set" line.long 0x10 "TPTC_SABIDX,Src Actv Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless.." line.long 0x14 "TPTC_SAMPPRXY,Src Actv Set Mem Protect Proxy." bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x14 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x14 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." line.long 0x18 "TPTC_SACNTRLD,Src Actv Set Cnt Reload." hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src.." line.long 0x1C "TPTC_SASRCBREF,Src Actv Set Src Addr B-Reference." hexmask.long 0x1C 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." line.long 0x20 "TPTC_SADSTBREF,Src Actv Set Dst Addr B-Reference." hexmask.long 0x20 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0." line.long 0x24 "TPTC_SABCNT,Src Actv Set B-Count." hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count:Number of arrays to be transferred where each array is ACNT in length.Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT.." rgroup.long 0x280++0x7 line.long 0x0 "TPTC_DFCNTRLD,Dst FIFO Set Cnt Reload." hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.." line.long 0x4 "TPTC_DFSRCBREF,Dst FIFO Set Src Addr B-Reference." hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." rgroup.long 0x300++0x1B line.long 0x0 "TPTC_DFOPT0,Dst FIFO Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_DFSRC0,Dst FIFO Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." line.long 0x8 "TPTC_DFACNT0,Dst FIFO Set A-Count." hexmask.long.tbyte 0x8 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." line.long 0xC "TPTC_DFDST0,Dst FIFO Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x10 "TPTC_DFBIDX0,Dst FIFO Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." line.long 0x14 "TPTC_DFMPPRXY0,Dst FIFO Set Mem Protect Proxy." bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x14 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x14 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." line.long 0x18 "TPTC_DFBCNT0,Dst FIFO Set B-Count." hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." rgroup.long 0x340++0x1B line.long 0x0 "TPTC_DFOPT1,Dst FIFO Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_DFSRC1,Dst FIFO Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." line.long 0x8 "TPTC_DFACNT1,Dst FIFO Set A-Count." hexmask.long.tbyte 0x8 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." line.long 0xC "TPTC_DFDST1,Dst FIFO Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x10 "TPTC_DFBIDX1,Dst FIFO Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." line.long 0x14 "TPTC_DFMPPRXY1,Dst FIFO Set Mem Protect Proxy." bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x14 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x14 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." line.long 0x18 "TPTC_DFBCNT1,Dst FIFO Set B-Count." hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." tree.end tree.end tree "EDMA1_TPTC" base ad:0x52A60000 rgroup.long 0x0++0x7 line.long 0x0 "TPTC_PID,Peripheral ID Register." bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version" bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" line.long 0x4 "TPTC_TCCFG,TC Configuration Register." bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" newline bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x7 line.long 0x0 "TPTC_TCSTAT,TC Status Register." bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start PointerRepresents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3" bitfld.long 0x0 8. "ACTV,Channel ActiveChannel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.ACTV =0 : Channel is idle.ACTV =1 : Channel is busy." "0: Channel is idle,1: Channel is busy" newline bitfld.long 0x0 4.--6. "DSTACTV,Destination Active StateSpecifies the number of TRs that are resident in the Dst Register FIFO at a given instant.Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "WSACTV,Write Status ActiveWSACTV =0 : Write status is not pending. Write status has been received for all previously issued write commands.WSACTV =1 : Write Status is pending. Write status has not been received for all previously issued write commands." "0: Write status is not pending,1: Write Status is pending" newline bitfld.long 0x0 1. "SRCACTV,Source Active StateSRCACTV =0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].SRCACTV =1 : Source Active set is busy either performing.." "0: Source Active set is idle,1: Source Active set is busy either performing read.." bitfld.long 0x0 0. "PROGBUSY,Program Register Set BusyPROGBUSY =0 : Prog set idle and is available for programming.PROGBUSY =1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy" line.long 0x4 "TPTC_INTSTAT,Interrupt Status Register." bitfld.long 0x4 1. "TRDONE,TR Done Event Status:TRDONE =0 : Condition not detected.TRDONE =1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE.." "0: Condition not detected,1: Set when TC has completed a Transfer Request" bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status:PROGEMPTY =0 : Condition not detected.PROGEMPTY =1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.." group.long 0x108++0x3 line.long 0x0 "TPTC_INTEN,Interrupt Enable Register." bitfld.long 0x0 1. "TRDONE,TR Done Event Enable:INTEN.TRDONE =0 : TRDONE Event is disabled.INTEN.TRDONE =1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.." bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable:INTEN.PROGEMPTY =0 : PROGEMPTY Event is disabled.INTEN.PROGEMPTY =1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.." wgroup.long 0x10C++0x7 line.long 0x0 "TPTC_INTCLR,Interrupt Clear Register." bitfld.long 0x0 1. "TRDONE,TR Done Event Clear:INTCLR.TRDONE =0 : Writes of '0' have no effect.INTCLR.TRDONE =1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear:INTCLR.PROGEMPTY =0 : Writes of '0' have no effect.INTCLR.PROGEMPTY =1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" line.long 0x4 "TPTC_INTCMD,Interrupt Command Register." bitfld.long 0x4 1. "SET,Set TPTC interrupt:Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interruptWrite of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" rgroup.long 0x120++0x3 line.long 0x0 "TPTC_ERRSTAT,Error Status Register." bitfld.long 0x0 3. "MMRAERR,MMR Address Error:MMRAERR =0 : Condition not detected.MMRAERR =1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.." bitfld.long 0x0 2. "TRERR,TR Error:TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" newline bitfld.long 0x0 0. "BUSERR,Bus Error Event:BUSERR =0:Condition not detected.BUSERR =1:TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.." group.long 0x124++0x3 line.long 0x0 "TPTC_ERREN,Error Enable Register." bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR:ERREN.MMRAERR =0 : BUSERR is disabled.ERREN.MMRAERR =1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.." bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR:ERREN.TRERR =0 : BUSERR is disabled.ERREN.TRERR =1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.." newline bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR:ERREN.BUSERR =0 : BUSERR is disabled.ERREN.BUSERR =1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.." wgroup.long 0x128++0x3 line.long 0x0 "TPTC_ERRCLR,Error Clear Register." bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR:ERRCLR.MMRAERR =0 : Writes of '0' have no effect.ERRCLR.MMRAERR =1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR:ERRCLR.TRERR =0 : Writes of '0' have no effect.ERRCLR.TRERR =1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" newline bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR:ERRCLR.BUSERR =0 : Writes of '0' have no effect.ERRCLR.BUSERR =1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" rgroup.long 0x12C++0x3 line.long 0x0 "TPTC_ERRDET,Error Details Register." bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error." hexmask.long.byte 0x0 0.--3. 1. "STAT,Transaction Status:Stores the non-zero status/error code that was detected on the read status or write status bus.MS-bit effectively serves as the read vs. write error code.If read status and write status are returned on the same cycle then the TC.." wgroup.long 0x130++0x3 line.long 0x0 "TPTC_ERRCMD,Error Command Register." bitfld.long 0x0 1. "SET,Set TPTC error interrupt:Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interruptWrite of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" group.long 0x140++0x3 line.long 0x0 "TPTC_RDRATE,Read Rate Register." bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x0 "TPTC_POPT,Prog Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_PSRC,Prog Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set" line.long 0x8 "TPTC_PCNT,Prog Set Count." hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length." hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." line.long 0xC "TPTC_PDST,Prog Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set" line.long 0x10 "TPTC_PBIDX,Prog Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.." rgroup.long 0x214++0x3 line.long 0x0 "TPTC_PMPPRXY,Prog Set Mem Protect Proxy." bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x0 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.long 0x240++0x27 line.long 0x0 "TPTC_SAOPT,Src Actv Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_SASRC,Src Actv Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Source Active Register Set" line.long 0x8 "TPTC_SACNT,Src Actv Set A-Count." hexmask.long.tbyte 0x8 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." line.long 0xC "TPTC_SADST,Src Actv Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Source Active Register Set" line.long 0x10 "TPTC_SABIDX,Src Actv Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless.." line.long 0x14 "TPTC_SAMPPRXY,Src Actv Set Mem Protect Proxy." bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x14 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x14 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." line.long 0x18 "TPTC_SACNTRLD,Src Actv Set Cnt Reload." hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src.." line.long 0x1C "TPTC_SASRCBREF,Src Actv Set Src Addr B-Reference." hexmask.long 0x1C 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." line.long 0x20 "TPTC_SADSTBREF,Src Actv Set Dst Addr B-Reference." hexmask.long 0x20 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0." line.long 0x24 "TPTC_SABCNT,Src Actv Set B-Count." hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count:Number of arrays to be transferred where each array is ACNT in length.Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT.." rgroup.long 0x280++0x7 line.long 0x0 "TPTC_DFCNTRLD,Dst FIFO Set Cnt Reload." hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.." line.long 0x4 "TPTC_DFSRCBREF,Dst FIFO Set Src Addr B-Reference." hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." rgroup.long 0x300++0x1B line.long 0x0 "TPTC_DFOPT0,Dst FIFO Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_DFSRC0,Dst FIFO Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." line.long 0x8 "TPTC_DFACNT0,Dst FIFO Set A-Count." hexmask.long.tbyte 0x8 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." line.long 0xC "TPTC_DFDST0,Dst FIFO Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x10 "TPTC_DFBIDX0,Dst FIFO Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." line.long 0x14 "TPTC_DFMPPRXY0,Dst FIFO Set Mem Protect Proxy." bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x14 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x14 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." line.long 0x18 "TPTC_DFBCNT0,Dst FIFO Set B-Count." hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." rgroup.long 0x340++0x1B line.long 0x0 "TPTC_DFOPT1,Dst FIFO Set Options." bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read [tptc_r_dbg_channel_id] and write [tptc_w_dbg_channel_id] command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0:Transfer complete chaining is disabled.1:Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0:Transfer complete interrupt is disabled.1:Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0:Priority 0 - Highest priority1:Priority 1 ...7:Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0:INCR Dst addressing within an array increments.1:FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0:INCR Src addressing within an array increments.1:FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC_DFSRC1,Dst FIFO Set Src Address." hexmask.long 0x4 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." line.long 0x8 "TPTC_DFACNT1,Dst FIFO Set A-Count." hexmask.long.tbyte 0x8 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." line.long 0xC "TPTC_DFDST1,Dst FIFO Set Dst Address." hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x10 "TPTC_DFBIDX1,Dst FIFO Set B-Dim Idx." hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." line.long 0x14 "TPTC_DFMPPRXY1,Dst FIFO Set Mem Protect Proxy." bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.long 0x14 8. "PRIV,Privilege Level:PRIV =0 : User level privilegePRIV =1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.long.byte 0x14 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." line.long 0x18 "TPTC_DFBCNT1,Dst FIFO Set B-Count." hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." tree.end tree "EDMA_TRIGXBAR_INTR" base ad:0x52E01000 rgroup.long 0x0++0x3 line.long 0x0 "EDMA_TRIGXBAR_INTR_PID,Identification register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,Rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "EDMA_TRIGXBAR_INTR_MUXCNTL_j,Interrupt mux control register." bitfld.long 0x0 16. "INT_ENABLE,Interrupt j Output Enable." "0,1" hexmask.long.word 0x0 0.--8. 1. "MUX_CNTL,Mux Control for Interrupt j." tree.end tree.end tree "EPWM" base ad:0x0 tree "EPWM00" tree "EPWM00_G0" base ad:0x50000000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM00_G1" base ad:0x50040000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM00_G2" base ad:0x50080000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM00_G3" base ad:0x500C0000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM01" tree "EPWM01_G0" base ad:0x50001000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM01_G1" base ad:0x50041000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM01_G2" base ad:0x50081000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM01_G3" base ad:0x500C1000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM02" tree "EPWM02_G0" base ad:0x50002000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM02_G1" base ad:0x50042000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM02_G2" base ad:0x50082000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM02_G3" base ad:0x500C2000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM03" tree "EPWM03_G0" base ad:0x50003000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM03_G1" base ad:0x50043000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM03_G2" base ad:0x50083000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM03_G3" base ad:0x500C3000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM04" tree "EPWM04_G0" base ad:0x50004000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM04_G1" base ad:0x50044000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM04_G2" base ad:0x50084000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM04_G3" base ad:0x500C4000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM05" tree "EPWM05_G0" base ad:0x50005000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM05_G1" base ad:0x50045000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM05_G2" base ad:0x50085000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM05_G3" base ad:0x500C5000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM06" tree "EPWM06_G0" base ad:0x50006000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM06_G1" base ad:0x50046000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM06_G2" base ad:0x50086000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM06_G3" base ad:0x500C6000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM07" tree "EPWM07_G0" base ad:0x50007000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM07_G1" base ad:0x50047000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM07_G2" base ad:0x50087000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM07_G3" base ad:0x500C7000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM08" tree "EPWM08_G0" base ad:0x50008000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM08_G1" base ad:0x50048000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM08_G2" base ad:0x50088000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM08_G3" base ad:0x500C8000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM09" tree "EPWM09_G0" base ad:0x50009000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM09_G1" base ad:0x50049000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM09_G2" base ad:0x50089000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM09_G3" base ad:0x500C9000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM10" tree "EPWM10_G0" base ad:0x5000A000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM10_G1" base ad:0x5004A000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM10_G2" base ad:0x5008A000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM10_G3" base ad:0x500CA000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM11" tree "EPWM11_G0" base ad:0x5000B000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM11_G1" base ad:0x5004B000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM11_G2" base ad:0x5008B000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM11_G3" base ad:0x500CB000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM12" tree "EPWM12_G0" base ad:0x5000C000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM12_G1" base ad:0x5004C000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM12_G2" base ad:0x5008C000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM12_G3" base ad:0x500CC000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM13" tree "EPWM13_G0" base ad:0x5000D000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM13_G1" base ad:0x5004D000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM13_G2" base ad:0x5008D000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM13_G3" base ad:0x500CD000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM14" tree "EPWM14_G0" base ad:0x5000E000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM14_G1" base ad:0x5004E000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM14_G2" base ad:0x5008E000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM14_G3" base ad:0x500CE000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM15" tree "EPWM15_G0" base ad:0x5000F000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM15_G1" base ad:0x5004F000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM15_G2" base ad:0x5008F000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM15_G3" base ad:0x500CF000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM16" tree "EPWM16_G0" base ad:0x50010000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM16_G1" base ad:0x50050000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM16_G2" base ad:0x50090000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM16_G3" base ad:0x500D0000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM17" tree "EPWM17_G0" base ad:0x50011000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM17_G1" base ad:0x50051000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM17_G2" base ad:0x50091000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM17_G3" base ad:0x500D1000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM18" tree "EPWM18_G0" base ad:0x50012000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM18_G1" base ad:0x50052000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM18_G2" base ad:0x50092000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM18_G3" base ad:0x500D2000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM19" tree "EPWM19_G0" base ad:0x50013000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM19_G1" base ad:0x50053000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM19_G2" base ad:0x50093000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM19_G3" base ad:0x500D3000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM20" tree "EPWM20_G0" base ad:0x50014000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM20_G1" base ad:0x50054000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM20_G2" base ad:0x50094000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM20_G3" base ad:0x500D4000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM21" tree "EPWM21_G0" base ad:0x50015000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM21_G1" base ad:0x50055000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM21_G2" base ad:0x50095000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM21_G3" base ad:0x500D5000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM22" tree "EPWM22_G0" base ad:0x50016000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM22_G1" base ad:0x50056000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM22_G2" base ad:0x50096000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM22_G3" base ad:0x500D6000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM23" tree "EPWM23_G0" base ad:0x50017000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM23_G1" base ad:0x50057000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM23_G2" base ad:0x50097000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM23_G3" base ad:0x500D7000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM24" tree "EPWM24_G0" base ad:0x50018000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM24_G1" base ad:0x50058000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM24_G2" base ad:0x50098000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM24_G3" base ad:0x500D8000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM25" tree "EPWM25_G0" base ad:0x50019000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM25_G1" base ad:0x50059000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM25_G2" base ad:0x50099000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM25_G3" base ad:0x500D9000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM26" tree "EPWM26_G0" base ad:0x5001A000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM26_G1" base ad:0x5005A000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM26_G2" base ad:0x5009A000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM26_G3" base ad:0x500DA000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM27" tree "EPWM27_G0" base ad:0x5001B000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM27_G1" base ad:0x5005B000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM27_G2" base ad:0x5009B000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM27_G3" base ad:0x500DB000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM28" tree "EPWM28_G0" base ad:0x5001C000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM28_G1" base ad:0x5005C000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM28_G2" base ad:0x5009C000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM28_G3" base ad:0x500DC000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM29" tree "EPWM29_G0" base ad:0x5001D000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM29_G1" base ad:0x5005D000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM29_G2" base ad:0x5009D000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM29_G3" base ad:0x500DD000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM30" tree "EPWM30_G0" base ad:0x5001E000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM30_G1" base ad:0x5005E000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM30_G2" base ad:0x5009E000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM30_G3" base ad:0x500DE000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM31" tree "EPWM31_G0" base ad:0x5001F000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM31_G1" base ad:0x5005F000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM31_G2" base ad:0x5009F000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM31_G3" base ad:0x500DF000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM_WLINK" tree "EPWM_WLINK_G0" base ad:0x50020000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM_WLINK_G1" base ad:0x50060000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM_WLINK_G2" base ad:0x500A0000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "EPWM_WLINK_G3" base ad:0x500E0000 group.word 0x0++0x3 line.word 0x0 "EPWM_TBCTL,Time Base Control Register." bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "EPWM_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "EPWM_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register." hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal0x0: Disabled0x01: EPWM0.SYNCOUT.0x10: EPWM15.SYNCOUT0x11:EPWM16.SYNCOUT.0x20: EPWM31.SYNCOUT0x21: Reserved.0x40: ECAP0.SYNCOUT.0x49: ECAP9.SYNCOUT0x4A: Reserved.0x4F: Reserved0x50:.." line.word 0x2 "EPWM_TBCTR,Time Base Counter Register." hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "EPWM_TBSTS,Time Base Status Register." bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0:Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1:Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0:Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1:Reading a 1 on this bit indicates that an external synchronization event has occurred [EPWMxSYNCI]." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0:Time-Base Counter is currently counting down. 1:Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "EPWM_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register." bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "EPWM_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "EPWM_CMPCTL,Counter Compare Control Register." bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "EPWM_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00:Shadow to Active Load of CMPD occurs according to LOADDMODE 01:Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPD.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00:Shadow to Active Load of CMPC occurs according to LOADCMODE 01:Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPC.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1:Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "EPWM_DBCTL,Dead-Band Generator Control Register." bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.' 1:Shadow mode. Operates as a double buffer. All writes.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path].." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "EPWM_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0:Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1:Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0 or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "EPWM_AQCTL,Action Qualifier Control Register." bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00:Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01:Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00:Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01:Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10:Shadow to Active Load of.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1:Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0:Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "EPWM_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register." hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000 DCAEVT1 0001 DCAEVT2 0010 DCBEVT1 0011 DCBEVT2 0100 TZ1 0101 TZ2 0110 TZ3 0111 EPWMxSYNCI 1000 DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "EPWM_PCCTL,PWM Chopper Control Register." bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000:Duty = 1/8 [12.5%] 001:Duty = 2/8 [25.0%] 010:Duty = 3/8 [37.5%] 011:Duty = 4/8 [50.0%] 100:Duty = 5/8 [62.5%] 101:Duty = 6/8 [75.0%] 110:Duty = 7/8 [87.5%] 111:Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000:Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001:Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010:Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011:Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100:Divide by 5 [2.50 MHz at.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011 4 x EPWMCLK / 8 wide [ = 320 ns at 100 MHz.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0:Disable [bypass] PWM chopping function 1:Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "EPWM_VCAPCTL,Valley Capture Control Register." bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" line.word 0x2 "EPWM_VCNTCFG,Valley Counter Config Register." rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This.." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "EPWM_HRCNFG,HRPWM Configuration Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output." "0: EPWMxA and EPWMxB outputs are unchanged,1: EPWMxA signal appears on EPWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: EPWMxB output is normal,1: EPWMxB output is inverted version of EPWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD].." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "EPWM_HRCNFG2,HRPWM Configuration 2 Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "EPWM_HRPCTL,High Resolution Period Control Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000:EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001:Reserved 010:Reserved 011:Reserved 100:CTR = CMPC Count direction Up 101:CTR = CMPC Count.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize EPWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple EPWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0:High resolution period feature disabled. In this mode the EPWM behaves as a Type 0 EPWM. 1:High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "EPWM_TRREM,HRPWM High Resolution Remainder Register This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "EPWM_GLDCTL,Global PWM Load Control Register." rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000:No events 001:1 event 010:2 events 011:3 events 100:4 events 101:5 events 110:6 events 111:7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000:Disable counter 001:Generate strobe on GLDCNT = 001 [1st event] 010:Generate strobe on GLDCNT = 010 [2nd.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0:One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1:One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000 Load on Counter = 0 [CNT_ZRO] 0001 Load on Counter = Period [PRD_EQ] 0010 Load on either Counter = 0 or Counter = Period 0011 Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0:Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1:When set all the shadow to active reload events.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "EPWM_GLDCFG,Global PWM Load Config Register ." bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0:Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1:Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "EPWM_EPWMXLINK,EPWMx Link Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's GLDCTL2 registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPD registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPC registers. 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2 5'b00011:.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPB_CMPBHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's CMPA_CMPAHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's TBPRD_TBPRDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." line.long 0x4 "EPWM_EPWMXLINK2,EPWMx Link 2 Register This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBFED_DBFEDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's DBRED_DBREDHR registers. 5'b00000: EPWM0 5'b00001: EPWM1.." group.word 0x7A++0x1 line.word 0x0 "EPWM_ETEST,EPWM Test Register." bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1:Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "EPWM_EPWMREV,EPWM Revision Register." hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "EPWM_HRPWMREV,High Resolution Revision Register." hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "EPWM_AQCTLA,Action Qualifier Control Register For Output A ." bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "EPWM_AQCTLA2,Additional Action Qualifier Control Register For Output A ." bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxA output low. 10:Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "EPWM_AQCTLB,Action Qualifier Control Register For Output B ." bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB output high. 11:Toggle.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "EPWM_AQCTLB2,Additional Action Qualifier Control Register For Output B ." bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00:Do nothing [action disabled] 01:Clear: force EPWMxB output low. 10:Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "EPWM_AQSFRC,Action Qualifier Software Force Register." bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00:Load on event counter equals zero 01:Load on event counter equals period 10:Load on event counter equals zero or counter equals period 11:Load immediately [the active register is directly.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0:Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It can.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00:Does nothing [action disabled] 01:Clear [low] 10:Set [high] 11:Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "EPWM_AQCSFRC,Action Qualifier Continuous S/W Force Register ." bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00:Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "EPWM_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "EPWM_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register ." hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "EPWM_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register ." hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "EPWM_DBFED,Dead-Band Generator Falling Edge Delay Count Register." hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "EPWM_TBPHS,Time Base Phase High." hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "EPWM_TBPRDHR,Time Base Period High Resolution Register ." hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "EPWM_TBPRD,Time Base Period Register ." hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "EPWM_TBPRDHRB,Calculation Result for EPWMxB." hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "EPWM_CMPA,Counter Compare A Register ." hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "EPWM_CMPB,Compare B Register ." hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "EPWM_CMPC,Counter Compare C Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare C' event. Shadowing.." group.word 0xE2++0x1 line.word 0x0 "EPWM_CMPD,Counter Compare D Register LINK feature access should always be 16-bit." hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare D' event. Shadowing.." group.word 0xE8++0x1 line.word 0x0 "EPWM_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0:Writing of 0 will be ignored. Always reads back a 0. 1:Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence.." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "EPWM_SWVDELVAL,Software Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "EPWM_TZSEL,Trip Zone Select Register ." bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0:Disable DCBEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCBEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0:Disable DCAEVT1 as one-shot-trip source for this EPWM module. 1:Enable DCAEVT1 as one-shot-trip source for this EPWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a one-shot trip source for this EPWM module 1:Enable TZ6 as a one-shot trip source for this EPWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a one-shot trip source for this EPWM module 1:Enable TZ5 as a one-shot trip source for this EPWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a one-shot trip source for this EPWM module 1:Enable TZ4 as a one-shot trip source for this EPWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a one-shot trip source for this EPWM module 1:Enable TZ3 as a one-shot trip source for this EPWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a one-shot trip source for this EPWM module 1:Enable TZ2 as a one-shot trip source for this EPWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a one-shot trip source for this EPWM module 1:Enable TZ1 as a one-shot trip source for this EPWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0:Disable DCBEVT2 as a CBC trip source for this EPWM module 1:Enable DCBEVT2 as a CBC trip source for this EPWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0:Disable DCAEVT2 as a CBC trip source for this EPWM module 1:Enable DCAEVT2 as a CBC trip source for this EPWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a CBC trip source for this EPWM module 1:Enable TZ6 as a CBC trip source for this EPWM module" "0: Disable TZ6 as a CBC trip source for this EPWM..,1: Enable TZ6 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 4. "CBC5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a CBC trip source for this EPWM module 1:Enable TZ5 as a CBC trip source for this EPWM module" "0: Disable TZ5 as a CBC trip source for this EPWM..,1: Enable TZ5 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 3. "CBC4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a CBC trip source for this EPWM module 1:Enable TZ4 as a CBC trip source for this EPWM module" "0: Disable TZ4 as a CBC trip source for this EPWM..,1: Enable TZ4 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 2. "CBC3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a CBC trip source for this EPWM module 1:Enable TZ3 as a CBC trip source for this EPWM module" "0: Disable TZ3 as a CBC trip source for this EPWM..,1: Enable TZ3 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 1. "CBC2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a CBC trip source for this EPWM module 1:Enable TZ2 as a CBC trip source for this EPWM module" "0: Disable TZ2 as a CBC trip source for this EPWM..,1: Enable TZ2 as a CBC trip source for this EPWM.." newline bitfld.word 0x0 0. "CBC1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a CBC trip source for this EPWM module 1:Enable TZ1 as a CBC trip source for this EPWM module" "0: Disable TZ1 as a CBC trip source for this EPWM..,1: Enable TZ1 as a CBC trip source for this EPWM.." line.word 0x2 "EPWM_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0:Disable CAPEVT as a one-shot trip source for this EPWM module 1:Enable CAPEVT as a one-shot trip source for this EPWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0:Disable CAPEVT as a CBC trip source for this EPWM module 1:Enable CAPEVT as a CBC trip source for this EPWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this EPWM.." line.word 0x4 "EPWM_TZDCSEL,Trip Zone Digital Comparator Select Register." bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000:Event disabled 001:DCBH = low DCBL = don't care 010:DCBH = high DCBL = don't care 011:DCBL = low DCBH = don't care 100:DCBL = high DCBH = don't care 101:DCBL = high DCBH = low 110:Reserved.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000:Event disabled 001:DCAH = low DCAL = don't care 010:DCAH = high DCAL = don't care 011:DCAL = low DCAH = don't care 100:DCAL = high DCAH = don't care 101:DCAL = high DCAH = low 110:Reserved.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "EPWM_TZCTL,Trip Zone Control Register." bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00:High-impedance [EPWMxB = High-impedance state] 01:Force EPWMxB to a high state. 10:Force EPWMxB to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00:High-impedance [EPWMxA = High-impedance state] 01:Force EPWMxA to a high state. 10:Force EPWMxA to a low state. 11:Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00:High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "EPWM_TZCTL2,Additional Trip Zone Control Register." bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0:Use trip action from TZCTL [legacy EPWM compatibility] 1:Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved 110:Reserved 111:Do.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "EPWM_TZCTLDCA,Trip Zone Control Register Digital Compare A ." bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000:HiZ [EPWMxA = HiZ state] 001:Forced Hi [EPWMxA = High state] 010:Forced Lo [EPWMxA = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "EPWM_TZCTLDCB,Trip Zone Control Register Digital Compare B ." bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000:HiZ [EPWMxB = HiZ state] 001:Forced Hi [EPWMxB = High state] 010:Forced Lo [EPWMxB = Lo state] 011:Toggle [Low -> High High -> Low] 100:Reserved 101:Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "EPWM_TZEINT,Trip Zone Enable Interrupt Register." bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0:Disabled 1:Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-Zone One-Shot Interrupt Enable 0:Disable one-shot interrupt generation 1:Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT VIM interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-Zone Cycle-by-Cycle Interrupt Enable 0:Disable cycle-by-cycle interrupt generation. 1:Enable interrupt generation A cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation A cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "EPWM_TZFLG,Trip Zone Flag Register." bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT VIM interrupt was.." line.word 0x2 "EPWM_TZCBCFLG,Trip Zone CBC Flag Register." bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT2. 1:Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT2. 1:Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC6. 1:Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC5. 1:Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC4. 1:Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC3. 1:Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC2. 1:Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on CBC1. 1:Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "EPWM_TZOSTFLG,Trip Zone OST Flag Register." bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCBEVT1. 1:Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on DCAEVT1. 1:Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST6. 1:Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST5. 1:Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST4. 1:Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST3. 1:Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST2. 1:Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0:Reading a 0 indicates that no trip has occurred on OST1. 1:Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "EPWM_TZCLR,Trip Zone Clear Register." bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit.." "0: Has no effect,1: Clears the trip-interrupt flag for this EPWM.." line.word 0x2 "EPWM_TZCBCCLR,Trip Zone CBC Clear Register." bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "EPWM_TZOSTCLR,Trip Zone OST Clear Register." bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "EPWM_TZFRC,Trip Zone Force Register." bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "EPWM_TZTRIPOUTSEL,Trip Zone Force Register." bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 7. "TZ6,Trip-Zone 6 [TZ6] Select 0:Disable TZ6 as a TRIPOUT source for this EPWM module 1:Enable TZ6 as a TRIPOUT source for this EPWM module" "0: Disable TZ6 as a TRIPOUT source for this EPWM..,1: Enable TZ6 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 6. "TZ5,Trip-Zone 5 [TZ5] Select 0:Disable TZ5 as a TRIPOUT source for this EPWM module 1:Enable TZ5 as a TRIPOUT source for this EPWM module" "0: Disable TZ5 as a TRIPOUT source for this EPWM..,1: Enable TZ5 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 5. "TZ4,Trip-Zone 4 [TZ4] Select 0:Disable TZ4 as a TRIPOUT source for this EPWM module 1:Enable TZ4 as a TRIPOUT source for this EPWM module" "0: Disable TZ4 as a TRIPOUT source for this EPWM..,1: Enable TZ4 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 4. "TZ3,Trip-Zone 3 [TZ3] Select 0:Disable TZ3 as a TRIPOUT source for this EPWM module 1:Enable TZ3 as a TRIPOUT source for this EPWM module" "0: Disable TZ3 as a TRIPOUT source for this EPWM..,1: Enable TZ3 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 3. "TZ2,Trip-Zone 2 [TZ2] Select 0:Disable TZ2 as a TRIPOUT source for this EPWM module 1:Enable TZ2 as a TRIPOUT source for this EPWM module" "0: Disable TZ2 as a TRIPOUT source for this EPWM..,1: Enable TZ2 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 2. "TZ1,Trip-Zone 1 [TZ1] Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." newline bitfld.word 0x0 0. "OST,OST Select 0:Disable TZ1 as a TRIPOUT source for this EPWM module 1:Enable TZ1 as a TRIPOUT source for this EPWM module" "0: Disable TZ1 as a TRIPOUT source for this EPWM..,1: Enable TZ1 as a TRIPOUT source for this EPWM.." group.word 0x148++0x1 line.word 0x0 "EPWM_ETSEL,Event Trigger Selection Register." bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0:Disable EPWMxSOCB. 1:Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000:Enable DCBEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0:Disable EPWMxSOCA. 1:Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000:Enable DCAEVT1.soc event 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR =.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0:Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable EPWM Interrupt [EPWMx_INT] Generation 0:Disable EPWMx_INT generation 1:Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,EPWM Interrupt [EPWMx_INT] Selection Options 000:Reserved 001:Enable event time-base counter equal to zero. [TBCTR = 0x00] 010:Enable event time-base counter equal to period [TBCTR = TBPRD] 011:Enable event time-base counter based on mixed events.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "EPWM_ETPS,Event Trigger Pre-Scale Register." rbitfld.word 0x0 14.--15. "SOCBCNT,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers.." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "EPWM_ETFLG,Event Trigger Flag Register." bitfld.word 0x0 3. "SOCB,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched EPWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0:Indicates no event occurred 1:Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched EPWM Interrupt [EPWMx_INT] Status Flag 0:Indicates no event occurred 1:Indicates that an EPWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an EPWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "EPWM_ETCLR,Event Trigger Clear Register." bitfld.word 0x0 3. "SOCB,EPWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,EPWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,EPWM Interrupt [EPWMx_INT] Flag Clear Bit 0:Writing a 0 has no effect. Always reads back a 0 1:Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "EPWM_ETFRC,Event Trigger Force Register." bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "EPWM_ETINTPS,Event-Trigger Interrupt Pre-Scale Register." hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000 Disable counter 0001 Generate interrupt on INTCNT = 1 [first event] 0010 Generate interrupt on.." group.word 0x160++0x1 line.word 0x0 "EPWM_ETSOCPS,Event-Trigger SOC Pre-Scale Register." hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCBCNT2 = 1 [first event] 0010 Generate interrupt on.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000 No events 0001 1 event 0010 2 events 0011 3 events 0100 4 events ... 1111 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000 Disable counter 0001 Generate interrupt on SOCACNT2 = 1 [first event] 0010 Generate interrupt on.." group.word 0x164++0x1 line.word 0x0 "EPWM_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register." bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0:Has no effect. 1:Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0:Has no effect. 1:This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "EPWM_ETCNTINIT,Event-Trigger Counter Initialization Register." hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an EPWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an EPWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "EPWM_ETINTMIXEN,Event-Trigger Mixed INT Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "EPWM_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection." bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "EPWM_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection." bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:DCBEVT1.soc event is not enabled 1:Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "EPWM_DCTRIPSEL,Digital Compare Trip Select Register." hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBLTRIPSEL register ORed.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCBHTRIPSEL register ORed.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCALTRIPSEL register ORed.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by DCAHTRIPSEL register ORed.." group.word 0x186++0x3 line.word 0x0 "EPWM_DCACTL,Digital Compare A Control Register." rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0:Source Is DCAEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0:Source Is DCAEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "EPWM_DCBCTL,Digital Compare B Control Register." rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0:Source Is DCBEVT2 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0:SYNC Generation Disabled 1:SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0:SOC Generation Disabled 1:SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0:Source is synchronized with EPWMCLK 1:Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0:Source Is DCBEVT1 Signal 1:Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "EPWM_DCFCTL,Digital Compare Filter Control Register." rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix" "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "EPWM_DCCAPCTL,Digital Compare Capture Control Register." bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "EPWM_DCFOFFSET,Digital Compare Filter Offset Register ." hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "EPWM_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register." hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "EPWM_DCFWINDOW,Digital Compare Filter Window Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "EPWM_DCFWINDOWCNT,Digital Compare Filter Window Counter Register." hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "EPWM_BLANKPULSEMIXSEL,Blanking window trigger pulse select register." bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "EPWM_DCCAPMIXSEL,Capture Event pulse select register." bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCC0PMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCC0PMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCC0PMIX]. 0:Period match event is not enabled 1:Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCC0PMIX]. 0:Zero match event is not enabled 1:Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "EPWM_DCCAP,Digital Compare Counter Capture Register ." hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCC0PCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "EPWM_DCAHTRIPSEL,Digital Compare AH Trip Select ." bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "EPWM_DCALTRIPSEL,Digital Compare AL Trip Select ." bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "EPWM_DCBHTRIPSEL,Digital Compare BH Trip Select ." bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "EPWM_DCBLTRIPSEL,Digital Compare BL Trip Select ." bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "EPWM_CAPCTL,Event Capture Control Register." bitfld.word 0x8 8. "FRCLOAD,0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCC0P" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic]" "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "EPWM_CAPGATETRIPSEL,Event Capture Gate Trip input select." bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "EPWM_CAPINTRIPSEL,Event Capture Trip input select." bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0:Trip Input 15 not selected as combinational ORed input 1:Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0:Trip Input 14 not selected as combinational ORed input 1:Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0:Trip Input 13 not selected as combinational ORed input 1:Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0:Trip Input 12 not selected as combinational ORed input 1:Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0:Trip Input 11 not selected as combinational ORed input 1:Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0:Trip Input 10 not selected as combinational ORed input 1:Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0:Trip Input 9 not selected as combinational ORed input 1:Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0:Trip Input 8 not selected as combinational ORed input 1:Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0:Trip Input 7 not selected as combinational ORed input 1:Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0:Trip Input 6 not selected as combinational ORed input 1:Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0:Trip Input 5 not selected as combinational ORed input 1:Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0:Trip Input 4 not selected as combinational ORed input 1:Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0:Trip Input 3 not selected as combinational ORed input 1:Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0:Trip Input 2 not selected as combinational ORed input 1:Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0:Trip Input 1 not selected as combinational ORed input 1:Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "EPWM_CAPTRIPSEL,Event Capture Signal Select." hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPGATETRIPSEL register ORed.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000 TRIPIN1 0001 TRIPIN2 0010 TRIPIN3 0011 TRIPIN4 ... 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input [all trip inputs selected by CAPINTRIPSEL register ORed.." group.long 0x1F4++0x3 line.long 0x0 "EPWM_EPWMLOCK,EPWM Lock Register." hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1:Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1:Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1:TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1:TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1:HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "EPWM_HWVDELVAL,Hardware Valley Mode Delay Register." hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "EPWM_VCNTVAL,Hardware Valley Counter Register." hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "EPWM_XCMPCTL1,XCMP Mode Control Register." hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "EPWM_XLOADCTL,XCMP Mode Load Control Register." rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0 1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers.." "0,1,2,3" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "EPWM_XLOAD,XCMP Mode Load Enable Register." bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence Writing '1' to this bit would allow load strobe.." "0,1" line.long 0x4 "EPWM_EPWMXLINKXLOAD,Link register across PWM modules." hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the EPWM module selected by the following bit selections results in a simultaneous write to the current EPWM module's XLOAD registers 5'b00000: EPWM0 5'b00001: EPWM1 5'b00010: EPWM2.." rgroup.long 0x420++0x3 line.long 0x0 "EPWM_XREGSHDW1STS,Shadow Buffer 1 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "EPWM_XREGSHDW2STS,Shadow Buffer 2 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "EPWM_XREGSHDW3STS,Shadow Buffer 3 Update Status Register." bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "EPWM_XCMP1_ACTIVE,Additional Compare 1 Active Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_ACTIVE,Additional Compare 2 Active Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_ACTIVE,Additional Compare 3 Active Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_ACTIVE,Additional Compare 4 Active Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_ACTIVE,Additional Compare 5 Active Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_ACTIVE,Additional Compare 6 Active Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_ACTIVE,Additional Compare 7 Active Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_ACTIVE,Additional Compare 8 Active Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_ACTIVE,Additional Time Base Period Active Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "EPWM_XAQCTLA_ACTIVE,AQCTLA Active Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "EPWM_XMINMAX_ACTIVE,XMINMAX Active Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "EPWM_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW1,CMPC Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW1,CMPD Shadow 1 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW1,XMINMAX Shadow 1 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "EPWM_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "EPWM_CMPC_SHDW2,CMPC Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "EPWM_CMPD_SHDW2,CMPD Shadow 2 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW2,XMINMAX Shadow 2 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "EPWM_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "EPWM_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register." hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "EPWM_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register." hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "EPWM_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register." hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "EPWM_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register." hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "EPWM_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register." hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "EPWM_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register." hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "EPWM_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register." hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "EPWM_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register." hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "EPWM_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register." bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "EPWM_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register." bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 2'b00 Do nothing [action disabled] 2'b01 Clear [low] 2'b10 Set [high] 2'b11 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "EPWM_CMPC_SHDW3,CMPC Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "EPWM_CMPD_SHDW3,CMPD Shadow 3 Register." hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "EPWM_XMINMAX_SHDW3,XMINMAX Shadow 3 Register." hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "EPWM_DECTL,DE control register." hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "EPWM_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPH000010 : Input-XBAR[1] is the source of TRIPH..100000 : Input-XBAR[31] is the source of TRIPH100001 : CMPSSA0 is the source of TRIPH100010 : CMPSSA1 is the source of TRIPH..101010 :.." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved000001 : Input-XBAR[0] is the source of TRIPL000010 : Input-XBAR[1] is the source of TRIPL..100000 : Input-XBAR[31] is the source of TRIPL100001 : CMPSSA0 is the source of TRIPL100010 : CMPSSA1 is the source of TRIPL..101010 :.." line.long 0x8 "EPWM_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "EPWM_DESTS,DE Status register." bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "EPWM_DEFRC,DE Status force register." bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "EPWM_DECLR,DE Status clear register." bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "EPWM_DEMONCNT,DE trip monitor counter." hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "EPWM_DEMONCTL,DE monitor mode control." bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0:DE Mode Monitor counter function is disabled 1:DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "EPWM_DEMONSTEP,DE monitor counter step." hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "EPWM_DEMONTHRES,DE monitor counter threshold." hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "EPWM_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "EPWM_MINDBDLY,Minimum dead band delay register." hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "EPWM_LUTCTLA,LUT control register on PWMA." bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "EPWM_LUTCTLB,LUT control register on PWMB." bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree.end tree "EQEP" base ad:0x0 tree "EQEP0" base ad:0x50270000 group.long 0x0++0xF line.long 0x0 "EQEP_QPOSCNT,Position Counter ." hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "EQEP_QPOSINIT,Position Counter Init ." hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter Init This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "EQEP_QPOSMAX,Maximum Position Count ." hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position Count This register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "EQEP_QPOSCMP,Position Compare ." hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "EQEP_QPOSILAT,Index Position Latch ." hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "EQEP_QPOSSLAT,Strobe Position Latch." hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "EQEP_QPOSLAT,Position Latch ." hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "EQEP_QUTMR,QEP Unit Timer ." hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "EQEP_QUPRD,QEP Unit Period ." hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit Period This register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "EQEP_QWDTMR,QEP Watchdog Timer ." hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "EQEP_QWDPRD,QEP Watchdog Period ." hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "EQEP_QDECCTL,Quadrature Decoder Control ." bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable 0 Disable position-compare sync output1 Enable position-compare sync output" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection 0 Index pin is used for sync output1 Strobe pin is used for sync output" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate 0 2x resolution: Count the rising/falling edge1 1x resolution: Count the rising edge only" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter 0 Quadrature-clock inputs are not swapped1 Quadrature-clock inputs are swapped" "0,1" bitfld.word 0x4 9. "IGATE,Index pulse gating option 0 Disable gating of Index pulse1 Gate the index pin with strobe" "0,1" bitfld.word 0x4 8. "QAP,QEPA input polarity 0 No effect1 Negates QEPA input" "0,1" newline bitfld.word 0x4 7. "QBP,QEPB input polarity 0 No effect1 Negates QEPB input" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity 0 No effect1 Negates QEPI input" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity 0 No effect1 Negates QEPS input" "0,1" bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices 1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "EQEP_QEPCTL,QEP Control ." bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode 0 QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h.." "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset 0 Position counter reset on an index event1 Position counter reset on the maximum position2 Position counter reset on the first index event3 Position counter reset on a unit time event" "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter 0 Does nothing (action disabled)1 Does nothing (action disabled)2 Initializes the position counter on rising edge of the QEPS signal3 Clockwise Direction: Initializes the.." "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count 0 Do nothing (action disabled)1 Do nothing (action disabled)2 Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT)3 Initializes the position.." "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter 0 Do nothing (action disabled)1 Initialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically" "0,1" bitfld.word 0x6 6. "SEL,Strobe event latch of position counter 0 The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in.." "0,1" bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker] 0 Reserved1 Latches position counter on rising edge of the index signal2 Latches position counter on falling edge of the index signal3 Software index.." "0,1,2,3" newline bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset 0 Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled .." "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode 0 Latch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register.1 Latch on unit time out." "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable 0 Disable eQEP unit timer1 Enable unit timer" "0,1" bitfld.word 0x6 0. "WDE,QEP watchdog enable 0 Disable the eQEP watchdog timer1 Enable the eQEP watchdog timer" "0,1" line.word 0x8 "EQEP_QCAPCTL,Qaudrature Capture Control ." bitfld.word 0x8 15. "CEN,Enable eQEP capture 0 eQEP capture unit is disabled1 eQEP capture unit is enabled" "0,1" bitfld.word 0x8 4.--6. "CCPS,EQEP capture timer clock prescaler 0 CAPCLK = SYSCLKOUT/11 CAPCLK = SYSCLKOUT/22 CAPCLK = SYSCLKOUT/43 CAPCLK = SYSCLKOUT/84 CAPCLK = SYSCLKOUT/165 CAPCLK = SYSCLKOUT/326 CAPCLK = SYSCLKOUT/647 CAPCLK =.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler 0 UPEVNT = QCLK/11 UPEVNT = QCLK/22 UPEVNT = QCLK/43 UPEVNT = QCLK/84 UPEVNT = QCLK/165 UPEVNT = QCLK/326 UPEVNT = QCLK/647 UPEVNT = QCLK/1288 UPEVNT = QCLK/2569 UPEVNT.." line.word 0xA "EQEP_QPOSCTL,Position Compare Control ." bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable 0 Shadow disabled load Immediate1 Shadow enabled" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load 0 Load on QPOSCNT = 01 Load when QPOSCNT = QPOSCMP" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output 0 Active HIGH pulse output1 Active LOW pulse output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable 0 Disable position compare unit1 Enable position compare unit" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width 0 1 * 4 * SYSCLKOUT cycles1 2 * 4 * SYSCLKOUT cycles4095 4096 * 4 * SYSCLKOUT cycles" line.word 0xC "EQEP_QEINT,QEP Interrupt Control ." bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" newline bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "EQEP_QFLG,QEP Interrupt Flag ." bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag 0 No interrupt generated1 Interrupt was generated" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag 0 No interrupt generated1 Set by eQEP unit timer period match" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag 0 No interrupt generated1 This bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag 0 No interrupt generated1 This bit is set after latching the QPOSCNT to QPOSSLAT" "0,1" bitfld.word 0x0 8. "PCM,EQEP compare match event interrupt flag 0 No interrupt generated1 This bit is set on position-compare match" "0,1" bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag 0 No interrupt generated1 This bit is set after transferring the shadow register value to the active position compare register" "0,1" bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag 0 No interrupt generated1 This bit is set on position counter overflow." "0,1" newline bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag 0 No interrupt generated1 This bit is set on position counter underflow." "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag 0 No interrupt generated1 Set by watchdog timeout" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag 0 No interrupt generated1 Interrupt was generated" "0,1" bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag 0 No interrupt generated1 Set on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag 0 No interrupt generated1 Position counter error" "0,1" bitfld.word 0x0 0. "INT,Global interrupt status flag 0 No interrupt generated1 Interrupt was generated" "0,1" group.word 0x34++0x9 line.word 0x0 "EQEP_QCLR,QEP Interrupt Clear ." bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" newline bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt clear flag 0 No effect1 Clears the interrupt flag" "0,1" line.word 0x2 "EQEP_QFRC,QEP Interrupt Force ." bitfld.word 0x2 12. "QMAE,Force QMA error interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt 0 No effect1 Force the interrupt" "0,1" newline bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt 0 No effect1 Force the interrupt" "0,1" line.word 0x4 "EQEP_QEPSTS,QEP Status ." bitfld.word 0x4 7. "UPEVNT,Unit position event flag 0 No unit position event detected1 Unit position event detected. Write 1 to clear" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index marker Status of the direction is latched on the first index event marker. 0 Counter-clockwise rotation (or reverse movement) on the first index event1 Clockwise rotation (or forward movement) on.." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag 0 Counter-clockwise rotation (or reverse movement)1 Clockwise rotation (or forward movement)" "0,1" rbitfld.word 0x4 4. "QDLF,EQEP direction latch flag 0 Counter-clockwise rotation (or reverse movement) on index event marker1 Clockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag 0 Overflow has not occurred.1 Overflow occurred in eQEP Capture timer (QEPCTMR). This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 2. "CDEF,Capture direction error flag 0 Capture direction error has not occurred.1 Direction change occurred between the capture position event. This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 1. "FIMF,First index marker flag 0 First index pulse has not occurred.1 Set by first occurrence of index pulse. This bit is cleared by writing a '1'." "0,1" newline rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event. 0 No error occurred during the last index transition1 Position counter error" "0,1" line.word 0x6 "EQEP_QCTMR,QEP Capture Timer ." hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "EQEP_QCPRD,QEP Capture Period ." hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "EQEP_QCTMRLAT,QEP Capture Latch ." hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event Reading the eQEP position counter." line.word 0x2 "EQEP_QCPRDLAT,QEP Capture Period Latch ." hexmask.word 0x2 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events viz. unit timeout event Reading the eQEP position counter." rgroup.long 0x60++0x3 line.long 0x0 "EQEP_REV,QEP Revision Number." bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x68++0x7 line.long 0x0 "EQEP_QMACTRL,QMA Control register." bitfld.long 0x0 0.--2. "MODE,Select Mode for QMA mode: 000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected 010 : QMA Mode-2 operation selected 011 : QMA Module is bypassed [reserved] 1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected,?,?,?,?,?,?" line.long 0x4 "EQEP_QEPSRCSEL,QEP Source Select Register." hexmask.long.byte 0x4 24.--28. 1. "QEPSSEL,QEP Strobe source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is.." hexmask.long.byte 0x4 16.--20. 1. "QEPISEL,QEP Index source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x4 8.--12. 1. "QEPBSEL,QEPB source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x4 0.--4. 1. "QEPASEL,QEPA source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." tree.end tree "EQEP1" base ad:0x50271000 group.long 0x0++0xF line.long 0x0 "EQEP_QPOSCNT,Position Counter ." hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "EQEP_QPOSINIT,Position Counter Init ." hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter Init This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "EQEP_QPOSMAX,Maximum Position Count ." hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position Count This register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "EQEP_QPOSCMP,Position Compare ." hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "EQEP_QPOSILAT,Index Position Latch ." hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "EQEP_QPOSSLAT,Strobe Position Latch." hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "EQEP_QPOSLAT,Position Latch ." hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "EQEP_QUTMR,QEP Unit Timer ." hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "EQEP_QUPRD,QEP Unit Period ." hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit Period This register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "EQEP_QWDTMR,QEP Watchdog Timer ." hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "EQEP_QWDPRD,QEP Watchdog Period ." hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "EQEP_QDECCTL,Quadrature Decoder Control ." bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable 0 Disable position-compare sync output1 Enable position-compare sync output" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection 0 Index pin is used for sync output1 Strobe pin is used for sync output" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate 0 2x resolution: Count the rising/falling edge1 1x resolution: Count the rising edge only" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter 0 Quadrature-clock inputs are not swapped1 Quadrature-clock inputs are swapped" "0,1" bitfld.word 0x4 9. "IGATE,Index pulse gating option 0 Disable gating of Index pulse1 Gate the index pin with strobe" "0,1" bitfld.word 0x4 8. "QAP,QEPA input polarity 0 No effect1 Negates QEPA input" "0,1" newline bitfld.word 0x4 7. "QBP,QEPB input polarity 0 No effect1 Negates QEPB input" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity 0 No effect1 Negates QEPI input" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity 0 No effect1 Negates QEPS input" "0,1" bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices 1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "EQEP_QEPCTL,QEP Control ." bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode 0 QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h.." "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset 0 Position counter reset on an index event1 Position counter reset on the maximum position2 Position counter reset on the first index event3 Position counter reset on a unit time event" "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter 0 Does nothing (action disabled)1 Does nothing (action disabled)2 Initializes the position counter on rising edge of the QEPS signal3 Clockwise Direction: Initializes the.." "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count 0 Do nothing (action disabled)1 Do nothing (action disabled)2 Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT)3 Initializes the position.." "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter 0 Do nothing (action disabled)1 Initialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically" "0,1" bitfld.word 0x6 6. "SEL,Strobe event latch of position counter 0 The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in.." "0,1" bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker] 0 Reserved1 Latches position counter on rising edge of the index signal2 Latches position counter on falling edge of the index signal3 Software index.." "0,1,2,3" newline bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset 0 Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled .." "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode 0 Latch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register.1 Latch on unit time out." "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable 0 Disable eQEP unit timer1 Enable unit timer" "0,1" bitfld.word 0x6 0. "WDE,QEP watchdog enable 0 Disable the eQEP watchdog timer1 Enable the eQEP watchdog timer" "0,1" line.word 0x8 "EQEP_QCAPCTL,Qaudrature Capture Control ." bitfld.word 0x8 15. "CEN,Enable eQEP capture 0 eQEP capture unit is disabled1 eQEP capture unit is enabled" "0,1" bitfld.word 0x8 4.--6. "CCPS,EQEP capture timer clock prescaler 0 CAPCLK = SYSCLKOUT/11 CAPCLK = SYSCLKOUT/22 CAPCLK = SYSCLKOUT/43 CAPCLK = SYSCLKOUT/84 CAPCLK = SYSCLKOUT/165 CAPCLK = SYSCLKOUT/326 CAPCLK = SYSCLKOUT/647 CAPCLK =.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler 0 UPEVNT = QCLK/11 UPEVNT = QCLK/22 UPEVNT = QCLK/43 UPEVNT = QCLK/84 UPEVNT = QCLK/165 UPEVNT = QCLK/326 UPEVNT = QCLK/647 UPEVNT = QCLK/1288 UPEVNT = QCLK/2569 UPEVNT.." line.word 0xA "EQEP_QPOSCTL,Position Compare Control ." bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable 0 Shadow disabled load Immediate1 Shadow enabled" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load 0 Load on QPOSCNT = 01 Load when QPOSCNT = QPOSCMP" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output 0 Active HIGH pulse output1 Active LOW pulse output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable 0 Disable position compare unit1 Enable position compare unit" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width 0 1 * 4 * SYSCLKOUT cycles1 2 * 4 * SYSCLKOUT cycles4095 4096 * 4 * SYSCLKOUT cycles" line.word 0xC "EQEP_QEINT,QEP Interrupt Control ." bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" newline bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "EQEP_QFLG,QEP Interrupt Flag ." bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag 0 No interrupt generated1 Interrupt was generated" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag 0 No interrupt generated1 Set by eQEP unit timer period match" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag 0 No interrupt generated1 This bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag 0 No interrupt generated1 This bit is set after latching the QPOSCNT to QPOSSLAT" "0,1" bitfld.word 0x0 8. "PCM,EQEP compare match event interrupt flag 0 No interrupt generated1 This bit is set on position-compare match" "0,1" bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag 0 No interrupt generated1 This bit is set after transferring the shadow register value to the active position compare register" "0,1" bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag 0 No interrupt generated1 This bit is set on position counter overflow." "0,1" newline bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag 0 No interrupt generated1 This bit is set on position counter underflow." "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag 0 No interrupt generated1 Set by watchdog timeout" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag 0 No interrupt generated1 Interrupt was generated" "0,1" bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag 0 No interrupt generated1 Set on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag 0 No interrupt generated1 Position counter error" "0,1" bitfld.word 0x0 0. "INT,Global interrupt status flag 0 No interrupt generated1 Interrupt was generated" "0,1" group.word 0x34++0x9 line.word 0x0 "EQEP_QCLR,QEP Interrupt Clear ." bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" newline bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt clear flag 0 No effect1 Clears the interrupt flag" "0,1" line.word 0x2 "EQEP_QFRC,QEP Interrupt Force ." bitfld.word 0x2 12. "QMAE,Force QMA error interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt 0 No effect1 Force the interrupt" "0,1" newline bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt 0 No effect1 Force the interrupt" "0,1" line.word 0x4 "EQEP_QEPSTS,QEP Status ." bitfld.word 0x4 7. "UPEVNT,Unit position event flag 0 No unit position event detected1 Unit position event detected. Write 1 to clear" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index marker Status of the direction is latched on the first index event marker. 0 Counter-clockwise rotation (or reverse movement) on the first index event1 Clockwise rotation (or forward movement) on.." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag 0 Counter-clockwise rotation (or reverse movement)1 Clockwise rotation (or forward movement)" "0,1" rbitfld.word 0x4 4. "QDLF,EQEP direction latch flag 0 Counter-clockwise rotation (or reverse movement) on index event marker1 Clockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag 0 Overflow has not occurred.1 Overflow occurred in eQEP Capture timer (QEPCTMR). This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 2. "CDEF,Capture direction error flag 0 Capture direction error has not occurred.1 Direction change occurred between the capture position event. This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 1. "FIMF,First index marker flag 0 First index pulse has not occurred.1 Set by first occurrence of index pulse. This bit is cleared by writing a '1'." "0,1" newline rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event. 0 No error occurred during the last index transition1 Position counter error" "0,1" line.word 0x6 "EQEP_QCTMR,QEP Capture Timer ." hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "EQEP_QCPRD,QEP Capture Period ." hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "EQEP_QCTMRLAT,QEP Capture Latch ." hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event Reading the eQEP position counter." line.word 0x2 "EQEP_QCPRDLAT,QEP Capture Period Latch ." hexmask.word 0x2 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events viz. unit timeout event Reading the eQEP position counter." rgroup.long 0x60++0x3 line.long 0x0 "EQEP_REV,QEP Revision Number." bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x68++0x7 line.long 0x0 "EQEP_QMACTRL,QMA Control register." bitfld.long 0x0 0.--2. "MODE,Select Mode for QMA mode: 000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected 010 : QMA Mode-2 operation selected 011 : QMA Module is bypassed [reserved] 1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected,?,?,?,?,?,?" line.long 0x4 "EQEP_QEPSRCSEL,QEP Source Select Register." hexmask.long.byte 0x4 24.--28. 1. "QEPSSEL,QEP Strobe source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is.." hexmask.long.byte 0x4 16.--20. 1. "QEPISEL,QEP Index source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x4 8.--12. 1. "QEPBSEL,QEPB source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x4 0.--4. 1. "QEPASEL,QEPA source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." tree.end tree "EQEP2" base ad:0x50272000 group.long 0x0++0xF line.long 0x0 "EQEP_QPOSCNT,Position Counter ." hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "EQEP_QPOSINIT,Position Counter Init ." hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter Init This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "EQEP_QPOSMAX,Maximum Position Count ." hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position Count This register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "EQEP_QPOSCMP,Position Compare ." hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "EQEP_QPOSILAT,Index Position Latch ." hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "EQEP_QPOSSLAT,Strobe Position Latch." hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "EQEP_QPOSLAT,Position Latch ." hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "EQEP_QUTMR,QEP Unit Timer ." hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "EQEP_QUPRD,QEP Unit Period ." hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit Period This register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "EQEP_QWDTMR,QEP Watchdog Timer ." hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "EQEP_QWDPRD,QEP Watchdog Period ." hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "EQEP_QDECCTL,Quadrature Decoder Control ." bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable 0 Disable position-compare sync output1 Enable position-compare sync output" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection 0 Index pin is used for sync output1 Strobe pin is used for sync output" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate 0 2x resolution: Count the rising/falling edge1 1x resolution: Count the rising edge only" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter 0 Quadrature-clock inputs are not swapped1 Quadrature-clock inputs are swapped" "0,1" bitfld.word 0x4 9. "IGATE,Index pulse gating option 0 Disable gating of Index pulse1 Gate the index pin with strobe" "0,1" bitfld.word 0x4 8. "QAP,QEPA input polarity 0 No effect1 Negates QEPA input" "0,1" newline bitfld.word 0x4 7. "QBP,QEPB input polarity 0 No effect1 Negates QEPB input" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity 0 No effect1 Negates QEPI input" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity 0 No effect1 Negates QEPS input" "0,1" bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices 1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "EQEP_QEPCTL,QEP Control ." bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode 0 QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h.." "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset 0 Position counter reset on an index event1 Position counter reset on the maximum position2 Position counter reset on the first index event3 Position counter reset on a unit time event" "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter 0 Does nothing (action disabled)1 Does nothing (action disabled)2 Initializes the position counter on rising edge of the QEPS signal3 Clockwise Direction: Initializes the.." "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count 0 Do nothing (action disabled)1 Do nothing (action disabled)2 Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT)3 Initializes the position.." "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter 0 Do nothing (action disabled)1 Initialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically" "0,1" bitfld.word 0x6 6. "SEL,Strobe event latch of position counter 0 The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in.." "0,1" bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker] 0 Reserved1 Latches position counter on rising edge of the index signal2 Latches position counter on falling edge of the index signal3 Software index.." "0,1,2,3" newline bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset 0 Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled .." "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode 0 Latch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register.1 Latch on unit time out." "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable 0 Disable eQEP unit timer1 Enable unit timer" "0,1" bitfld.word 0x6 0. "WDE,QEP watchdog enable 0 Disable the eQEP watchdog timer1 Enable the eQEP watchdog timer" "0,1" line.word 0x8 "EQEP_QCAPCTL,Qaudrature Capture Control ." bitfld.word 0x8 15. "CEN,Enable eQEP capture 0 eQEP capture unit is disabled1 eQEP capture unit is enabled" "0,1" bitfld.word 0x8 4.--6. "CCPS,EQEP capture timer clock prescaler 0 CAPCLK = SYSCLKOUT/11 CAPCLK = SYSCLKOUT/22 CAPCLK = SYSCLKOUT/43 CAPCLK = SYSCLKOUT/84 CAPCLK = SYSCLKOUT/165 CAPCLK = SYSCLKOUT/326 CAPCLK = SYSCLKOUT/647 CAPCLK =.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler 0 UPEVNT = QCLK/11 UPEVNT = QCLK/22 UPEVNT = QCLK/43 UPEVNT = QCLK/84 UPEVNT = QCLK/165 UPEVNT = QCLK/326 UPEVNT = QCLK/647 UPEVNT = QCLK/1288 UPEVNT = QCLK/2569 UPEVNT.." line.word 0xA "EQEP_QPOSCTL,Position Compare Control ." bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable 0 Shadow disabled load Immediate1 Shadow enabled" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load 0 Load on QPOSCNT = 01 Load when QPOSCNT = QPOSCMP" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output 0 Active HIGH pulse output1 Active LOW pulse output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable 0 Disable position compare unit1 Enable position compare unit" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width 0 1 * 4 * SYSCLKOUT cycles1 2 * 4 * SYSCLKOUT cycles4095 4096 * 4 * SYSCLKOUT cycles" line.word 0xC "EQEP_QEINT,QEP Interrupt Control ." bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" newline bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable 0 Interrupt is disabled1 Interrupt is enabled" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "EQEP_QFLG,QEP Interrupt Flag ." bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag 0 No interrupt generated1 Interrupt was generated" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag 0 No interrupt generated1 Set by eQEP unit timer period match" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag 0 No interrupt generated1 This bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag 0 No interrupt generated1 This bit is set after latching the QPOSCNT to QPOSSLAT" "0,1" bitfld.word 0x0 8. "PCM,EQEP compare match event interrupt flag 0 No interrupt generated1 This bit is set on position-compare match" "0,1" bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag 0 No interrupt generated1 This bit is set after transferring the shadow register value to the active position compare register" "0,1" bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag 0 No interrupt generated1 This bit is set on position counter overflow." "0,1" newline bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag 0 No interrupt generated1 This bit is set on position counter underflow." "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag 0 No interrupt generated1 Set by watchdog timeout" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag 0 No interrupt generated1 Interrupt was generated" "0,1" bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag 0 No interrupt generated1 Set on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag 0 No interrupt generated1 Position counter error" "0,1" bitfld.word 0x0 0. "INT,Global interrupt status flag 0 No interrupt generated1 Interrupt was generated" "0,1" group.word 0x34++0x9 line.word 0x0 "EQEP_QCLR,QEP Interrupt Clear ." bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" newline bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag 0 No effect1 Clears the interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt clear flag 0 No effect1 Clears the interrupt flag" "0,1" line.word 0x2 "EQEP_QFRC,QEP Interrupt Force ." bitfld.word 0x2 12. "QMAE,Force QMA error interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt 0 No effect1 Force the interrupt" "0,1" newline bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt 0 No effect1 Force the interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt 0 No effect1 Force the interrupt" "0,1" line.word 0x4 "EQEP_QEPSTS,QEP Status ." bitfld.word 0x4 7. "UPEVNT,Unit position event flag 0 No unit position event detected1 Unit position event detected. Write 1 to clear" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index marker Status of the direction is latched on the first index event marker. 0 Counter-clockwise rotation (or reverse movement) on the first index event1 Clockwise rotation (or forward movement) on.." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag 0 Counter-clockwise rotation (or reverse movement)1 Clockwise rotation (or forward movement)" "0,1" rbitfld.word 0x4 4. "QDLF,EQEP direction latch flag 0 Counter-clockwise rotation (or reverse movement) on index event marker1 Clockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag 0 Overflow has not occurred.1 Overflow occurred in eQEP Capture timer (QEPCTMR). This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 2. "CDEF,Capture direction error flag 0 Capture direction error has not occurred.1 Direction change occurred between the capture position event. This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 1. "FIMF,First index marker flag 0 First index pulse has not occurred.1 Set by first occurrence of index pulse. This bit is cleared by writing a '1'." "0,1" newline rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event. 0 No error occurred during the last index transition1 Position counter error" "0,1" line.word 0x6 "EQEP_QCTMR,QEP Capture Timer ." hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "EQEP_QCPRD,QEP Capture Period ." hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "EQEP_QCTMRLAT,QEP Capture Latch ." hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event Reading the eQEP position counter." line.word 0x2 "EQEP_QCPRDLAT,QEP Capture Period Latch ." hexmask.word 0x2 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events viz. unit timeout event Reading the eQEP position counter." rgroup.long 0x60++0x3 line.long 0x0 "EQEP_REV,QEP Revision Number." bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x68++0x7 line.long 0x0 "EQEP_QMACTRL,QMA Control register." bitfld.long 0x0 0.--2. "MODE,Select Mode for QMA mode: 000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected 010 : QMA Mode-2 operation selected 011 : QMA Module is bypassed [reserved] 1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected,?,?,?,?,?,?" line.long 0x4 "EQEP_QEPSRCSEL,QEP Source Select Register." hexmask.long.byte 0x4 24.--28. 1. "QEPSSEL,QEP Strobe source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is.." hexmask.long.byte 0x4 16.--20. 1. "QEPISEL,QEP Index source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x4 8.--12. 1. "QEPBSEL,QEPB source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x4 0.--4. 1. "QEPASEL,QEPA source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." tree.end tree.end tree "ESM0" base ad:0x52D00000 rgroup.long 0x0++0x7 line.long 0x0 "ESM_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "ESM_INFO,The Info Register gives the configuration Inforrmation of this ESM." bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" bitfld.long 0x4 30. "CRIT_INTR,Indicates if the critical priority interrupt output has asserted" "0,1" bitfld.long 0x4 29. "CRIT_DELAY_CNTR_ERROR,Indicates if a bit error has occurred in the critical priority interrupt delay counter" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" group.long 0x8++0x3 line.long 0x0 "ESM_EN,The Global Enable Register has the master interrupt mask." hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable. This field is a global mask to all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that after a warm reset software may observe the state of the ESM.." wgroup.long 0xC++0x3 line.long 0x0 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables." hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset. Write: 0xF: Clear all raw status and enable bits All others no.." group.long 0x10++0xF line.long 0x0 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors." hexmask.long.byte 0x0 0.--3. 1. "STS,This is the raw status for config errors. This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset and not by warm reset. A global soft reset will set this field to 0 Read: 0x0:Inactive.." line.long 0x4 "ESM_ERR_STS,Config Error Enable and Clear Register." hexmask.long.byte 0x4 0.--3. 1. "MSK,This is the masked status/clear for config errors. This is the masked status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. Read: 0x0:Inactive.." line.long 0x8 "ESM_ERR_EN_SET,Config Error Enable Set Register." hexmask.long.byte 0x8 0.--3. 1. "MSK,This is the mask enable set for config errors. This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the global_enable are set then then interrupt is unmasked. This field is only reset by a Power-On-Reset.." line.long 0xC "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register." hexmask.long.byte 0xC 0.--3. 1. "MSK,This is the mask enable clear for config errors. This is the mask clear for errors in the configuration for Group N. If the corresponding bit and the global_enable are set then then interrupt is unmasked. This field is only reset by a Power-On-Reset.." rgroup.long 0x20++0xF line.long 0x0 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt." hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt. Indicates what the highest priority Low Priority interrupt caused by a pulse number is. The lowest event has the highest priority. i.e. if Global Events 0 1 2 3 and 4 are.." hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt. Indicates what the highest priority Low Priority interrupt caused by a level number is. The lowest event has the highest priority. i.e. if Global Events 0 1 2 3 and 4 are.." line.long 0x4 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt." hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt. Indicates what the highest priority High Priority interrupt caused by a pulse number is. The lowest event has the highest priority. i.e. if Global Events 0 1 2 3 and 4 are.." hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt. Indicates what the highest priority High Priority interrupt caused by a level number is. The lowest event has the highest priority. i.e. if Global Events 0 1 2 3 and 4 are.." line.long 0x8 "ESM_LOW,Shows which groups have oustanding low priority interrupts." hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors. Indicates which Event Groups have one or more Low Priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc (bit N is for Event Group N)." line.long 0xC "ESM_HI,Shows which groups have oustanding high priority interrupts." hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors. Indicates which Event Groups have one or more High Priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc (bit N is for Event Group N)." wgroup.long 0x30++0x3 line.long 0x0 "ESM_EOI,End of Interrupt Register." hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a reevaluation of interrupts. If when the vector is written there are still pending interrupts a new pulse will be generated. 0x0: Configuration Error.." group.long 0x40++0x3 line.long 0x0 "ESM_PIN_CTRL,This register controls the error_pin_n output." hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable. PWM mode enable. This field should only be modified when the ESM is disabled from the Global Enable register. This field is only reset by a Power-On-Reset (not warm reset). 0x0:Error output pin is a level 0xF:Error output pin is a PWM.." hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key. This field controls behavior of the Error Pin. Note during reset the field is 0x0 but the Error Pin is asserted (active low). Immediately after reset the Error Pin de-asserts. This field is only reset by a Power-On-Reset (not warm.." rgroup.long 0x44++0x7 line.long 0x0 "ESM_PIN_STS,This register reflects the status of the error_pin_n output." bitfld.long 0x0 0. "VAL,Value of the error_pin_n. This field indicates the status of the Error Pin as looped back from the I/O. This field reflects the state of SAFETY_ERRORn I/O. 0x1 - De-Asserted 0x0 - Asserted Note while in reset the error pin is actually active.." "0,1" line.long 0x4 "ESM_PIN_CNTR,This register shows the current value of the error pin counter." hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value. This field indicates the current value of the Time Interval Counter. Register is reloaded to the counter preload value on entry to the ESM_ERROR state from ESM_IDLE and counts down by one per clock cycle. Once the counter has.." group.long 0x4C++0x3 line.long 0x0 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value. This is the value that will be loaded in to the counter field of the Error Pin Counter Value Register whenever the ESM enters the ESM_ERROR state from ESM_IDLE. This field is only reset by a Power-On-Reset (not warm reset)." rgroup.long 0x50++0x3 line.long 0x0 "ESM_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value. This field indicates the current value of the PWM High Time Interval Counter. The reset value is the 24'h0186A0. If pwm_en is set to PWM mode then this register is enabled. This register is reloaded to the PWM high.." group.long 0x54++0x3 line.long 0x0 "ESM_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value. This is the value that will be loaded in to the counter field of the Error Pin PWM High Counter Value Register whenever the error output pin toggles high. This field is only reset by a Power-On-Reset (not warm reset). A.." rgroup.long 0x58++0x3 line.long 0x0 "ESM_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value. This field indicates the current value of the PWM Low Time Interval Counter. The reset value is the 24'h0186A0. If pwm_en is set to PWM mode then this register is enabled. This register is reloaded to the PWM low.." group.long 0x5C++0x3 line.long 0x0 "ESM_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value. This is the value that will be loaded in to the counter field of the Error Pin PWM Low Counter Value Register whenever the error output pin toggles low. This field is only reset by a Power-On-Reset (not warm reset). A global.." rgroup.long 0x60++0x3 line.long 0x0 "ESM_CRIT_DELAY_CNTR,This register shows the current value of the Critical Priority Interrupt Delay Counter." hexmask.long 0x0 0.--31. 1. "COUNT,Current Counter Value. This field indicates the current value of the Critical Priority Interrupt Delay Counter. The reset value is the crit_delay_cntr_ipcfg tie-off. This register decrements by 1 each cycle there is an input error event asserted.." group.long 0x64++0x3 line.long 0x0 "ESM_CRIT_DELAY_CNTR_PRE,This register contains the value that is loaded into the Critical Priority Interrupt Delay Counter." hexmask.long 0x0 0.--31. 1. "COUNT,Counter Pre-Load Value. This is the value that will be loaded in to the counter field of the Critical Priority Interrupt Delay Counter Value Register whenever there are no critical priority interrupt influential events left and the register count.." group.long 0x400++0x1B line.long 0x0 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_RAW_j,Raw Status/Set Register for Group A Errors" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status/set for errors Group A. This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc). For Level events the raw status is the event.." line.long 0x4 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_STS_j,Error Enable and Clear Register" hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status/clear for errors in Group A. This is the masked status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc...). This field is only reset by a.." line.long 0x8 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_INTR_EN_SET_j,Level Error Enable Set Register" hexmask.long 0x8 0.--31. 1. "MSK,This is the mask enable set for errors in Group A. This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit. If the corresponding bit and the global_enable are set then then interrupt is.." line.long 0xC "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register" hexmask.long 0xC 0.--31. 1. "MSK,This is the mask enable clear for errors in Group A. This field is used to disable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit. If the corresponding bit and the global_enable are set then then interrupt is.." line.long 0x10 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_INT_PRIO_j,Level Error Interrupt Priority register" hexmask.long 0x10 0.--31. 1. "MSK,This is interrupt priority for errors in Group A. This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit. This field is only reset by a.." line.long 0x14 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_PIN_EN_SET_j,Error Pin Enabled Set register" hexmask.long 0x14 0.--31. 1. "MSK,This is the error pin influence enable set for errors in Group A. This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit. This field is only reset by a Power-On-Reset (not warm reset). A global.." line.long 0x18 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_PIN_EN_CLR_j,Error Pin Enabled Clear register" hexmask.long 0x18 0.--31. 1. "MSK,This is the error pin influence enable clear for errors in Group A. This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit. This field is only reset by a Power-On-Reset (not warm reset). A.." group.long 0x800++0x7 line.long 0x0 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_EXT_GRP_CRIT_EN_SET_j,Level Critical Priority Interrupt Enabled Clear register" hexmask.long 0x0 0.--31. 1. "MSK,This is the critical priority interrupt influence enable set for errors in Group A. This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1.." line.long 0x4 "ESM_PCR_GENERATED_MEMORY_MAP_ERR_EXT_GRP_CRIT_EN_CLR_j,Level Critical Priority Interrupt Enabled Clear register" hexmask.long 0x4 0.--31. 1. "MSK,This is the critical priority interrupt influence enable clear for errors in Group A. This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1.." tree.end tree "FSI" base ad:0x0 tree "FSI_RX0" base ad:0x50290000 group.word 0x0++0x1 line.word 0x0 "FSI_RX_CFG_RX_MASTER_CTRL_ALTC,Receive master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h[R/W] = Data filtering is disabled. 1h[R/W] = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs [RXCLK RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Controller Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles." "0,1" group.word 0x8++0x1 line.word 0x0 "FSI_RX_CFG_RX_OPER_CTRL,Receive operation control register." bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h[R/W] = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h[R/W] = Data will be received on one data line RXD0. 1h[R/W] = Data will be received on two data lines RXD0 and RXD1. 2h3h[R/W] = Reserved" "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_INFO,Receive frame control register." hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b[R/W] = A ping frame was received 0100b[R/W] = A DATA_1_WORD frame was received [16-bit data]. 0101b[R/W] = A DATA_2_WORD frame was received.." line.word 0x2 "FSI_RX_CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register." hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "FSI_RX_CFG_RX_DMA_CTRL,Receive DMA event control register." bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_STS_ALT1,Receive event and error status flag register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched data.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No data frame has been received. 1h[R] = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No ping frame has been received. 1h[R] = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No error frame has been received. 1h[R] = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No frame has been successfully received. 1h[R] = A frame.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid end-of-frame has not been received. 1h[R].." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid frame type has not been received. 1h[R] = Invalid frame.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by Writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Frame watchdog timeout has not occured. 1h[R] = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Ping watchdog timeout has not occured. 1h[R] = Ping watchdog.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC." hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_CLR_ALT1,Receive event and error clear register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_EVT_FRC_ALT1,Receive event and error flag force register." bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] = Writing.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register." hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_STS,Receive buffer pointer status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "FSI_RX_CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register." bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference." hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count." hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_WD_CTRL,Receive ping watchdog control register." bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_TAG,Receive ping tag register." hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_REF,Receive ping watchdog counter reference." hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_CNT,Receive pingwatchdog current count." hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "FSI_RX_CFG_RX_INT1_CTRL_ALT1,Receive interrupt control register for RX_INT1." bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W].." "0,1" line.word 0x2 "FSI_RX_CFG_RX_INT2_CTRL_ALT1,Receive interrupt control register for RX_INT2." bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A buffer.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W].." "0,1" line.word 0x4 "FSI_RX_CFG_RX_LOCK_CTRL,Receive lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_DATA,Receive ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_VAL,Receive ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register." hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_LOG,Receive ECC log and status register." bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h[R] Multiple Bit Errors.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h[R] No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register." bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "FSI_RX_CFG_RX_PING_TAG_CMP,Receive ping tag compare register." bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_0,Receive Trigger Control register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_WIDTH_0,Receive Trigger Wdith register 0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width[in SYSCLK cycles] of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "FSI_RX_CFG_RX_DLYLINE_CTRL,Receive delay line control register." hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_1,Receive Trigger Control register 1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_CTRL_2,Receive Trigger Control register 2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "FSI_RX_CFG_RX_TRIG_CTRL_3,Receive Trigger Control register 3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "FSI_RX_CFG_RX_VIS_1,Receive debug visibility register 1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "FSI_RX_CFG_RX_UDATA_FILTER,Receive User Data Filter Control register." hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_BASE_j,Base address for receive data buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI_RX1" base ad:0x50291000 group.word 0x0++0x1 line.word 0x0 "FSI_RX_CFG_RX_MASTER_CTRL_ALTC,Receive master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h[R/W] = Data filtering is disabled. 1h[R/W] = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs [RXCLK RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Controller Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles." "0,1" group.word 0x8++0x1 line.word 0x0 "FSI_RX_CFG_RX_OPER_CTRL,Receive operation control register." bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h[R/W] = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h[R/W] = Data will be received on one data line RXD0. 1h[R/W] = Data will be received on two data lines RXD0 and RXD1. 2h3h[R/W] = Reserved" "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_INFO,Receive frame control register." hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b[R/W] = A ping frame was received 0100b[R/W] = A DATA_1_WORD frame was received [16-bit data]. 0101b[R/W] = A DATA_2_WORD frame was received.." line.word 0x2 "FSI_RX_CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register." hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "FSI_RX_CFG_RX_DMA_CTRL,Receive DMA event control register." bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_STS_ALT1,Receive event and error status flag register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched data.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No data frame has been received. 1h[R] = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No ping frame has been received. 1h[R] = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No error frame has been received. 1h[R] = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No frame has been successfully received. 1h[R] = A frame.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid end-of-frame has not been received. 1h[R].." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid frame type has not been received. 1h[R] = Invalid frame.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by Writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Frame watchdog timeout has not occured. 1h[R] = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Ping watchdog timeout has not occured. 1h[R] = Ping watchdog.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC." hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_CLR_ALT1,Receive event and error clear register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_EVT_FRC_ALT1,Receive event and error flag force register." bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] = Writing.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register." hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_STS,Receive buffer pointer status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "FSI_RX_CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register." bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference." hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count." hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_WD_CTRL,Receive ping watchdog control register." bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_TAG,Receive ping tag register." hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_REF,Receive ping watchdog counter reference." hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_CNT,Receive pingwatchdog current count." hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "FSI_RX_CFG_RX_INT1_CTRL_ALT1,Receive interrupt control register for RX_INT1." bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W].." "0,1" line.word 0x2 "FSI_RX_CFG_RX_INT2_CTRL_ALT1,Receive interrupt control register for RX_INT2." bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A buffer.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W].." "0,1" line.word 0x4 "FSI_RX_CFG_RX_LOCK_CTRL,Receive lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_DATA,Receive ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_VAL,Receive ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register." hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_LOG,Receive ECC log and status register." bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h[R] Multiple Bit Errors.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h[R] No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register." bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "FSI_RX_CFG_RX_PING_TAG_CMP,Receive ping tag compare register." bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_0,Receive Trigger Control register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_WIDTH_0,Receive Trigger Wdith register 0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width[in SYSCLK cycles] of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "FSI_RX_CFG_RX_DLYLINE_CTRL,Receive delay line control register." hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_1,Receive Trigger Control register 1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_CTRL_2,Receive Trigger Control register 2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "FSI_RX_CFG_RX_TRIG_CTRL_3,Receive Trigger Control register 3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "FSI_RX_CFG_RX_VIS_1,Receive debug visibility register 1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "FSI_RX_CFG_RX_UDATA_FILTER,Receive User Data Filter Control register." hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_BASE_j,Base address for receive data buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI_RX2" base ad:0x502B0000 group.word 0x0++0x1 line.word 0x0 "FSI_RX_CFG_RX_MASTER_CTRL_ALTC,Receive master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h[R/W] = Data filtering is disabled. 1h[R/W] = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs [RXCLK RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Controller Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles." "0,1" group.word 0x8++0x1 line.word 0x0 "FSI_RX_CFG_RX_OPER_CTRL,Receive operation control register." bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h[R/W] = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h[R/W] = Data will be received on one data line RXD0. 1h[R/W] = Data will be received on two data lines RXD0 and RXD1. 2h3h[R/W] = Reserved" "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_INFO,Receive frame control register." hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b[R/W] = A ping frame was received 0100b[R/W] = A DATA_1_WORD frame was received [16-bit data]. 0101b[R/W] = A DATA_2_WORD frame was received.." line.word 0x2 "FSI_RX_CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register." hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "FSI_RX_CFG_RX_DMA_CTRL,Receive DMA event control register." bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_STS_ALT1,Receive event and error status flag register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched data.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No data frame has been received. 1h[R] = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No ping frame has been received. 1h[R] = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No error frame has been received. 1h[R] = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No frame has been successfully received. 1h[R] = A frame.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid end-of-frame has not been received. 1h[R].." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid frame type has not been received. 1h[R] = Invalid frame.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by Writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Frame watchdog timeout has not occured. 1h[R] = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Ping watchdog timeout has not occured. 1h[R] = Ping watchdog.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC." hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_CLR_ALT1,Receive event and error clear register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_EVT_FRC_ALT1,Receive event and error flag force register." bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] = Writing.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register." hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_STS,Receive buffer pointer status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "FSI_RX_CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register." bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference." hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count." hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_WD_CTRL,Receive ping watchdog control register." bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_TAG,Receive ping tag register." hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_REF,Receive ping watchdog counter reference." hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_CNT,Receive pingwatchdog current count." hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "FSI_RX_CFG_RX_INT1_CTRL_ALT1,Receive interrupt control register for RX_INT1." bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W].." "0,1" line.word 0x2 "FSI_RX_CFG_RX_INT2_CTRL_ALT1,Receive interrupt control register for RX_INT2." bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A buffer.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W].." "0,1" line.word 0x4 "FSI_RX_CFG_RX_LOCK_CTRL,Receive lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_DATA,Receive ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_VAL,Receive ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register." hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_LOG,Receive ECC log and status register." bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h[R] Multiple Bit Errors.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h[R] No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register." bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "FSI_RX_CFG_RX_PING_TAG_CMP,Receive ping tag compare register." bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_0,Receive Trigger Control register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_WIDTH_0,Receive Trigger Wdith register 0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width[in SYSCLK cycles] of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "FSI_RX_CFG_RX_DLYLINE_CTRL,Receive delay line control register." hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_1,Receive Trigger Control register 1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_CTRL_2,Receive Trigger Control register 2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "FSI_RX_CFG_RX_TRIG_CTRL_3,Receive Trigger Control register 3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "FSI_RX_CFG_RX_VIS_1,Receive debug visibility register 1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "FSI_RX_CFG_RX_UDATA_FILTER,Receive User Data Filter Control register." hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_BASE_j,Base address for receive data buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI_RX3" base ad:0x502B1000 group.word 0x0++0x1 line.word 0x0 "FSI_RX_CFG_RX_MASTER_CTRL_ALTC,Receive master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h[R/W] = Data filtering is disabled. 1h[R/W] = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs [RXCLK RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Controller Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles." "0,1" group.word 0x8++0x1 line.word 0x0 "FSI_RX_CFG_RX_OPER_CTRL,Receive operation control register." bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h[R/W] = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h[R/W] = Data will be received on one data line RXD0. 1h[R/W] = Data will be received on two data lines RXD0 and RXD1. 2h3h[R/W] = Reserved" "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_INFO,Receive frame control register." hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b[R/W] = A ping frame was received 0100b[R/W] = A DATA_1_WORD frame was received [16-bit data]. 0101b[R/W] = A DATA_2_WORD frame was received.." line.word 0x2 "FSI_RX_CFG_RX_FRAME_TAG_UDATA,Receive frame tag and user data register." hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "FSI_RX_CFG_RX_DMA_CTRL,Receive DMA event control register." bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_STS_ALT1,Receive event and error status flag register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched data.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No data frame has been received. 1h[R] = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No ping frame has been received. 1h[R] = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No error frame has been received. 1h[R] = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No frame has been successfully received. 1h[R] = A frame.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid end-of-frame has not been received. 1h[R].." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid frame type has not been received. 1h[R] = Invalid frame.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by Writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Frame watchdog timeout has not occured. 1h[R] = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Ping watchdog timeout has not occured. 1h[R] = Ping watchdog.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_CRC_INFO,Receive CRC info of received and computed CRC." hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "FSI_RX_CFG_RX_EVT_CLR_ALT1,Receive event and error clear register." bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "FSI_RX_CFG_RX_EVT_FRC_ALT1,Receive event and error flag force register." bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W].." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] = Writing.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_LOAD,Receive buffer pointer load register." hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_PTR_STS,Receive buffer pointer status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "FSI_RX_CFG_RX_FRAME_WD_CTRL,Receive frame watchdog control register." bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF].." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_REF,Receive frame watchdog counter reference." hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "FSI_RX_CFG_RX_FRAME_WD_CNT,Receive frame watchdog current count." hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_WD_CTRL,Receive ping watchdog control register." bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "FSI_RX_CFG_RX_PING_TAG,Receive ping tag register." hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "ZERO,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0] application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_REF,Receive ping watchdog counter reference." hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "FSI_RX_CFG_RX_PING_WD_CNT,Receive pingwatchdog current count." hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "FSI_RX_CFG_RX_INT1_CTRL_ALT1,Receive interrupt control register for RX_INT1." bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] =.." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W].." "0,1" line.word 0x2 "FSI_RX_CFG_RX_INT2_CTRL_ALT1,Receive interrupt control register for RX_INT2." bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] =.." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A buffer.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W] = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT2. 1h[R/W].." "0,1" line.word 0x4 "FSI_RX_CFG_RX_LOCK_CTRL,Receive lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_DATA,Receive ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_VAL,Receive ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "FSI_RX_CFG_RX_ECC_SEC_DATA,Receive ECC corrected data register." hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "FSI_RX_CFG_RX_ECC_LOG,Receive ECC log and status register." bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h[R] Multiple Bit Errors.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h[R] No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "FSI_RX_CFG_RX_FRAME_TAG_CMP,Receive frame tag compare register." bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "FSI_RX_CFG_RX_PING_TAG_CMP,Receive ping tag compare register." bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_0,Receive Trigger Control register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_WIDTH_0,Receive Trigger Wdith register 0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width[in SYSCLK cycles] of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "FSI_RX_CFG_RX_DLYLINE_CTRL,Receive delay line control register." hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "FSI_RX_CFG_RX_TRIG_CTRL_1,Receive Trigger Control register 1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "FSI_RX_CFG_RX_TRIG_CTRL_2,Receive Trigger Control register 2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "FSI_RX_CFG_RX_TRIG_CTRL_3,Receive Trigger Control register 3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux Select Value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "FSI_RX_CFG_RX_VIS_1,Receive debug visibility register 1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "FSI_RX_CFG_RX_UDATA_FILTER,Receive User Data Filter Control register." hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "FSI_RX_CFG_RX_BUF_BASE_j,Base address for receive data buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI_TX0" base ad:0x50280000 group.word 0x0++0x1 line.word 0x0 "FSI_TX_CFG_TX_MASTER_CTRL,Transmit master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h[R/W] = Transmitter core is not in reset and can transmit frames. 1h[R/W] = Transmitter core is held.." "0,1" group.word 0x4++0x1 line.word 0x0 "FSI_TX_CFG_TX_CLK_CTRL,Transmit clock control register." hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h[R/W] = Reserved 1h[R/W] = Input clock /1 2h[R/W] = Input clock /2.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h[R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h[R/W] = The.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h[R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h[R/W] = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2,Transmit operation control register low." bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-target TDM operation. 0h[R/W] Transmit TDM Mode is not enabled. 1h[R/W] Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h[R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h[R/W] = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h[R/W] = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h[R/W] = The ping counter will.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h[R/W] = The transmitted CRC value is computed by hardware. 1h[R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h[R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h[R/W] = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h[R/W] = FSI is in normal mode of operation. 1h[R/W] = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h[R/W] = Data will be transmitted on one data line [TXD0] 1h[R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of.." "0,1,2,3" line.word 0x2 "FSI_TX_CFG_TX_OPER_CTRL_HI_ALT1,Transmit operation control register high." hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h[R/W] = Trigger 1 is the source. 01h[R/W] = Trigger 2 is the source. 02h[R/W] = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "FSI_TX_CFG_TX_FRAME_CTRL,Transmit frame control register." bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b[R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b[R/W] = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "FSI_TX_CFG_TX_FRAME_TAG_UDATA,Transmit frame tag and user data register." hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "FSI_TX_CFG_TX_BUF_PTR_LOAD,Transmit buffer pointer control load register." hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_PTR_STS,Transmit buffer pointer control status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "FSI_TX_CFG_TX_PING_CTRL_ALT1,Transmit ping control register." hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h[R/W] = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h[R/W] = External triggers will not be used to generate ping frames. 1h[R/W] = The selected external trigger [selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h[R/W] = The ping timer is disabled and will not generate ping frames. 1h[R/W] = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h[R/W] = Clear the CNT_RST. 1h[R/W] = The.." "0,1" line.word 0x2 "FSI_TX_CFG_TX_PING_TAG,Transmit ping tag register." hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_REF,Transmit ping timeout counter reference." hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_CNT,Transmit ping timeout current count." hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value [TX_PING_TO_REF] at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "FSI_TX_CFG_TX_INT_CTRL,Transmit interrupt event control register." bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "FSI_TX_CFG_TX_DMA_CTRL,Transmit DMA event control register." bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the completion of a transmitted frame." "0,1" line.word 0x4 "FSI_TX_CFG_TX_LOCK_CTRL,Transmit lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "FSI_TX_CFG_TX_EVT_STS,Transmit event and error status flag register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by Writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Overrun has not occured. 1h[R] = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Underrun has not occured. 1h[R] = Buffer Underrun has occured." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "FSI_TX_CFG_TX_EVT_CLR,Transmit event and error clear register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "FSI_TX_CFG_TX_EVT_FRC,Transmit event and error flag force register." bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" group.word 0x30++0x1 line.word 0x0 "FSI_TX_CFG_TX_USER_CRC,Transmit user-defined CRC register." hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "FSI_TX_CFG_TX_ECC_DATA,Transmit ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "FSI_TX_CFG_TX_ECC_VAL,Transmit ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "FSI_TX_CFG_TX_DLYLINE_CTRL,Transmit delay Line control register." hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD1 path. TXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD0 path. TXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_BASE_j,Base address for transmit buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree "FSI_TX1" base ad:0x50281000 group.word 0x0++0x1 line.word 0x0 "FSI_TX_CFG_TX_MASTER_CTRL,Transmit master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h[R/W] = Transmitter core is not in reset and can transmit frames. 1h[R/W] = Transmitter core is held.." "0,1" group.word 0x4++0x1 line.word 0x0 "FSI_TX_CFG_TX_CLK_CTRL,Transmit clock control register." hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h[R/W] = Reserved 1h[R/W] = Input clock /1 2h[R/W] = Input clock /2.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h[R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h[R/W] = The.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h[R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h[R/W] = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2,Transmit operation control register low." bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-target TDM operation. 0h[R/W] Transmit TDM Mode is not enabled. 1h[R/W] Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h[R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h[R/W] = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h[R/W] = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h[R/W] = The ping counter will.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h[R/W] = The transmitted CRC value is computed by hardware. 1h[R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h[R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h[R/W] = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h[R/W] = FSI is in normal mode of operation. 1h[R/W] = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h[R/W] = Data will be transmitted on one data line [TXD0] 1h[R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of.." "0,1,2,3" line.word 0x2 "FSI_TX_CFG_TX_OPER_CTRL_HI_ALT1,Transmit operation control register high." hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h[R/W] = Trigger 1 is the source. 01h[R/W] = Trigger 2 is the source. 02h[R/W] = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "FSI_TX_CFG_TX_FRAME_CTRL,Transmit frame control register." bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b[R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b[R/W] = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "FSI_TX_CFG_TX_FRAME_TAG_UDATA,Transmit frame tag and user data register." hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "FSI_TX_CFG_TX_BUF_PTR_LOAD,Transmit buffer pointer control load register." hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_PTR_STS,Transmit buffer pointer control status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "FSI_TX_CFG_TX_PING_CTRL_ALT1,Transmit ping control register." hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h[R/W] = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h[R/W] = External triggers will not be used to generate ping frames. 1h[R/W] = The selected external trigger [selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h[R/W] = The ping timer is disabled and will not generate ping frames. 1h[R/W] = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h[R/W] = Clear the CNT_RST. 1h[R/W] = The.." "0,1" line.word 0x2 "FSI_TX_CFG_TX_PING_TAG,Transmit ping tag register." hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_REF,Transmit ping timeout counter reference." hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_CNT,Transmit ping timeout current count." hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value [TX_PING_TO_REF] at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "FSI_TX_CFG_TX_INT_CTRL,Transmit interrupt event control register." bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "FSI_TX_CFG_TX_DMA_CTRL,Transmit DMA event control register." bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the completion of a transmitted frame." "0,1" line.word 0x4 "FSI_TX_CFG_TX_LOCK_CTRL,Transmit lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "FSI_TX_CFG_TX_EVT_STS,Transmit event and error status flag register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by Writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Overrun has not occured. 1h[R] = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Underrun has not occured. 1h[R] = Buffer Underrun has occured." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "FSI_TX_CFG_TX_EVT_CLR,Transmit event and error clear register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "FSI_TX_CFG_TX_EVT_FRC,Transmit event and error flag force register." bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" group.word 0x30++0x1 line.word 0x0 "FSI_TX_CFG_TX_USER_CRC,Transmit user-defined CRC register." hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "FSI_TX_CFG_TX_ECC_DATA,Transmit ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "FSI_TX_CFG_TX_ECC_VAL,Transmit ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "FSI_TX_CFG_TX_DLYLINE_CTRL,Transmit delay Line control register." hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD1 path. TXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD0 path. TXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_BASE_j,Base address for transmit buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree "FSI_TX2" base ad:0x502A0000 group.word 0x0++0x1 line.word 0x0 "FSI_TX_CFG_TX_MASTER_CTRL,Transmit master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h[R/W] = Transmitter core is not in reset and can transmit frames. 1h[R/W] = Transmitter core is held.." "0,1" group.word 0x4++0x1 line.word 0x0 "FSI_TX_CFG_TX_CLK_CTRL,Transmit clock control register." hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h[R/W] = Reserved 1h[R/W] = Input clock /1 2h[R/W] = Input clock /2.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h[R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h[R/W] = The.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h[R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h[R/W] = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2,Transmit operation control register low." bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-target TDM operation. 0h[R/W] Transmit TDM Mode is not enabled. 1h[R/W] Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h[R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h[R/W] = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h[R/W] = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h[R/W] = The ping counter will.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h[R/W] = The transmitted CRC value is computed by hardware. 1h[R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h[R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h[R/W] = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h[R/W] = FSI is in normal mode of operation. 1h[R/W] = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h[R/W] = Data will be transmitted on one data line [TXD0] 1h[R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of.." "0,1,2,3" line.word 0x2 "FSI_TX_CFG_TX_OPER_CTRL_HI_ALT1,Transmit operation control register high." hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h[R/W] = Trigger 1 is the source. 01h[R/W] = Trigger 2 is the source. 02h[R/W] = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "FSI_TX_CFG_TX_FRAME_CTRL,Transmit frame control register." bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b[R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b[R/W] = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "FSI_TX_CFG_TX_FRAME_TAG_UDATA,Transmit frame tag and user data register." hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "FSI_TX_CFG_TX_BUF_PTR_LOAD,Transmit buffer pointer control load register." hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_PTR_STS,Transmit buffer pointer control status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "FSI_TX_CFG_TX_PING_CTRL_ALT1,Transmit ping control register." hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h[R/W] = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h[R/W] = External triggers will not be used to generate ping frames. 1h[R/W] = The selected external trigger [selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h[R/W] = The ping timer is disabled and will not generate ping frames. 1h[R/W] = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h[R/W] = Clear the CNT_RST. 1h[R/W] = The.." "0,1" line.word 0x2 "FSI_TX_CFG_TX_PING_TAG,Transmit ping tag register." hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_REF,Transmit ping timeout counter reference." hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_CNT,Transmit ping timeout current count." hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value [TX_PING_TO_REF] at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "FSI_TX_CFG_TX_INT_CTRL,Transmit interrupt event control register." bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "FSI_TX_CFG_TX_DMA_CTRL,Transmit DMA event control register." bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the completion of a transmitted frame." "0,1" line.word 0x4 "FSI_TX_CFG_TX_LOCK_CTRL,Transmit lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "FSI_TX_CFG_TX_EVT_STS,Transmit event and error status flag register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by Writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Overrun has not occured. 1h[R] = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Underrun has not occured. 1h[R] = Buffer Underrun has occured." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "FSI_TX_CFG_TX_EVT_CLR,Transmit event and error clear register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "FSI_TX_CFG_TX_EVT_FRC,Transmit event and error flag force register." bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" group.word 0x30++0x1 line.word 0x0 "FSI_TX_CFG_TX_USER_CRC,Transmit user-defined CRC register." hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "FSI_TX_CFG_TX_ECC_DATA,Transmit ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "FSI_TX_CFG_TX_ECC_VAL,Transmit ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "FSI_TX_CFG_TX_DLYLINE_CTRL,Transmit delay Line control register." hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD1 path. TXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD0 path. TXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_BASE_j,Base address for transmit buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree "FSI_TX3" base ad:0x502A1000 group.word 0x0++0x1 line.word 0x0 "FSI_TX_CFG_TX_MASTER_CTRL,Transmit master control register." hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h[R/W] = Transmitter core is not in reset and can transmit frames. 1h[R/W] = Transmitter core is held.." "0,1" group.word 0x4++0x1 line.word 0x0 "FSI_TX_CFG_TX_CLK_CTRL,Transmit clock control register." hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h[R/W] = Reserved 1h[R/W] = Input clock /1 2h[R/W] = Input clock /2.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h[R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h[R/W] = The.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h[R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h[R/W] = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2,Transmit operation control register low." bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-target TDM operation. 0h[R/W] Transmit TDM Mode is not enabled. 1h[R/W] Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h[R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h[R/W] = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h[R/W] = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h[R/W] = The ping counter will.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h[R/W] = The transmitted CRC value is computed by hardware. 1h[R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h[R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h[R/W] = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h[R/W] = FSI is in normal mode of operation. 1h[R/W] = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h[R/W] = Data will be transmitted on one data line [TXD0] 1h[R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of.." "0,1,2,3" line.word 0x2 "FSI_TX_CFG_TX_OPER_CTRL_HI_ALT1,Transmit operation control register high." hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h[R/W] = Trigger 1 is the source. 01h[R/W] = Trigger 2 is the source. 02h[R/W] = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "FSI_TX_CFG_TX_FRAME_CTRL,Transmit frame control register." bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h[R/W] = Writing a 0 to this bit will have no effect. 1h[R/W] = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b[R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b[R/W] = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "FSI_TX_CFG_TX_FRAME_TAG_UDATA,Transmit frame tag and user data register." hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "FSI_TX_CFG_TX_BUF_PTR_LOAD,Transmit buffer pointer control load register." hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_PTR_STS,Transmit buffer pointer control status register." hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "FSI_TX_CFG_TX_PING_CTRL_ALT1,Transmit ping control register." hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h[R/W] = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h[R/W] = External triggers will not be used to generate ping frames. 1h[R/W] = The selected external trigger [selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h[R/W] = The ping timer is disabled and will not generate ping frames. 1h[R/W] = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h[R/W] = Clear the CNT_RST. 1h[R/W] = The.." "0,1" line.word 0x2 "FSI_TX_CFG_TX_PING_TAG,Transmit ping tag register." hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_REF,Transmit ping timeout counter reference." hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "FSI_TX_CFG_TX_PING_TO_CNT,Transmit ping timeout current count." hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value [TX_PING_TO_REF] at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "FSI_TX_CFG_TX_INT_CTRL,Transmit interrupt event control register." bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "FSI_TX_CFG_TX_DMA_CTRL,Transmit DMA event control register." bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the completion of a transmitted frame." "0,1" line.word 0x4 "FSI_TX_CFG_TX_LOCK_CTRL,Transmit lock control register." hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after Writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "FSI_TX_CFG_TX_EVT_STS,Transmit event and error status flag register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by Writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Overrun has not occured. 1h[R] = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Underrun has not occured. 1h[R] = Buffer Underrun has occured." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "FSI_TX_CFG_TX_EVT_CLR,Transmit event and error clear register." bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "FSI_TX_CFG_TX_EVT_FRC,Transmit event and error flag force register." bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h[W] =.." "0,1" group.word 0x30++0x1 line.word 0x0 "FSI_TX_CFG_TX_USER_CRC,Transmit user-defined CRC register." hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "FSI_TX_CFG_TX_ECC_DATA,Transmit ECC data register." hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "FSI_TX_CFG_TX_ECC_VAL,Transmit ECC value register." hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "FSI_TX_CFG_TX_DLYLINE_CTRL,Transmit delay Line control register." hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD1 path. TXD1 is taken directly from the.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD0 path. TXD0 is taken directly from the.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "FSI_TX_CFG_TX_BUF_BASE_j,Base address for transmit buffer." hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree.end tree "FSS0" base ad:0x0 tree "FSS0_DATA" tree "FSS0_DATA_REG0" base ad:0x60000000 group.long 0x0++0x3 line.long 0x0 "DATA_REG0_HPB_DATA_MEM_j,FSAS data region0." hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region0" tree.end tree "FSS0_DATA_REG1" base ad:0x80000000 group.long 0x0++0x3 line.long 0x0 "DATA_REG1_HPB_DATA_MEM_j,FSAS boot data region1." hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1" tree.end tree "FSS0_DATA_REG3" base ad:0x88000000 group.long 0x0++0x3 line.long 0x0 "DATA_REG3_HPB_DATA_MEM_j,FSAS bypass data region3." hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1" tree.end tree.end tree "FSS0_FOTA_GENREGS" base ad:0x5380B000 group.long 0x0++0xB line.long 0x0 "FOTA_GENREGS_FOTA_INIT,This register is used to initialize FOTA logic including M8051EW MCU." bitfld.long 0x0 5. "MCU_STALL_EN,Reserved field. This field SHALL be retained at 0 which is the default value." "0,1" bitfld.long 0x0 4. "FUNC_MODE,This bit is used for selection functional or debug mode. 1'b1 - M8051EW uses functional mode for regular operation. 1'b0 - M8051EW uses debug mode for debug using JTAG." "0,1" rbitfld.long 0x0 3. "PDMEM_INIT_DONE,This bit indicates that FOTA program/data memory RAM initialization is done. Until this bit is set access to program/data memory should not be performed by software." "0,1" bitfld.long 0x0 2. "MEMACCESS,This bit provides SOC CPU access to program/data memory and internal memory through FSS config interface when set. If clear these M8051EW memories are not accessible through config interface and is fully under the control of M8051EW. Software.." "0,1" bitfld.long 0x0 1. "CLKDIS,This bit holds M8051EW core clock gated when set to 1'b1. Clock to M8051EW is enabled at reset. SOC software sets this bit to put M8051EW and other FOTA logic in low power state when not used by enabling clock gating." "0,1" newline bitfld.long 0x0 0. "RESET,This bit holds M8051EW core in reset when set to 1'b1. System firmware clears this bit after setting up program and data memories." "0,1" line.long 0x4 "FOTA_GENREGS_FOTA_CTRL,This register is used to start M8051EW firmware." bitfld.long 0x4 0. "GO,SOC CPU sets this bit to indicate to M8051EW firmware that it can start the next FOTA page write. Once go is set SOC software has to ensure that it is set again only after receiving an interrupt (completion or error) from M8051EW. If this requirement.." "0,1" line.long 0x8 "FOTA_GENREGS_FOTA_ERR_INFO,This register contains information from FOTA logic used when servicing fsas_fota_stat_err_pend/fsas_fota_stat_err_req interrupt. This information is used in conjunction with FOTA interrupt status register.." hexmask.long.byte 0x8 12.--16. 1. "MCU_ERR_CODE,This field contains error code reported by M8051EW firmware when ERR_STS_IRQ_STATUS_RAW.mcu_err is set. Error codes are software defined. Example encoding: 5'd0 - Flash error encountered during auto status polling 5'd1 - Auto polling.." bitfld.long 0x8 9.--11. "DAT_ERR_SSTATUS,This field contains read error status code when ERR_STS_IRQ_STATUS_RAW.dat_read_err interrupt flag is set" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "DAT_ERR_RSTATUS,This field contains read error status code when ERR_STS_IRQ_STATUS_RAW.dat_read_err interrupt flag is set" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "CFG_ERR_SSTATUS,This field contains read error status code when ERR_STS_IRQ_STATUS_RAW.cfg_read_err interrupt flag is set" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "CFG_ERR_RSTATUS,This field contains read error status code when ERR_STS_IRQ_STATUS_RAW.cfg_read_err interrupt flag is set" "0,1,2,3,4,5,6,7" group.long 0x10++0x3 line.long 0x0 "FOTA_GENREGS_FOTA_GP0,FOTA general purpose 0 register. SOC CPU can write to this register to pass information to M8051EW firmware through ESFR space." hexmask.long.byte 0x0 24.--31. 1. "VAL3,General purpose 0 register val3." hexmask.long.byte 0x0 16.--23. 1. "VAL2,General purpose 0 register val2." hexmask.long.byte 0x0 8.--15. 1. "VAL1,General purpose 0 register val1." hexmask.long.byte 0x0 0.--7. 1. "VAL0,General purpose 0 register val0." rgroup.long 0x14++0x3 line.long 0x0 "FOTA_GENREGS_FOTA_GP1,FOTA general purpose 1 register. M8051EW can write to this register to pass information to SOC CPU through ESFR space. Interpretation for this register is software defined and can be made context dependent if required." hexmask.long.byte 0x0 24.--31. 1. "VAL3,General purpose 1 register val3." hexmask.long.byte 0x0 16.--23. 1. "VAL2,General purpose 1 register val2." hexmask.long.byte 0x0 8.--15. 1. "VAL1,General purpose 1 register val1." hexmask.long.byte 0x0 0.--7. 1. "VAL0,General purpose 1 register val0." group.long 0x18++0x7 line.long 0x0 "FOTA_GENREGS_FOTA_ADDR,FOTA operation write address register. SOC can write to this register to preload address for FOTA write instead of having 8051 firmware to setup address. Writing this register causes an indirect write to MCU_DAT_ADDR0-MCU_DAT_ADDR3.." hexmask.long.byte 0x0 24.--31. 1. "VAL3,FOTA write address bits 31:24" hexmask.long.byte 0x0 16.--23. 1. "VAL2,FOTA write address bits 23:16" hexmask.long.byte 0x0 8.--15. 1. "VAL1,FOTA write address bits 15:8" hexmask.long.byte 0x0 0.--7. 1. "VAL0,FOTA write address bits 7:0" line.long 0x4 "FOTA_GENREGS_FOTA_CNT,FOTA operation write byte count. SOC can write to this register to preload byte count based on the page size of the flash memory used. Writing this register causes an indirect write to MCU_DAT_CNT0-MCU_DAT_CNT1 ESFR registers that.." bitfld.long 0x4 8.--9. "VAL1,FOTA write byte count bits 9:8" "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "VAL0,FOTA write byte count bits 7:0" wgroup.long 0x20++0x3 line.long 0x0 "FOTA_GENREGS_STS_IRQ_IRQ_EOI,The End of Interrupt (EOI) Register allows the CPU to acknowledge completion of fsas_fota_stat_intr_req pulse interrupt. When this register is written to 1'b0. INTD logic used for converting fsas_ecc_intr_err_pend level.." bitfld.long 0x0 0. "EOI_VECTOR,Write 1'b0 to acknowledge fsas_fota_stat_intr_req pulse interrupt." "0,1" group.long 0x24++0xF line.long 0x0 "FOTA_GENREGS_STS_IRQ_IRQ_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_intr_pend/fsas_fota_stat_intr_req interrupt output. Write 0:.." bitfld.long 0x0 0. "FOTA_DONE,FOTA done raw status flag" "0,1" line.long 0x4 "FOTA_GENREGS_STS_IRQ_IRQ_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_intr_pend/fsas_fota_stat_intr_req interrupt output. Write 0: No.." bitfld.long 0x4 0. "FOTA_DONE,FOTA done status flag" "0,1" line.long 0x8 "FOTA_GENREGS_STS_IRQ_IRQ_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_intr_pend/fsas_fota_stat_intr_req interrupt output. Write.." bitfld.long 0x8 0. "FOTA_DONE,FOTA done enable set" "0,1" line.long 0xC "FOTA_GENREGS_STS_IRQ_IRQ_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_intr_pend/fsas_fota_stat_intr_req interrupt output." bitfld.long 0xC 0. "FOTA_DONE,FOTA done enable clear" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "FOTA_GENREGS_ERR_STS_IRQ_IRQ_EOI,The End of Interrupt (EOI) Register allows the CPU to acknowledge completion of fsas_fota_stat_err_req pulse interrupt. When this register is written to 1'b0. INTD logic used for converting fsas_ecc_intr_err_pend level.." bitfld.long 0x0 0. "EOI_VECTOR,Write 1'b0 to acknowledge fsas_fota_stat_err_req pulse interrupt." "0,1" group.long 0x44++0xF line.long 0x0 "FOTA_GENREGS_ERR_STS_IRQ_IRQ_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_err_pend/fsas_fota_stat_err_req interrupt output. Write.." bitfld.long 0x0 6. "MCU_ERR,MCU error raw status flag. This is used to communicate error conditions encountered by 8051 firmware to SOC CPU. Error code is captured in FOTA_ERR_INFO.mcu_err_code field. If 8051 firmware runs into any error conditions it sets the.." "0,1" bitfld.long 0x0 5. "DAT_WRITE_ERR,Data interface write status error raw status flag. This error flag gets set when M8051EW performs a data write and error status is returned. The CBA error status code received is stored in FOTA_ERR_INFO.dat_err_sstatus register." "0,1" bitfld.long 0x0 4. "DAT_READ_ERR,Data interface read status error raw status flag. This error flag gets set when M8051EW performs a data read and error status is returned. The CBA error status code received is stored in FOTA_ERR_INFO.dat_err_rstatus register." "0,1" bitfld.long 0x0 3. "CFG_WRITE_ERR,Config interface write status error raw status flag. This error flag gets set when M8051EW performs a configuration write and error status is returned. The CBA error status code received is stored in FOTA_ERR_INFO.cfg_err_sstatus register." "0,1" bitfld.long 0x0 2. "CFG_READ_ERR,Config interface read status error raw status flag. This error flag gets set when M8051EW performs a configuration read and error status is returned. The CBA error status code received is stored in FOTA_ERR_INFO.cfg_err_rstatus register." "0,1" line.long 0x4 "FOTA_GENREGS_ERR_STS_IRQ_IRQ_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_err_pend/fsas_fota_stat_err_req interrupt output. Write 0:.." bitfld.long 0x4 6. "MCU_ERR,MCU error status flag" "0,1" bitfld.long 0x4 5. "DAT_WRITE_ERR,Data interface write status error status flag" "0,1" bitfld.long 0x4 4. "DAT_READ_ERR,Data interface read status error status flag" "0,1" bitfld.long 0x4 3. "CFG_WRITE_ERR,Config interface write status error status flag" "0,1" bitfld.long 0x4 2. "CFG_READ_ERR,Config interface read status error status flag" "0,1" line.long 0x8 "FOTA_GENREGS_ERR_STS_IRQ_IRQ_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_err_pend/fsas_fota_stat_err_req interrupt output." bitfld.long 0x8 6. "MCU_ERR,MCU error enable set" "0,1" bitfld.long 0x8 5. "DAT_WRITE_ERR,Data interface write status error enable set" "0,1" bitfld.long 0x8 4. "DAT_READ_ERR,Data interface read status error enable set" "0,1" bitfld.long 0x8 3. "CFG_WRITE_ERR,Config interface write status error enable set" "0,1" bitfld.long 0x8 2. "CFG_READ_ERR,Config interface read status error enable set" "0,1" line.long 0xC "FOTA_GENREGS_ERR_STS_IRQ_IRQ_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_err_pend/fsas_fota_stat_err_req interrupt output." bitfld.long 0xC 6. "MCU_ERR,MCU error enable clear" "0,1" bitfld.long 0xC 5. "DAT_WRITE_ERR,Data interface write status error enable clear" "0,1" bitfld.long 0xC 4. "DAT_READ_ERR,Data interface read status error enable clear" "0,1" bitfld.long 0xC 3. "CFG_WRITE_ERR,Config interface write status error enable clear" "0,1" bitfld.long 0xC 2. "CFG_READ_ERR,Config interface read status error enable clear" "0,1" tree.end base ad:0x0 tree "FSS0_FSAS" tree "FSS0_FSAS_ECC_AGGR" base ad:0x5380F000 rgroup.long 0x0++0x3 line.long 0x0 "FSAS_ECC_AGGR_REV,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "FSAS_ECC_AGGR_VECTOR,ECC Vector Register." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "FSAS_ECC_AGGR_STAT,Misc Status." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "FSAS_ECC_AGGR_RESERVED_SVBUS_j,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "FSAS_ECC_AGGR_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "FSAS_ECC_AGGR_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "FSAS_ECC_AGGR_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "FSAS_ECC_AGGR_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "FSAS_ECC_AGGR_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "FSAS_ECC_AGGR_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "FSAS_ECC_AGGR_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "FSAS_ECC_AGGR_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "FSAS_ECC_AGGR_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "FSAS_ECC_AGGR_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "FSAS_ECC_AGGR_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "FSAS_ECC_AGGR_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "FSS0_FSAS_OTFA_REGS" base ad:0x53802000 rgroup.long 0x0++0x3 line.long 0x0 "FSAS_OTFA_REGS_REVID,This register defines the revision and functional ID." hexmask.long 0x0 0.--31. 1. "REVID,REVID" group.long 0x4++0x1B line.long 0x0 "FSAS_OTFA_REGS_SCFG,This register defines the power IDLE mode." bitfld.long 0x0 0.--1. "IDLE_MODE,IDLE MODE. 0x0: Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally i.e. regardless of the IP module's internal requirements. Backup mode for debug only. 0x1: No-idle mode: local target.." "0: Force-idle mode: local target's idle state follows,1: No-idle mode: local target never enters idle state,2: Smart-idle mode: local target's idle state..,3: Reserved" line.long 0x4 "FSAS_OTFA_REGS_ISR,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug and SW testing." hexmask.long.byte 0x4 12.--15. 1. "MAC_ERR,Region MAC compare error event Read MAC did not match the Write MAC. Write0:No action Read0:No event pending Read1:Event pending Write1:Set event (debug)" newline hexmask.long.byte 0x4 8.--11. 1. "WRT_ERR,Region write error event write cmd issues when write is disabled Write0:No action Read0:No event pending Read1:Event pending Write1:Set event (debug)" newline hexmask.long.byte 0x4 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region. Write0:No action Read0:No event pending Read1:Event pending Write1:Set event (debug)" newline hexmask.long.byte 0x4 0.--3. 1. "CTR_WKV,AES CTR enabled region violated Wrt Once Per Wrt Key rule. Write0:No action Read0:No event pending Read1:Event pending Write1:Set event (debug)" line.long 0x8 "FSAS_OTFA_REGS_IS,Per-event 'enabled' interrupt status vector. Enabled status isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. i.e. even if not enabled)." hexmask.long.byte 0x8 12.--15. 1. "MAC_ERR,Region MAC compare error event Read MAC did not match the Write MAC. Write0:No action Read0:No (enabled) event pending Read1:Event pending Write1:Clear event" newline hexmask.long.byte 0x8 8.--11. 1. "WRT_ERR,Region write error event write cmd issues when write is disabled. Write0:No action Read0:No (enabled) event pending Read1:Event pending Write1:Clear event" newline hexmask.long.byte 0x8 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossing a start or end of a region. Write0:No action Read0:No (enabled) event pending Read1:Event pending Write1:Clear event Note: a RMW transaction can make create 2 events 1st.." newline hexmask.long.byte 0x8 0.--3. 1. "CTR_WKV,AES CTR enabled region violated Wrt Once Per Wrt Key rule. Write0:No action Read0:No (enabled) event pending Read1:Event pending Write1:Clear event and reset counter" line.long 0xC "FSAS_OTFA_REGS_IES,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." hexmask.long.byte 0xC 12.--15. 1. "MAC_ERR,Region MAC compare error event Read MAC did not match the Write MAC. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Enable interrupt" newline hexmask.long.byte 0xC 8.--11. 1. "WRT_ERR,Region write error event write cmd issues when write is disabled. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Enable interrupt" newline hexmask.long.byte 0xC 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossing a start or end of a region. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Enable interrupt" newline hexmask.long.byte 0xC 0.--3. 1. "CTR_WKV,AES CTR enabled region violated Wrt Once Per Wrt Key rule. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Enable interrupt" line.long 0x10 "FSAS_OTFA_REGS_IEC,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." hexmask.long.byte 0x10 12.--15. 1. "MAC_ERR,Region MAC compare error event Read MAC did not match the Write MAC. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Enable interrupt" newline hexmask.long.byte 0x10 8.--11. 1. "WRT_ERR,Region write error event write cmd issues when write is disabled Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Disable interrupt" newline hexmask.long.byte 0x10 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossing a start or end of a region. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Disable interrupt" newline hexmask.long.byte 0x10 0.--3. 1. "CTR_WKV,AES CTR enabled region violated Wrt Once Per Wrt Key rule. Write0:No action Read0:Interrupt disabled (masked) Read1:Interrupt enabled Write1:Disable interrupt" line.long 0x14 "FSAS_OTFA_REGS_CCFG,This register controls the enabling and the functionality of this AES core." bitfld.long 0x14 31. "MASTER_EN_RD,This register controls the enabling and the functionality of this IP. Write0:Request to Disabled and enter into Bypass mode. Read0:Disabled and enter into Bypass mode is active When Disabled then Bypass mux is enabled which will directly.." "0,1" newline bitfld.long 0x14 15. "FE_PROC_EN,This register allows the AES-CTR GCM GHASH modes to start the required AES jobs as soon as the RD CMD is passed through OTFA to help hide the AES op latency 0x0: Front End CMD AES start disable only backend response Legacy mode 0x1:.." "0: Front End CMD AES start disable,1: Front End CMD AES start enabled" newline bitfld.long 0x14 12. "MAC_LSB_ALIGN_EN,This register controls shift of mac data to always LSB independent of address. 0x0: Default mode 0x1: Set for FSS use case updated Opti flash." "0: Default mode,1: Set" newline bitfld.long 0x14 10.--11. "MAC_SIZE,This register defines the MAC size. 0x0: 4-bytes 0x1: 8-bytes 0x2: 12-bytes 0x3: 16-bytes." "0: 4-bytes,1: 8-bytes,2: 12-bytes,3: 16-bytes" newline bitfld.long 0x14 9. "ERROR_RESP_EN,This register controls the enable of of the OCP Error Response if a MAC error event occurred. The sys_SResp[1:0] will be drive to 3(Error Response) for data words which had the MAC error." "0,1" newline bitfld.long 0x14 8. "OTFA_WAIT,This register allows the ability to stop any new transactions from getting accepted and allow the current transactions to complete. Note: The otfa_emif has a one deep receive pipe stage this will allow one new crypto cmd to get accepted before.." "0,1" newline bitfld.long 0x14 6. "CACHE_ENABLE,This register controls the enable of the MAC cache Rd buffer. 0x0: Disabled 0x1: Enabled" "0: Disabled,1: Enabled" newline bitfld.long 0x14 5. "CACHE_EVICT_MODE,cache evict mode" "0,1" newline bitfld.long 0x14 4. "KEY_SIZE,This register controls the key size used for all AES operations. 0x0: 128 Bit 0x1: 256 Bit" "0: 128 Bit,1: 256 Bit" newline hexmask.long.byte 0x14 0.--3. 1. "RD_WRT_OPT,This register defines the static allocation of the AES/GHASH cores to read transactions and write transactions. Adjusted only allowed before the OTFA is enabled for first time or after Enable must use the wait/busy method. 0x0: Read and Write.." line.long 0x18 "FSAS_OTFA_REGS_CSTATUS,This is the status register which can be used to fine tune the AES core allocation to the Rd Pipe and Wrt Pipe along with a global activity status. Performance Counters which counts the number of events which causes high latency." rbitfld.long 0x18 31. "BUSY,0x0: No transactions are active crypto or non-crypto. 0x1: One or more transactions are active crypto or non-crypto SW needs to read 2 consecutive 0 with 100ns delay or more between samples to insure the pipe is fully empty" "0: No transactions are active,1: One or more transactions are active" newline rbitfld.long 0x18 30. "CRYPTO_BUSY,0x0: No crypto transactions are active 0x1: One or more crypto transactions are active. SW needs to read 2 consecutive 0 with 100ns delay or more between samples to insure the pipe is fully empty" "0: No crypto transactions are active,1: One or more crypto transactions are active" newline hexmask.long.word 0x18 16.--29. 1. "RD_STALL_EVENT_CNT,Read the number of Rd Pipe full events. The counter increments every clock.event that we have no more rd cores available for a new transaction. Saturates to 0x3FFF. Any Write to CSTATUS reset RdStallEventCnt and WrtStallEventCnt to 0x0." newline hexmask.long.word 0x18 0.--13. 1. "WRT_STALL_EVENT_CNT,Read the number of Wrt Pipe full events. The counter increments every clock.event that we have no more wrt cores available for a new transaction. Saturates to 0x3FFF. Any Write to CSTATUS reset RdStallEventCnt and WrtStallEventCnt to.." rgroup.long 0x220++0xF line.long 0x0 "FSAS_OTFA_REGS_IRQADDINFO0,IRQAdditionalInfo0 ." hexmask.long 0x0 0.--31. 1. "IRQ_MADDR,Master Address which caused the event. Note During MAC Error Events a new response can over write the data. Another method to debug is to enable error response this can also be used to mark which transaction caused the error." line.long 0x4 "FSAS_OTFA_REGS_IRQADDINFO1,IRQAdditionalInfo1 ." hexmask.long.byte 0x4 14.--17. 1. "IRQ_MLEN,Master OCP LENGTH which caused the event" newline bitfld.long 0x4 11.--13. "IRQ_MSEQ,Master OCP Seq which caused the event. Not avalible for MAC error events" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "IRQ_MCMD,Master OCP CMD which caused the event. Note: During MAC Error Events a new response can over write the data. Another method to debug is to enable error response this can also be used to mark which transaction caused the error." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--7. 1. "IRQ_MID,Master OCP ID which caused the event Note: During MAC Error Events a new response can over write the data. Another method to debug is to enable error response this can also be used to mark which transaction caused the error." line.long 0x8 "FSAS_OTFA_REGS_MACCACHEINFO,MACCacheInfo ." hexmask.long.word 0x8 0.--15. 1. "CACHE_MISS_EVENT_CNT,Counts the number of Cache Miss events. Saturates to 0xFFFF Any Write to reset to 0x0 Note that any Read Transaction that crosses a cache line will trigger a cache miss and 2 lines will be read. Also any Write Transaction that.." line.long 0xC "FSAS_OTFA_REGS_RMWRMCNT,RMWRMCnt ." hexmask.long.word 0xC 16.--31. 1. "RM_EVENT_CNT,Counts the number of RM events. Saturates to 0xFFFF Any Write to RMWRMCNT will reset rm_event_cnt and rmw_event_cnt" newline hexmask.long.word 0xC 0.--15. 1. "RMW_EVENT_CNT,Counts the number of RMW events. Saturates to 0xFFFF Any Write to RMWRMCNT will reset rm_event_cnt and rmw_event_cnt" group.long 0x20++0x13 line.long 0x0 "FSAS_OTFA_REGS_RG_RGCFG_j,RegionCfg" bitfld.long 0x0 4. "WRT_PROTECT,WRT protect" "0,1" newline bitfld.long 0x0 2.--3. "MAC_MODE,MAC mode" "0,1,2,3" newline bitfld.long 0x0 0.--1. "AES_MODE,AES mode" "0,1,2,3" line.long 0x4 "FSAS_OTFA_REGS_RG_RGMACST_j,RegionMacStart" hexmask.long.tbyte 0x4 0.--19. 1. "M_START,This defines the start of the mac buffer in 4KBytes steps" line.long 0x8 "FSAS_OTFA_REGS_RG_RGST_j,RegionStart" hexmask.long.tbyte 0x8 0.--19. 1. "R_START,This defines the start of the crypto region in 4KBytes steps" line.long 0xC "FSAS_OTFA_REGS_RG_RGSI_j,RegionSize" hexmask.long.tbyte 0xC 0.--19. 1. "R_SIZE,This defines the size of the crypto region in 4KBytes steps" line.long 0x10 "FSAS_OTFA_REGS_RG_RKEYE_j_k,RegionKeyE" hexmask.long 0x10 0.--31. 1. "R_KEY_E,Key E" group.long 0x50++0x3 line.long 0x0 "FSAS_OTFA_REGS_RG_RKEYEP_j_k,RegionKeyEP" hexmask.long 0x0 0.--31. 1. "R_KEY_EP,Key EP" group.long 0x70++0x3 line.long 0x0 "FSAS_OTFA_REGS_RG_RKEYA_j_k,RegionKeyA" hexmask.long 0x0 0.--31. 1. "R_KEY_A,Key A" group.long 0x80++0x3 line.long 0x0 "FSAS_OTFA_REGS_RG_RKEYAP_j_k,RegionKeyAP" hexmask.long 0x0 0.--31. 1. "R_KEY_AP,Key AP" group.long 0x90++0x3 line.long 0x0 "FSAS_OTFA_REGS_RG_RIV_j_k,RegionIV" hexmask.long 0x0 0.--31. 1. "R_IV,IV" tree.end tree.end tree "FSS0_FSS" tree "FSS0_FSS_FSAS_GENREGS" base ad:0x53801000 rgroup.long 0x0++0x3 line.long 0x0 "FSS_FSAS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x4++0x3 line.long 0x0 "FSS_FSAS_GENREGS_SYSCONFIG,Controls various parameters of the cotroller state." hexmask.long.byte 0x0 11.--18. 1. "HW_RW_DELAY_COUNT,Delay for switching between reads and writes" bitfld.long 0x0 10. "HW_RW_DELAY_EN,Enable delay when switching between reads and writes to avoid read-write collision for sensitive logic." "0,1" bitfld.long 0x0 9. "DP_EN,0 Safety double pumping disabled. 1 Safety double pumping enabled" "0,1" newline bitfld.long 0x0 8. "OSPI_32B_DISABLE_MODE,0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled" "0,1" bitfld.long 0x0 7. "DISXIP,This field is used to disable XIP prefetching. 0 XIP Prefetch Enabled. 1 XIP prefetch disabled Please note that this is referring to prefetching feature that is useful for linear accesses associated with XIP. This is NOT referring to XIP features.." "0,1" bitfld.long 0x0 6. "OSPI_DDR_DISABLE_MODE,0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled" "0,1" newline bitfld.long 0x0 3. "ECC_DISABLE_ADR,0 Block address within ECC calculation 1 Block address not within ECC calculation" "0,1" rbitfld.long 0x0 2. "FSS_AES_EN_IPCFG,1 select security 0 disable security" "0,1" bitfld.long 0x0 0. "ECC_EN,0 ECC disabled. 1 ECC enabled" "0,1" group.long 0x80++0x3 line.long 0x0 "FSS_FSAS_GENREGS_DP_ERR_INJ_CTRL,This register is used to setup double pumping error injection. Only one error injection enable field has to be set in this register at a given time. After error injection is enabled. a read must be issued to a valid flash.." hexmask.long.byte 0x0 8.--15. 1. "BIT_SEL,Bit select for injecting error on command or read return fields. For command error only 0 through 47 are valid values for bit select. For read return error only 0 through 166 are valid values for bit select." bitfld.long 0x0 4. "RET_NFIRST_LAST,1'b0 - Inject on first read return phase 1'b1 - Inject on last read return phase" "0,1" bitfld.long 0x0 3. "EN_DUPL_RET,Enable error injection on duplicate read return fields." "0,1" newline bitfld.long 0x0 2. "EN_ORIG_RET,Enable error injection on original read return fields." "0,1" bitfld.long 0x0 1. "EN_DUPL_CMD,Enable error injection on duplicate command fields." "0,1" bitfld.long 0x0 0. "EN_ORIG_CMD,Enable error injection on original command fields." "0,1" wgroup.long 0x10++0x3 line.long 0x0 "FSS_FSAS_GENREGS_IRQ_IRQ_EOI,The End of Interrupt (EOI) Register allows the CPU to acknowledge completion of fsas_ecc_intr_err_req pulse interrupt. When this register is written to 1'b0. INTD logic used for converting fsas_ecc_intr_err_pend level.." bitfld.long 0x0 0. "EOI_VECTOR,Write 1'b0 to acknowledge fsas_ecc_intr_err_req pulse interrupt." "0,1" group.long 0x14++0xF line.long 0x0 "FSS_FSAS_GENREGS_IRQ_IRQ_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources associated with each bit in this register to be manually set when writing a 1 to a specific bit. This register corresponds to fsas_ecc_intr_err_pend (level) and.." bitfld.long 0x0 4. "DP_RET_ERROR,Safety double pumping read return error" "0,1" bitfld.long 0x0 3. "DP_CMD_ERROR,Safety double pumping command error" "0,1" bitfld.long 0x0 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" newline bitfld.long 0x0 1. "ECC_ERROR_2BIT,An ECC error occurred on 2 bits and was not correctable" "0,1" bitfld.long 0x0 0. "ECC_ERROR_1BIT,An ECC error occurred on only 1 bit and was corrected" "0,1" line.long 0x4 "FSS_FSAS_GENREGS_IRQ_IRQ_STATUS,The IRQ_STATUS register allows the interrupt sources associated with each bit in this register to be manually cleared when writing a 1 to a specific bit. This register corresponds to fsas_ecc_intr_err_pend (level) and.." bitfld.long 0x4 4. "DP_RET_ERROR,Safety double pumping read return error" "0,1" bitfld.long 0x4 3. "DP_CMD_ERROR,Safety double pumping command error" "0,1" bitfld.long 0x4 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" newline bitfld.long 0x4 1. "ECC_ERROR_2BIT,An ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x4 0. "ECC_ERROR_1BIT,ECC error on 1 bits. corrected" "0,1" line.long 0x8 "FSS_FSAS_GENREGS_IRQ_IRQ_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources associated with each bit in this register to be manually enabled when writing a 1 to a specific bit. This register corresponds to fsas_ecc_intr_err_pend (level).." bitfld.long 0x8 4. "DP_RET_ERROR,Safety double pumping read return error" "0,1" bitfld.long 0x8 3. "DP_CMD_ERROR,Safety double pumping command error" "0,1" bitfld.long 0x8 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" newline bitfld.long 0x8 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x8 0. "ECC_ERROR_1BIT,ECC error on 1 bits. corrected" "0,1" line.long 0xC "FSS_FSAS_GENREGS_IRQ_IRQ_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources associated with each bit in this register to be manually disabled when writing a 1 to a specific bit. This register corresponds to fsas_ecc_intr_err_pend.." bitfld.long 0xC 4. "DP_RET_ERROR,Safety double pumping read return error" "0,1" bitfld.long 0xC 3. "DP_CMD_ERROR,Safety double pumping command error" "0,1" bitfld.long 0xC 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" newline bitfld.long 0xC 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0xC 0. "ECC_ERROR_1BIT,ECC error on 1 bits. corrected" "0,1" group.long 0x30++0x7 line.long 0x0 "FSS_FSAS_GENREGS_ECC_REGCTRL_ECC_RGSTRT_j,This defines the start of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x0 0.--19. 1. "R_START,This defines the start of the ECC region in 4KBytes steps. Address start = {start[19:0] 0x000} 0x0 means the start is 0x0000_0000 0x1 means the start is 0x0000_1000 0xA means the start is 0x0000_A000 Note the offset + size should be <=.." line.long 0x4 "FSS_FSAS_GENREGS_ECC_REGCTRL_ECC_RGSIZ_j,This defines the size of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x4 0.--19. 1. "R_SIZE,This defines the size of the ECC region in 4KBytes steps 0x0 means the size is zero and disabled 0x1 means the size is 4KBytes 0xA means the size is 40KBytes 0xF_FFFF means the size is 4GBytes Note the offset + size should be <= 4GBytes wrap.." rgroup.long 0x70++0x3 line.long 0x0 "FSS_FSAS_GENREGS_ERR_ECC_BLOCK_ADR,The ERR_ECC_BLOCK_ADR register holds the current top of stack ECC error block address. this is only valid when the ecc_err_valid is set" hexmask.long 0x0 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC 32 byte aligned block address" group.long 0x74++0x7 line.long 0x0 "FSS_FSAS_GENREGS_ERR_ECC_TYPE,The ERR_ECC_TYPE register holds the current top of stack ECC error info. this is only valid when the ecc_err_valid is set" bitfld.long 0x0 31. "ECC_ERR_VALID,When set indicates that there is valid ECC error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x0 5. "ECC_ERR_ADR,When set indicates that there was a single error detected within the address field. Bits 0 and 1 in this register indicate whether it is single or double error." "0,1" rbitfld.long 0x0 4. "ECC_ERR_MAC,When set indicates that there was a single error detected within the MAC field. Bits 0 and 1 in this register indicate whether it is single or double error." "0,1" newline rbitfld.long 0x0 3. "ECC_ERR_DA1,When set indicates that there was a single error detected within the High Data word which is bits 127 through 64 of the data word. Bits 0 and 1 in this register indicate whether it is single or double error." "0,1" rbitfld.long 0x0 2. "ECC_ERR_DA0,When set indicates that there was a single error detected within the Low Data word which is bits 63 through 0 of the data word. Bits 0 and 1 in this register indicate whether it is single or double error." "0,1" rbitfld.long 0x0 1. "ECC_ERR_DED,When set indicates that there was a double error detected for the block" "0,1" newline rbitfld.long 0x0 0. "ECC_ERR_SEC,When set indicates that there was a single error detected for the block. The fields that had single error are reported by bits 2 through 5 in this register. It is possible that single error is reported in multiple fields since the ECCM inputs.." "0,1" line.long 0x4 "FSS_FSAS_GENREGS_ERR_WRT_TYPE,The ERR_WRT_TYPE register holds the current top of stack write error info. this is only valid when the wrt_err_valid is set" bitfld.long 0x4 31. "WRT_ERR_VALID,When set indicates that there is valid write error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x4 13. "WRT_ERR_BEN,When set indicates that there was a write error due to a non-contiguous byte enables or because write byte count was not 32-byte multiple. Please note that this bit will always be set when wrt_err_valid bit is set. There is no write error if.." "0,1" rbitfld.long 0x4 12. "WRT_ERR_ADR,When set indicates that there was a write error due to a non-aligned address. Please note that this bit can only be set if address was 16-byte multiple but not 32-byte multiple. For example an address of 0x10 or 0x30 for writes will cause.." "0,1" newline hexmask.long.word 0x4 0.--11. 1. "WRT_ERR_ROUTEID,Indicates the Route ID for the Master that caused the write error" tree.end tree "FSS0_FSS_GENREGS" base ad:0x53800000 rgroup.long 0x0++0x3 line.long 0x0 "FSS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" tree.end tree.end tree "FSS0_IMEM_GENREGS" base ad:0x5380D000 group.long 0x0++0x3 line.long 0x0 "IMEM_GENREGS_LOC_j,M8051EW Internal Data Memory array." hexmask.long 0x0 0.--31. 1. "VAL,Value of element in internal data memory" tree.end base ad:0x0 tree "FSS0_OSPI" tree "FSS0_OSPI_CFG" base ad:0x53806000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x8++0x3 line.long 0x0 "OSPI_CFG_STAT,The Status register provide general status bits for the ospi." bitfld.long 0x0 1. "MEM_INIT_DONE,Bit indicates the memory initialization done status of the OSPI SRAM 1:Memory Intialization Done" "?,1: Memory Intialization Done" wgroup.long 0x20++0x3 line.long 0x0 "OSPI_CFG_EOI,End of Interrupt Register." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targetted interrupt. (E.g. Ext TS is bit 0).Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" tree.end tree "FSS0_OSPI_FLASH_CFG" base ad:0x53808000 group.long 0x0++0x1F line.long 0x0 "OSPI_FLASH_CFG_CONFIG_REG,This register contains basic configuration fields of the controller." rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value0 : Active target is selected based on Peripheral Chip Select Lines [bits [13:10]]. Value=1 Active target is selected based on actual AHB address [the partition for each device is calculated with respect to.." "0,1" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = (master reference clock) baud_rate_divisor. Where BD is:4b0000 = /24b0001 = /44b0010 = /64b0011 = /84b0100 = /104b0101 = /12..4b1111 = /32While the PHY Mode is enabled clock from DLL is.." newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value1 : Operate the device in XIP mode immediately Use this register when the.." "0,1" newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "0,1" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as [address + N] where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx01110xx011101x01110110111011111111111[no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode:0 : only 1 of 4 selects n_ss_out[3:0] is active1 : allow external 4-to-16 decode [n_ss_out = ss]" "0: only 1 of 4 selects n_ss_out[3:0] is active1 :..,?" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable:0 : Use Direct Access Controller/Indirect Access Controller1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB.." "0: Use Direct Access Controller/Indirect Access..,?" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller:0 : disable the Direct Access Controller once current transfer of the data word [FF_W] is complete.1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "0: disable the Direct Access Controller once..,1: enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]" "0: RESET feature on DQ3 pin of the device,1: RESET feature on dedicated pin of the device.." newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word.0 : the SPI clock is active outside the word1 : the SPI clock is inactive outside the word" "0: the SPI clock is active outside the word1 : the..,?" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word:0 : the SPI clock is quiescent low1 : the SPI clock is quiescent high" "0: the SPI clock is quiescent low1 : the SPI clock..,?" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable:0 : disable the Octal-SPI once current transfer of the data word [FF_W] is complete.1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "0: disable the Octal-SPI,1: enable the Octal-SPI" line.long 0x4 "OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG,This register defines the configuration of Multiple-SPI READ instruction. This register should be setup while the controller is idle." hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes:0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,?,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes:0 : Addresses can be shifted to the device on DQ0 only1 : Addresses can be shifted to the device on DQ0 and DQ1 only2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2 and.." "0: Addresses can be shifted to the device on DQ0..,?,?,?" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type:0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only]1 : Use DIO-SPI mode [Instructions Address and Data always sent on DQ0 and DQ1]2 : Use QIO-SPI mode [Instructions Address and Data always.." "0: Use Standard SPI mode [instruction always..,?,?,?" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG,This register defines the configuration of Multiple-SPI WRITE (Program Page) instruction. This register should be setup while the controller is idle." hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes:0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,?,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes:0 : Addresses can be shifted to the device on DQ0 only1 : Addresses can be shifted to the device on DQ0 and DQ1 only2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2 and.." "0: Addresses can be shifted to the device on DQ0..,?,?,?" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "OSPI_FLASH_CFG_DEV_DELAY_REG,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk. defined in this table.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different targets and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG,This register is used to adjust SPI transfer conditions in order to fetch and capture data reliably. This register should be setup while the controller is idle." hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "OSPI_FLASH_CFG_DEV_SIZE_CONFIG_REG,This register allows the user to define the memory organization of using Flash Devices. This register should be setup while the controller is idle." bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value00 : size of 512Mb. Value01 : size of 1Gb. Value10 : size of 2Gb. Value11 : size of 4Gb." "0,1,2,3" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value00 : size of 512Mb. Value01 : size of 1Gb. Value10 : size of 2Gb. Value11 : size of 4Gb." "0,1,2,3" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value00 : size of 512Mb. Value01 : size of 1Gb. Value10 : size of 2Gb. Value11 : size of 4Gb." "0,1,2,3" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value00 : size of 512Mb. Value01 : size of 1Gb. Value10 : size of 2Gb. Value11 : size of 4Gb." "0,1,2,3" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "OSPI_FLASH_CFG_SRAM_PARTITION_CFG_REG,This register allows the user to allocate the SRAM area for indirect writes and reads. N in this register is the SRAM depth. configured in the cdns_ospi_flash_ctrl_defs_default.v. The default value of N is 8 what.." hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "OSPI_FLASH_CFG_IND_AHB_ADDR_TRIGGER_REG,This register allows the user to define the address distinguishing DAC access from triggered INDAC one. This register should be setup while the controller is idle." hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." group.long 0x24++0x7 line.long 0x0 "OSPI_FLASH_CFG_REMAP_ADDR_REG,This register allows the user to define the address offset for DAC accesses. This register should be setup while the controller is idle." hexmask.long 0x0 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x4 "OSPI_FLASH_CFG_MODE_BIT_CONFIG_REG,This register allows the user to define the mode bits for corresponding Flash Device. It also provides configuration for CRC aware SPI transfers. This register should be setup while the controller is idle." hexmask.long.byte 0x4 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower] The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x4 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper] The second CRC byte returned after RX data chunk." newline bitfld.long 0x4 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline bitfld.long 0x4 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "OSPI_FLASH_CFG_SRAM_FILL_REG,This register keeps the values of current fill levels of both SRAM partitions." hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition" group.long 0x30++0x17 line.long 0x0 "OSPI_FLASH_CFG_TX_THRESH_REG,This register allows the user to define the TX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle." hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "OSPI_FLASH_CFG_RX_THRESH_REG,This register allows the user to define the RX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle." hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "OSPI_FLASH_CFG_WRITE_COMPLETION_CTRL_REG,This register defines how the controller will poll the device following a write transfer. By default it is set to poll bit 0 of the device STATUS register (using opcode 0x05). which is common across all devices to.." hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "OSPI_FLASH_CFG_NO_OF_POLLS_BEF_EXP_REG,This register defines maximum number of poll cycles. If the expected value of the bit being polled isnot gotten after number defined in this register. the auto-polling is done on the next phase." hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "OSPI_FLASH_CFG_IRQ_STATUS_REG,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted.." bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode0 : FIFO is not full1 : FIFO is full" "0,1" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "?,1: FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode0 : FIFO is not full 1 : FIFO is full" "?,1: FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "?,1: FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "0: no overflow has been detected,1: an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected:0 : no underflow has been detected1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the.." "0: no underflow has been detected1 : underflow is..,?" newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI." "0: no mode fault has been detected1 : a mode fault..,?" line.long 0x14 "OSPI_FLASH_CFG_IRQ_MASK_REG,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled." bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x50++0xB line.long 0x0 "OSPI_FLASH_CFG_LOWER_WR_PROT_REG,This register allows the user to define lower boundary of the write protection area. This register should be setup while the controller is idle." hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from Writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "OSPI_FLASH_CFG_UPPER_WR_PROT_REG,Is register allows the user to define upper boundary of the write protection area. This register should be setup while the controller is idle." hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from Writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "OSPI_FLASH_CFG_WR_PROT_CTRL_REG,This register allows the user to define the configuration of write protection settings. This register should be setup while the controller is idle." bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" group.long 0x60++0x23 line.long 0x0 "OSPI_FLASH_CFG_INDIRECT_READ_XFER_CTRL_REG,This register allows the user to control of the Indirect Read Transfer logic." rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.; indirect operation [status]" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress [status]" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "OSPI_FLASH_CFG_INDIRECT_READ_XFER_WATERMARK_REG,This register allows the user to define watermark level for Indirect read transfers. This register should be setup before an indirect read transfer is triggered." hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by Writing a value of all.." line.long 0x8 "OSPI_FLASH_CFG_INDIRECT_READ_XFER_START_REG,This register allows the user to define start address of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered." hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "OSPI_FLASH_CFG_INDIRECT_READ_XFER_NUM_BYTES_REG,This register allows the user to define number of bytes to be read of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered." hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_CTRL_REG,This register allows the user to control of the Indirect Write Transfer logic." rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress [status]" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_WATERMARK_REG,This register allows the user to define watermark level for Indirect write transfers. This register should be setup before an indirect write transfer is triggered." hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by Writing a value.." line.long 0x18 "OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_START_REG,This register allows the user to define start address of indirect write transfer which is about to be triggered. This register should be setup before an indirect write transfer is triggered." hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_NUM_BYTES_REG,This register allows the user to define number of bytes to be written of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered." hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "OSPI_FLASH_CFG_INDIRECT_TRIGGER_ADDR_RANGE_REG,This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer. there is no need to detect indirect.." hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." group.long 0x8C++0xB line.long 0x0 "OSPI_FLASH_CFG_FLASH_COMMAND_CTRL_MEM_REG,This register controls the Memory Bank accesses. It also defines the number of bytes intended to get by STIG access configured to use the STIG Memory Bank." hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "OSPI_FLASH_CFG_FLASH_CMD_CTRL_REG,This register controls SPI transactions generated by STIG. It allows the user to define corresponding SPI frame to particular command. triggering the transfer and polling for its completion." hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via Writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "OSPI_FLASH_CFG_FLASH_CMD_ADDR_REG,This register allows the user to define the address of the command using by the STIG controller. This register should be setup while the controller is idle." hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the address used by the command specified in the opcode field [bits 31:24] of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "OSPI_FLASH_CFG_FLASH_RD_DATA_LOWER_REG,This register keeps the last 4 bytes read by STIG SPI access." hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "OSPI_FLASH_CFG_FLASH_RD_DATA_UPPER_REG,This register keeps the last but 4 bytes read by STIG SPI access. This register in conjunction with the Flash Command Read Data Register (Lower) enables the controller to keep 8 last bytes read from the Flash Device.." hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." group.long 0xA8++0x13 line.long 0x0 "OSPI_FLASH_CFG_FLASH_WR_DATA_LOWER_REG,This register takes the first 4 bytes to be written by STIG." hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "OSPI_FLASH_CFG_FLASH_WR_DATA_UPPER_REG,This register takes the bytes ranging from 5 to 8 to be written by STIG." hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "OSPI_FLASH_CFG_POLLING_FLASH_STATUS_REG,This register provides auto-polling data. It acts as the extension for the Write Completion Control Register where full status is not available and any action can be taken only relying on the indication of single.." hexmask.long.byte 0x8 16.--19. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "OSPI_FLASH_CFG_PHY_CONFIGURATION_REG,PHY Configuration Register." bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register." bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and target DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower." hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the target DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "OSPI_FLASH_CFG_DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper." hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." group.long 0xE0++0x7 line.long 0x0 "OSPI_FLASH_CFG_OPCODE_EXT_LOWER_REG,This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by Octal-SPI Configuration Register bit[30]." hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OSPI_FLASH_CFG_OPCODE_EXT_UPPER_REG,This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by Octal-SPI Configuration Register bit[30]. Additionaly. it allows the user to define the Write Enable Latch (WEL) command first.." hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" rgroup.long 0xFC++0x3 line.long 0x0 "OSPI_FLASH_CFG_MODULE_ID_REG,This register provides the IP release number and the configuration data." hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number:0 : OCTAL + PHY Configuration1 : OCTAL Configuration2 : QUAD + PHY Configuration3 : QUAD Configuration" "0: OCTAL + PHY Configuration1 : OCTAL..,?,?,?" tree.end tree.end tree "FSS0_OSPI0_ECC_AGGR" base ad:0x53807000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI0_ECC_AGGR_REV,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "OSPI0_ECC_AGGR_VECTOR,ECC Vector Register." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "OSPI0_ECC_AGGR_STAT,Misc Status." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "OSPI0_ECC_AGGR_RESERVED_SVBUS_j,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "OSPI0_ECC_AGGR_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI0_ECC_AGGR_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "OSPI0_ECC_AGGR_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "OSPI0_ECC_AGGR_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "OSPI0_ECC_AGGR_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI0_ECC_AGGR_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "OSPI0_ECC_AGGR_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "OSPI0_ECC_AGGR_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x200++0xF line.long 0x0 "OSPI0_ECC_AGGR_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "OSPI0_ECC_AGGR_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "OSPI0_ECC_AGGR_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "OSPI0_ECC_AGGR_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "FSS0_PDMEM_GENREGS" base ad:0x5380C000 group.long 0x0++0x3 line.long 0x0 "PDMEM_GENREGS_LOC_j,M8051EW program and external data memory array." hexmask.long 0x0 0.--31. 1. "VAL,Value of element in program and external data memory" tree.end tree "FSS0_WBUF_GENREGS" base ad:0x5380E000 group.long 0x0++0x3 line.long 0x0 "WBUF_GENREGS_LOC_j,FOTA write buffer array." hexmask.long 0x0 0.--31. 1. "VAL,Value of element in FOTA write buffer" tree.end tree.end tree "FSS_TIMEOUT_CFG0" base ad:0x53400000 rgroup.long 0x0++0xB line.long 0x0 "FSS_TIMEOUT_CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "FSS_TIMEOUT_CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "FSS_TIMEOUT_CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Current number of occupied slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Current number of occupied slots in the read scoreboard" group.long 0xC++0xF line.long 0x0 "FSS_TIMEOUT_CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "FSS_TIMEOUT_CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,The value of external flush input" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,SW control and indicator for whether the gasket is in flush mode. 4'b1111 - Flush mode All other values - Normal mode." line.long 0x8 "FSS_TIMEOUT_CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon. Each transaction can be outstanding for 2-3 eons before it times out." line.long 0xC "FSS_TIMEOUT_CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer. It increments once per clock cycle when the gasket is enabled." group.long 0x20++0x17 line.long 0x0 "FSS_TIMEOUT_CFG_ERR_RAW,This register contains the masked interrupt bits." bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "FSS_TIMEOUT_CFG_ERR,This register contains the masked interrupt bits." bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "FSS_TIMEOUT_CFG_ERR_MSK_SET,This register contains interrupt mask set bits." bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "FSS_TIMEOUT_CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits." bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "FSS_TIMEOUT_CFG_ERR_TM_INFO,This register contains information about timeout interrupts." bitfld.long 0x10 0.--1. "CNT,This field contains information about how many transactions have timed out since the last one was serviced. Writing to this register decrements the contents by the value written. The value saturates at 3." "0,1,2,3" line.long 0x14 "FSS_TIMEOUT_CFG_ERR_UN_INFO,This register contains information about unexpected interrupts." bitfld.long 0x14 0.--1. "CNT,This field contains information about how many unexpected responses have been received since the last one was serviced. Writing to this register decrements the contents by the value written. The value saturates at 3." "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "FSS_TIMEOUT_CFG_ERR_VAL,This register contains information about transaction that caused the interrupt." hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator. 0-write. 1-read." "0,1" bitfld.long 0x0 1. "TYP,Error Type Indicator. 0-transaction timeout. 1-unexpected response." "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator. If this field is a 1 then the contents of this and the below registers is considered valid: it contains the information about the transaction that was captured. If this field is 0 then this and the other listed registers are not.." "0,1" line.long 0x4 "FSS_TIMEOUT_CFG_ERR_TAG,This register contains information about transaction that caused the interrupt." hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator consisting of replacement CID for timeout error or SID/RID for unexpected response error." hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator. This is the original command id and is only valid on timeout error." line.long 0x8 "FSS_TIMEOUT_CFG_ERR_BYT,This register contains information about transaction that caused the interrupt." hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt. For timeout error this is the number of bytes that were not returned." hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt. This field represents the transaction cbytecnt of the original command." line.long 0xC "FSS_TIMEOUT_CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt." hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the address for the captured transaction. This is field is only valid for timeout error." line.long 0x10 "FSS_TIMEOUT_CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt." hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the address for the captured transaction. This is field is only valid for timeout error. If the address width is less than 32 then the bits above the address range will be read as 0." tree.end tree "GPIO" base ad:0x0 tree "GPIO0" base ad:0x52000000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register." bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register." bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register." hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register." hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register." hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register." hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register." hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR23,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR45,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR67,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR8,Direction Register." hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register." hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register." hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register." hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register." hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register." hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register." hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register." hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register." hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register." hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO1" base ad:0x52001000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register." bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register." bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register." hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register." hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register." hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register." hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register." hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR23,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR45,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR67,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR8,Direction Register." hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register." hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register." hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register." hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register." hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register." hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register." hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register." hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register." hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register." hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO2" base ad:0x52002000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register." bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register." bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register." hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register." hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register." hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register." hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register." hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR23,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR45,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR67,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR8,Direction Register." hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register." hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register." hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register." hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register." hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register." hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register." hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register." hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register." hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register." hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO3" base ad:0x52003000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register." bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register." bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register." hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register." hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register." hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register." hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register." hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR23,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR45,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR67,Direction Register." hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register." hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not effect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register." hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register." hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register." hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register." hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register." hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register." hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register." hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register." hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO_DIR8,Direction Register." hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register." hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not effect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register." hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register." hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register." hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register." hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register." hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register." hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register." hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register." hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree.end tree "GPIO_XBAR_INTR" base ad:0x52E02000 rgroup.long 0x0++0x3 line.long 0x0 "GPIO_XBAR_INTR_PID,Identification register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,Rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "GPIO_XBAR_INTR_MUXCNTL_j,Interrupt mux control register." bitfld.long 0x0 16. "INT_ENABLE,Interrupt j Output Enable." "0,1" hexmask.long.byte 0x0 0.--7. 1. "MUX_CNTL,Mux Control for Interrupt j." tree.end tree "HSM0_HSM" base ad:0x0 tree "HSM0_HSM_AES" base ad:0xCE006000 group.long 0x0++0x7F line.long 0x0 "HSM_AES_S_KEY2_6,XTS second key / CBC-MAC third key (Read-returns0s)." hexmask.long 0x0 0.--31. 1. "KEY,key data" line.long 0x4 "HSM_AES_S_KEY2_7,XTS second key (MSW for 256-bit key) / CBC-MAC third key (MSW) (Read-returns0s)." hexmask.long 0x4 0.--31. 1. "KEY,key data" line.long 0x8 "HSM_AES_S_KEY2_4,XTS / CCM second key / CBC-MAC third key (LSW) (Read-returns0s)." hexmask.long 0x8 0.--31. 1. "KEY,key data" line.long 0xC "HSM_AES_S_KEY2_5,XTS second key (MSW for 192-bit key) / CBC-MAC third key (Read-returns0s)." hexmask.long 0xC 0.--31. 1. "KEY,key data" line.long 0x10 "HSM_AES_S_KEY2_2,XTS / CCM / CBC-MAC second key / Hash Key input (Read-returns0s)." hexmask.long 0x10 0.--31. 1. "KEY,key data" line.long 0x14 "HSM_AES_S_KEY2_3,XTS second key (MSW for 128-bit key) + CCM/CBC-MAC second key (MSW) / Hash Key input (MSW) (Read-returns0s)." hexmask.long 0x14 0.--31. 1. "KEY,key data" line.long 0x18 "HSM_AES_S_KEY2_0,XTS / CCM / CBC-MAC second key (LSW) / Hash Key input (LSW) (Read-returns0s)." hexmask.long 0x18 0.--31. 1. "KEY,key data" line.long 0x1C "HSM_AES_S_KEY2_1,XTS / CCM / CBC-MAC second key / Hash Key input (Read-returns0s)." hexmask.long 0x1C 0.--31. 1. "KEY,key data" line.long 0x20 "HSM_AES_S_KEY1_6,Key (LSW for 256-bit key) (Read-returns0s)." hexmask.long 0x20 0.--31. 1. "KEY,key data" line.long 0x24 "HSM_AES_S_KEY1_7,Key (MSW for 256-bit key) (Read-returns0s)." hexmask.long 0x24 0.--31. 1. "KEY,key data" line.long 0x28 "HSM_AES_S_KEY1_4,Key (LSW for 192-bit key) (Read-returns0s)." hexmask.long 0x28 0.--31. 1. "KEY,key data" line.long 0x2C "HSM_AES_S_KEY1_5,Key (MSW for 192-bit key) (Read-returns0s)." hexmask.long 0x2C 0.--31. 1. "KEY,key data" line.long 0x30 "HSM_AES_S_KEY1_2,Key (Read-returns0s)." hexmask.long 0x30 0.--31. 1. "KEY,key data" line.long 0x34 "HSM_AES_S_KEY1_3,Key (MSW for 128-bit key) (Read-returns0s)." hexmask.long 0x34 0.--31. 1. "KEY,key data" line.long 0x38 "HSM_AES_S_KEY1_0,Key (LSW for 128-bit key) (Read-returns0s)." hexmask.long 0x38 0.--31. 1. "KEY,key data" line.long 0x3C "HSM_AES_S_KEY1_1,Key (Read-returns0s)." hexmask.long 0x3C 0.--31. 1. "KEY,key data" line.long 0x40 "HSM_AES_S_IV_IN_0,Initialization Vector input (LSW)." hexmask.long 0x40 0.--31. 1. "DATA,IV data" line.long 0x44 "HSM_AES_S_IV_IN_1,Initialization vector input." hexmask.long 0x44 0.--31. 1. "DATA,IV data" line.long 0x48 "HSM_AES_S_IV_IN_2,Initialization vector input ." hexmask.long 0x48 0.--31. 1. "DATA,IV data" line.long 0x4C "HSM_AES_S_IV_IN_3,Initialization Vector input (MSW)" hexmask.long 0x4C 0.--31. 1. "DATA,IV data" line.long 0x50 "HSM_AES_S_CTRL,Register determines the mode of operation of the AES Engine." rbitfld.long 0x50 31. "CONTEXT_READY,If'1' this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context." "0,1" rbitfld.long 0x50 30. "SAVE_CONTEXT_READY,If'1' this read-only status bit indicates that an AES authentication TAG and/or IV block[s] is/are available for the host to retrieve. This bit is only asserted if the'save_context' bit is set to'1'. The bit is mutual exclusive with.." "0,1" newline bitfld.long 0x50 29. "SAVE_CONTEXT,This bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set context output DMA and/or interrupt will be asserted if the operation is finished and related signals are enabled." "0,1" bitfld.long 0x50 22.--24. "CCM_M,Defines 'M' that indicated the length of the authentication field for CCM operations; the authentication field length equals two times [the value of CCM-M plus one]. Note that the AES Engine always returns a 128-bit authentication field of which.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 19.--21. "CCM_L,Defines 'L' that indicated the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. Supported values for L are [programmed value]: 2 [1] 4 [3] and 8 [7]." "0,1,2,3,4,5,6,7" bitfld.long 0x50 18. "CCM,AES-CCM is selected this is a combined mode using AES for both authentication and encryption. No additional mode selection is required. 0 Other mode selected 1 ccm mode selected" "0,1" newline bitfld.long 0x50 16.--17. "GCM,AES-GCM mode is selected.this is a combined mode using the Galois field multiplier GF[2^128] for authentication and AES-CTR mode for encryption the bits specify the GCM mode. 0x0 No operation 0x1 GHASH with H loaded and Y0-encrypted forced to zero.." "0,1,2,3" bitfld.long 0x50 15. "CBCMAC,AES-CBC MAC is selected the Direction bit must be set to'1' for this mode. 0 Other mode selected 1 cbcmac mode selected" "0,1" newline bitfld.long 0x50 14. "F9,AES f9 mode is selected the AES key size must be set to 128-bit for this mode. 0 Other mode selected 1 f9 selected" "0,1" bitfld.long 0x50 13. "F8,AES f8 mode is selected the AES key size must be set to 128-bit for this mode. 0 Other mode selected 1 f8 selected" "0,1" newline bitfld.long 0x50 11.--12. "XTS,AES-XTS operation is selected; the bits specify the XTS mode.01 = Previous/intermediate tweak value and'j' loaded [value is loaded via IV j is loaded via the AAD length register] 0x0 No operation 0x1 Previous/intermediate tweak value and'j' loaded.." "?,1: Previous/intermediate tweak value and'j' loaded..,?,?" bitfld.long 0x50 10. "CFB,full block AES cipher feedback mode [CFB128] is selected. 0 other mode selected 1 cfb selected" "0,1" newline bitfld.long 0x50 9. "ICM,AES integer counter mode [ICM] is selected this is a counter mode with a 16-bit wide counter. 0 Other mode selected. 1 ICM mode selected" "0,1" bitfld.long 0x50 7.--8. "CTR_WIDTH,Specifies the counter width for AES-CTR mode 0x0 Counter is 32 bits 0x1 Counter is 64 bits 0x2 Counter is 128 bits 0x3 Counter is 192 bits" "0,1,2,3" newline bitfld.long 0x50 6. "CTR,Tthis bit must also be set for GCM and CCM when encryption/decryption is required. 0 Other mode selected 1 Counter mode" "0,1" bitfld.long 0x50 5. "MODE,Ecb/cbc mode 0 ecb mode 1 cbc mode" "0,1" newline bitfld.long 0x50 3.--4. "KEY_SIZE,key size 0x0 reserved 0x1 Key is 128 bits. 0x2 Key is 192 bits 0x3 Key is 256" "0,1,2,3" bitfld.long 0x50 2. "DIRECTION,If set to'1' an encrypt operation is performed. If set to'0' a decrypt operation is performed. Read0 decryption is selected Read1 Encryption is selected" "0,1" newline rbitfld.long 0x50 1. "INPUT_READY,If'1' this read-only status bit indicates that the 16-byte input buffer is empty and the host is permitted to write the next block of data." "0,1" rbitfld.long 0x50 0. "OUTPUT_READY,If'1' this read-only status bit indicates that an AES output block is available for the host to retrieve." "0,1" line.long 0x54 "HSM_AES_S_C_LENGTH_0,Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (2^61- 1) bytes are allowed. For.." hexmask.long 0x54 0.--31. 1. "RESERVED,Data length [LSW]" line.long 0x58 "HSM_AES_S_C_LENGTH_1,Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (2^61- 1) bytes are allowed. For.." hexmask.long 0x58 0.--28. 1. "LENGTH,Data length [MSW] length registers [LSW and MSW] store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to [2^61 - 1] bytes are allowed. For GCM any.." line.long 0x5C "HSM_AES_S_AUTH_LENGTH,AAD data length. The authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM) Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any value up to (2^32 -.." hexmask.long 0x5C 0.--31. 1. "AUTH,data" line.long 0x60 "HSM_AES_S_DATA_IN_0,Data register to read and write plaintext/ciphertext (MSW)." hexmask.long 0x60 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x64 "HSM_AES_S_DATA_IN_1,Data register to read and write plaintext/ciphertext." hexmask.long 0x64 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x68 "HSM_AES_S_DATA_IN_2,Data register to read and write plaintext/ciphertext." hexmask.long 0x68 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x6C "HSM_AES_S_DATA_IN_3,Data register to read and write plaintext/ciphertext (LSW)." hexmask.long 0x6C 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x70 "HSM_AES_S_TAG_OUT_0,Hash result (MSW)." hexmask.long 0x70 0.--31. 1. "HASH,Hash result [MSW]" line.long 0x74 "HSM_AES_S_TAG_OUT_1,Hash result (MSW)." hexmask.long 0x74 0.--31. 1. "HASH,Hash result [MSW]" line.long 0x78 "HSM_AES_S_TAG_OUT_2,Hash result (MSW)." hexmask.long 0x78 0.--31. 1. "HASH,Hash result [MSW]" line.long 0x7C "HSM_AES_S_TAG_OUT_3,Hash result (MSW)." hexmask.long 0x7C 0.--31. 1. "HASH,Hash result [LSW]" rgroup.long 0x80++0x3 line.long 0x0 "HSM_AES_S_REVISION,Register AES_REVISION." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current. Read0x0 Legacy ASP or WTBU scheme Read0x1 Highlander 0.8 scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner. RTL follows a numbering such as X.Y.R.Z which are explained in this table. R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner. X changes ONLY when: [1] There is a major feature addition. An example would be adding Master Mode to Utopia Level2. The Func field [or Class/Type in old PID format] will remain the same. X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers. Read0x0 Non custom [standard] revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner. Y changes ONLY when: [1] Features are scaled [up or down]. Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP.." group.long 0x84++0xF line.long 0x0 "HSM_AES_S_SYSCONFIG,Register AES_SYSCONFIG.This register configures the DMA signals and controls the IDLE and reset logic." bitfld.long 0x0 12. "K3,If this bit is set to zero a regular cryptographic operation is performed.This bit may be set to one only if bit directbusen of this register and bit key_enc of this register are cleared to zero. If this bit is one the K3 key is used as key for the.." "0,1" bitfld.long 0x0 11. "KEY_ENC,If this bit is set to zero a regular cryptographic operation is performed.This bit may be set to one only if bit directbusen of this register is cleared to zero. If this bit is'1' the KEK [see description of bit kek_mode] key is XOR-ed with a.." "0,1" newline bitfld.long 0x0 10. "KEK_MODE,If this bit is zero the direct key is used directly for the selected cryptographic operation if it is selected by enabling directbusen of this register. If the direct key is not selected a regular operation is performed.This bit may be set to.." "0,1" bitfld.long 0x0 9. "MAP_CONTEXT_OUT_ON_DATA_OUT,If set to '1' the two context out requests [dma_req_context_out_en Bit [8] above and context_out interrupt enable Bit [3] of AES_IRQENABLE register] are mapped on the corresponding data output request bit. In this case the.." "0,1" newline bitfld.long 0x0 8. "DMA_REQ_CONTEXT_OUT_EN,If set to'1' the DMA context output request is enabled [for context data out e.g. TAG for authentication modes]. 0 Dma disabled 1 Dma enabled" "0,1" bitfld.long 0x0 7. "DMA_REQ_CONTEXT_IN_EN,If set to'1' the DMA context request is enabled. 0 Dma disabled 1 Dma enabled" "0,1" newline bitfld.long 0x0 6. "DMA_REQ_DATA_OUT_EN,If set to'1' the DMA output request is enabled. 0 Dma disabled 1 Dma enabled" "0,1" bitfld.long 0x0 5. "DMA_REQ_DATA_IN_EN,If set to'1' the DMA input request is enabled. 0 Dma disabled 1 Dma enabled" "0,1" newline bitfld.long 0x0 4. "DIRECTBUSEN,keys from register or directbus input0: Use the key registers 1: Use the directbus" "?,1: Use the directbus" bitfld.long 0x0 2.--3. "SIDLE,Sidle mode0x0: Force Idle mode. 0x1: No idle 0x2: Smart Idle mode 0x3: reserved" "?,1: No idle,2: Smart Idle mode,3: reserved" newline bitfld.long 0x0 1. "SOFTRESET,Softreset0: No operation. 1: When '1' starts softreset sequnce." "?,1: When '1'" bitfld.long 0x0 0. "AUTOIDLE,Autoidle 0: When '0' internal clocks are running. 1: When '1' internal clocks are cut." "0: When '0',1: When '1'" line.long 0x4 "HSM_AES_S_SYSSTATUS,System status." bitfld.long 0x4 0. "RESETDONE,Reset Done" "0,1" line.long 0x8 "HSM_AES_S_IRQSTATUS,This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted." bitfld.long 0x8 3. "CONTEXT_OUT,This bit indicates authentication tag [and IV] interrupt[s] is/are active and triggers the interrupt output." "0,1" bitfld.long 0x8 2. "DATA_OUT,This bit indicates data output interrupt is active and triggers the interrupt output." "0,1" newline bitfld.long 0x8 1. "DATA_IN,This bit indicates data input interrupt is active and triggers the interrupt output." "0,1" bitfld.long 0x8 0. "CONTEX_IN,This bit indicates context interrupt is active and triggers the interrupt output." "0,1" line.long 0xC "HSM_AES_S_IRQENABLE,This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to '1'. An interrupt that is enabled.." bitfld.long 0xC 3. "CONTEXT_OUT,This bit indicates authentication tag [and IV] interrupt[s] is/are active and triggers the interrupt output." "0,1" bitfld.long 0xC 2. "DATA_OUT,This bit indicates data output interrupt is active and triggers the interrupt output." "0,1" newline bitfld.long 0xC 1. "DATA_IN,This bit indicates data input interrupt is active and triggers the interrupt output." "0,1" bitfld.long 0xC 0. "CONTEX_IN,This bit indicates context interrupt is active and triggers the interrupt output." "0,1" rgroup.long 0x94++0x3 line.long 0x0 "HSM_AES_S_DIRTYBITS,Read/Write Access control." bitfld.long 0x0 3. "P_DIRTY,This bit is set to 1 by the module if any of the AES P_* registers is written." "0,1" bitfld.long 0x0 2. "P_ACCESS,This bit is set to 1 by the module if any of the AES P_* registers is read." "0,1" newline bitfld.long 0x0 1. "S_DIRTY,This bit is set to 1 by the module if any of the AES S_* registers is written except AES_S_DIRTYBITS and AES_S_LOCKDOWN." "0,1" bitfld.long 0x0 0. "S_ACCESS,This bit is set to 1 by the module if any of the AES S_* registers is read except AES_S_DIRTYBITS and AES_S_LOCKDOWN." "0,1" group.long 0x98++0x3 line.long 0x0 "HSM_AES_S_LOCKDOWN,Use this register to prevent further access /Lock Register." bitfld.long 0x0 5. "LENGTH_LOCK,If set to'1' the DES_P length registers can not be written [this lock involves word address from 0x1054 to 0x105c]." "0,1" bitfld.long 0x0 4. "CONTROL_LOCK,If set to'1' the AES_P control register can not be written [this lock involves word address 0x1050]." "0,1" newline bitfld.long 0x0 3. "IV_LOCK,If set to'1' the AES_P IV registers cannot be written [this lock involves word addresses 0x1040 up to 0x104C]." "0,1" bitfld.long 0x0 2. "KEY3_LOCK,If set to'1' the AES_P key3 registers cannot be written [this lock involves word addresses 0x1030 up to 0x103C]." "0,1" newline bitfld.long 0x0 1. "KEY2_LOCK,If set to'1' the AES_P key2 registers cannot be written [this lock involves word addresses 0x1020 up to 0x102C]." "0,1" bitfld.long 0x0 0. "KEY_LOCK,If set to'1' the AES_P key registers cannot be written [this lock involves word addresses 0x1000 up to 0x101C]." "0,1" group.long 0x1000++0x7F line.long 0x0 "HSM_AES_P_KEY2_6,XTS second key / CBC-MAC third key (Read-returns0s)." hexmask.long 0x0 0.--31. 1. "KEY,key data" line.long 0x4 "HSM_AES_P_KEY2_7,XTS second key (MSW for 256-bit key) / CBC-MAC third key (MSW) (Read-returns0s)." hexmask.long 0x4 0.--31. 1. "KEY,key data" line.long 0x8 "HSM_AES_P_KEY2_4,XTS / CCM second key / CBC-MAC third key (LSW) (Read-returns0s)." hexmask.long 0x8 0.--31. 1. "KEY,key data" line.long 0xC "HSM_AES_P_KEY2_5,XTS second key (MSW for 192-bit key) / CBC-MAC third key (Read-returns0s)." hexmask.long 0xC 0.--31. 1. "KEY,key data" line.long 0x10 "HSM_AES_P_KEY2_2,XTS / CCM / CBC-MAC second key / Hash Key input (Read-returns0s)." hexmask.long 0x10 0.--31. 1. "KEY,key data" line.long 0x14 "HSM_AES_P_KEY2_3,XTS second key (MSW for 128-bit key) + CCM/CBC-MAC second key (MSW) / Hash Key input (MSW) (Read-returns0s)." hexmask.long 0x14 0.--31. 1. "KEY,key data" line.long 0x18 "HSM_AES_P_KEY2_0,XTS / CCM / CBC-MAC second key (LSW) / Hash Key input (LSW) (Read-returns0s)." hexmask.long 0x18 0.--31. 1. "KEY,key data" line.long 0x1C "HSM_AES_P_KEY2_1,XTS / CCM / CBC-MAC second key / Hash Key input (Read-returns0s)." hexmask.long 0x1C 0.--31. 1. "KEY,key data" line.long 0x20 "HSM_AES_P_KEY1_6,Key (LSW for 256-bit key) (Read-returns0s)." hexmask.long 0x20 0.--31. 1. "KEY,key data" line.long 0x24 "HSM_AES_P_KEY1_7,Key (MSW for 256-bit key) (Read-returns0s)." hexmask.long 0x24 0.--31. 1. "KEY,key data" line.long 0x28 "HSM_AES_P_KEY1_4,Key (LSW for 192-bit key) (Read-returns0s)." hexmask.long 0x28 0.--31. 1. "KEY,key data" line.long 0x2C "HSM_AES_P_KEY1_5,Key (MSW for 192-bit key) (Read-returns0s)." hexmask.long 0x2C 0.--31. 1. "KEY,key data" line.long 0x30 "HSM_AES_P_KEY1_2,Key (Read-returns0s)." hexmask.long 0x30 0.--31. 1. "KEY,key data" line.long 0x34 "HSM_AES_P_KEY1_3,Key (MSW for 128-bit key) (Read-returns0s)." hexmask.long 0x34 0.--31. 1. "KEY,key data" line.long 0x38 "HSM_AES_P_KEY1_0,Key (LSW for 128-bit key) (Read-returns0s)." hexmask.long 0x38 0.--31. 1. "KEY,key data" line.long 0x3C "HSM_AES_P_KEY1_1,Key (Read-returns0s)." hexmask.long 0x3C 0.--31. 1. "KEY,key data" line.long 0x40 "HSM_AES_P_IV_IN_0,Initialization Vector input (LSW)." hexmask.long 0x40 0.--31. 1. "DATA,IV data" line.long 0x44 "HSM_AES_P_IV_IN_1,Initialization vector input." hexmask.long 0x44 0.--31. 1. "DATA,IV data" line.long 0x48 "HSM_AES_P_IV_IN_2,Initialization vector input." hexmask.long 0x48 0.--31. 1. "DATA,IV data" line.long 0x4C "HSM_AES_P_IV_IN_3,Initialization Vector input (MSW)." hexmask.long 0x4C 0.--31. 1. "DATA,IV data" line.long 0x50 "HSM_AES_P_CTRL,Register determines the mode of operation of the AES Engine." rbitfld.long 0x50 31. "CONTEXT_READY,If'1' this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context." "0,1" rbitfld.long 0x50 30. "SAVE_CONTEXT_READY,If'1' this read-only status bit indicates that an AES authentication TAG and/or IV block[s] is/are available for the host to retrieve. This bit is only asserted if the'save_context' bit is set to'1'. The bit is mutual exclusive with.." "0,1" newline bitfld.long 0x50 29. "SAVE_CONTEXT,This bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set context output DMA and/or interrupt will be asserted if the operation is finished and related signals are enabled." "0,1" bitfld.long 0x50 22.--24. "CCM_M,Defines 'M' that indicated the length of the authentication field for CCM operations; the authentication field length equals two times [the value of CCM-M plus one]. Note that the AES Engine always returns a 128-bit authentication field of which.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 19.--21. "CCM_L,Defines 'L' that indicated the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. Supported values for L are [programmed value]: 2 [1] 4 [3] and 8 [7]." "0,1,2,3,4,5,6,7" bitfld.long 0x50 18. "CCM,AES-CCM is selected this is a combined mode using AES for both authentication and encryption. No additional mode selection is required. 0 Other mode selected 1 ccm mode selected" "0,1" newline bitfld.long 0x50 16.--17. "GCM,AES-GCM mode is selected.this is a combined mode using the Galois field multiplier GF[2^128] for authentication and AES-CTR mode for encryption the bits specify the GCM mode. 0x0 No operation 0x1 GHASH with H loaded and Y0-encrypted forced to zero.." "0,1,2,3" bitfld.long 0x50 15. "CBCMAC,AES-CBC MAC is selected the Direction bit must be set to'1' for this mode. 0 Other mode selected 1 cbcmac mode selected" "0,1" newline bitfld.long 0x50 14. "F9,AES f9 mode is selected the AES key size must be set to 128-bit for this mode. 0 Other mode selected 1 f9 selected" "0,1" bitfld.long 0x50 13. "F8,AES f8 mode is selected the AES key size must be set to 128-bit for this mode. 0 Other mode selected 1 f8 selected" "0,1" newline bitfld.long 0x50 11.--12. "XTS,AES-XTS operation is selected; the bits specify the XTS mode.01 = Previous/intermediate tweak value and'j' loaded [value is loaded via IV j is loaded via the AAD length register] 0x0 No operation 0x1 Previous/intermediate tweak value and'j' loaded.." "?,1: Previous/intermediate tweak value and'j' loaded..,?,?" bitfld.long 0x50 10. "CFB,full block AES cipher feedback mode [CFB128] is selected. 0 other mode selected 1 cfb selected" "0,1" newline bitfld.long 0x50 9. "ICM,AES integer counter mode [ICM] is selected this is a counter mode with a 16-bit wide counter. 0 Other mode selected. 1 ICM mode selected" "0,1" bitfld.long 0x50 7.--8. "CTR_WIDTH,Specifies the counter width for AES-CTR mode 0x0 Counter is 32 bits 0x1 Counter is 64 bits 0x2 Counter is 128 bits 0x3 Counter is 192 bits" "0,1,2,3" newline bitfld.long 0x50 6. "CTR,Tthis bit must also be set for GCM and CCM when encryption/decryption is required. 0 Other mode selected 1 Counter mode" "0,1" bitfld.long 0x50 5. "MODE,Ecb/cbc mode 0 ecb mode 1 cbc mode" "0,1" newline bitfld.long 0x50 3.--4. "KEY_SIZE,key size 0x0 reserved 0x1 Key is 128 bits. 0x2 Key is 192 bits 0x3 Key is 256" "0,1,2,3" bitfld.long 0x50 2. "DIRECTION,If set to'1' an encrypt operation is performed. If set to'0' a decrypt operation is performed. Read0 decryption is selected Read1 Encryption is selected" "0,1" newline rbitfld.long 0x50 1. "INPUT_READY,If'1' this read-only status bit indicates that the 16-byte input buffer is empty and the host is permitted to write the next block of data." "0,1" rbitfld.long 0x50 0. "OUTPUT_READY,If'1' this read-only status bit indicates that an AES output block is available for the host to retrieve." "0,1" line.long 0x54 "HSM_AES_P_C_LENGTH_0,Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (2^61-1) bytes are allowed. For.." hexmask.long 0x54 0.--31. 1. "RESERVED,Data length [LSW]" line.long 0x58 "HSM_AES_P_C_LENGTH_1,Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (2^61-1) bytes are allowed. For.." hexmask.long 0x58 0.--28. 1. "LENGTH,Data length [MSW] length registers [LSW and MSW] store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to [2^61 - 1] bytes are allowed. For GCM any.." line.long 0x5C "HSM_AES_P_AUTH_LENGTH,AAD data length. The authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM) Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any value up to (2^32 -.." hexmask.long 0x5C 0.--31. 1. "AUTH,data" line.long 0x60 "HSM_AES_P_DATA_IN_0,Data register to read and write plaintext/ciphertext (MSW)." hexmask.long 0x60 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x64 "HSM_AES_P_DATA_IN_1,Data register to read and write plaintext/ciphertext." hexmask.long 0x64 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x68 "HSM_AES_P_DATA_IN_2,Data register to read and write plaintext/ciphertext." hexmask.long 0x68 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x6C "HSM_AES_P_DATA_IN_3,Data register to read and write plaintext/ciphertext (LSW)." hexmask.long 0x6C 0.--31. 1. "DATA,Data to encrypt/decrypt" line.long 0x70 "HSM_AES_P_TAG_OUT_0,Hash result (MSW)." hexmask.long 0x70 0.--31. 1. "HASH,Hash result [MSW]" line.long 0x74 "HSM_AES_P_TAG_OUT_1,Hash result (MSW)." hexmask.long 0x74 0.--31. 1. "HASH,Hash result [MSW]" line.long 0x78 "HSM_AES_P_TAG_OUT_2,Hash result (MSW)." hexmask.long 0x78 0.--31. 1. "HASH,Hash result [MSW]" line.long 0x7C "HSM_AES_P_TAG_OUT_3,Hash result (MSW)." hexmask.long 0x7C 0.--31. 1. "HASH,Hash result [LSW]" rgroup.long 0x1080++0x3 line.long 0x0 "HSM_AES_P_REVISION,Register AES_REVISION." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current. Read0x0 Legacy ASP or WTBU scheme Read0x1 Highlander 0.8 scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner. RTL follows a numbering such as X.Y.R.Z which are explained in this table. R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner. X changes ONLY when: [1] There is a major feature addition. An example would be adding Master Mode to Utopia Level2. The Func field [or Class/Type in old PID format] will remain the same. X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers. Read0x0 Non custom [standard] revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner. Y changes ONLY when: [1] Features are scaled [up or down]. Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP.." group.long 0x1084++0xF line.long 0x0 "HSM_AES_P_SYSCONFIG,Register AES_SYSCONFIG.This register configures the DMA signals and controls the IDLE and reset logic." bitfld.long 0x0 9. "MAP_CONTEXT_OUT_ON_DATA_OUT,If set to '1' the two context out requests [dma_req_context_out_en Bit [8] above and context_out interrupt enable Bit [3] of AES_IRQENABLE register] are mapped on the corresponding data output request bit. In this case the.." "0,1" bitfld.long 0x0 8. "DMA_REQ_CONTEXT_OUT_EN,If set to'1' the DMA context output request is enabled [for context data out e.g. TAG for authentication modes]. 0 Dma disabled 1 Dma enabled" "0,1" newline bitfld.long 0x0 7. "DMA_REQ_CONTEXT_IN_EN,If set to'1' the DMA context request is enabled. 0 Dma disabled 1 Dma enabled" "0,1" bitfld.long 0x0 6. "DMA_REQ_DATA_OUT_EN,If set to'1' the DMA output request is enabled. 0 Dma disabled 1 Dma enabled" "0,1" newline bitfld.long 0x0 5. "DMA_REQ_DATA_IN_EN,If set to'1' the DMA input request is enabled. 0 Dma disabled 1 Dma enabled" "0,1" bitfld.long 0x0 4. "DIRECTBUSEN,keys from register or directbus input0: Use the key registers 1: Use the directbus" "?,1: Use the directbus" newline bitfld.long 0x0 2.--3. "SIDLE,Sidle mode0x0: Force Idle mode. 0x1: No idle 0x2: Smart Idle mode 0x3: reserved" "?,1: No idle,2: Smart Idle mode,3: reserved" bitfld.long 0x0 1. "SOFTRESET,Softreset0: No operation. 1: When '1' starts softreset sequnce." "?,1: When '1'" newline bitfld.long 0x0 0. "AUTOIDLE,Autoidle 0: When '0' internal clocks are running. 1: When '1' internal clocks are cut." "0: When '0',1: When '1'" line.long 0x4 "HSM_AES_P_SYSSTATUS,System status." bitfld.long 0x4 0. "RESETDONE,Indicates reset done" "0,1" line.long 0x8 "HSM_AES_P_IRQSTATUS,This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted." bitfld.long 0x8 3. "CONTEXT_OUT,This bit indicates authentication tag [and IV] interrupt[s] is/are active and triggers the interrupt output." "0,1" bitfld.long 0x8 2. "DATA_OUT,This bit indicates data output interrupt is active and triggers the interrupt output." "0,1" newline bitfld.long 0x8 1. "DATA_IN,This bit indicates data input interrupt is active and triggers the interrupt output." "0,1" bitfld.long 0x8 0. "CONTEX_IN,This bit indicates context interrupt is active and triggers the interrupt output." "0,1" line.long 0xC "HSM_AES_P_IRQENABLE,This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to '1'. An interrupt that is enabled.." bitfld.long 0xC 3. "CONTEXT_OUT,This bit indicates authentication tag [and IV] interrupt[s] is/are active and triggers the interrupt output." "0,1" bitfld.long 0xC 2. "DATA_OUT,This bit indicates data output interrupt is active and triggers the interrupt output." "0,1" newline bitfld.long 0xC 1. "DATA_IN,This bit indicates data input interrupt is active and triggers the interrupt output." "0,1" bitfld.long 0xC 0. "CONTEX_IN,This bit indicates context interrupt is active and triggers the interrupt output." "0,1" tree.end tree "HSM0_HSM_DTHE" base ad:0xCE000000 group.byte 0x0++0x0 line.byte 0x0 "HSM_DTHE_S_EIP_CONFIG,This register is used for secured request configuration." bitfld.byte 0x0 0.--1. "CONFIG,This register is secured request configuration.Writing 3 to this register enables the mreqsecure to enable the write to S_SYSCONFIG register in AES and SHA." "0,1,2,3" group.long 0x10++0x3 line.long 0x0 "HSM_DTHE_S_SHA_IMST,Secured SHA Interrupt Mask Set Register." bitfld.long 0x0 2. "DIN,Data in: this interrupt is raised when DMA writes last word of input data to internal FIFO of the engine" "0,1" bitfld.long 0x0 1. "COUT,Context out: this interrupt is raised when DMA complets the output context movement from internal register" "0,1" bitfld.long 0x0 0. "CIN,context in: this interrupt is raised when DMA complets Context write to internal register" "0,1" rgroup.long 0x14++0x7 line.long 0x0 "HSM_DTHE_S_SHA_IRIS,Secured SHA Interrupt Raw Interrupt Status Register." bitfld.long 0x0 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x0 1. "COUT,Context output is done" "0,1" bitfld.long 0x0 0. "CIN,context input is done" "0,1" line.long 0x4 "HSM_DTHE_S_SHA_IMIS,Secured SHA Interrupt Masked interrupt Status Registe." bitfld.long 0x4 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x4 1. "COUT,Context output is done" "0,1" bitfld.long 0x4 0. "CIN,context input is done" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "HSM_DTHE_S_SHA_ICIS,Secured SHA Interrupt Clear Interrupt Status Register." bitfld.long 0x0 2. "DIN,Clear'input Data movement done' flag" "0,1" bitfld.long 0x0 1. "COUT,Clear'Context output done' flag" "0,1" bitfld.long 0x0 0. "CIN,Clear'context input done' flag" "0,1" group.long 0x20++0x3 line.long 0x0 "HSM_DTHE_S_AES_IMST,Secured AES Interrupt Mask Set Register." bitfld.long 0x0 3. "DOUT,Data out: this interrupt is raised when DMA finishes Writing last word of the process result" "0,1" bitfld.long 0x0 2. "DIN,Data in: this interrupt is raised when DMA writes last word of input data to internal FIFO of the engine" "0,1" bitfld.long 0x0 1. "COUT,Context out: this interrupt is raised when DMA complets the output context movement from internal register" "0,1" bitfld.long 0x0 0. "CIN,context in: this interrupt is raised when DMA complets Context write to internal register" "0,1" rgroup.long 0x24++0x7 line.long 0x0 "HSM_DTHE_S_AES_IRIS,Secured AES Interrupt Raw Interrupt Status Register." bitfld.long 0x0 3. "DOUT,Output Data movement is done" "0,1" bitfld.long 0x0 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x0 1. "COUT,Context output is done" "0,1" bitfld.long 0x0 0. "CIN,context input is done" "0,1" line.long 0x4 "HSM_DTHE_S_AES_IMIS,Secured AES Interrupt Masked interrupt Status Register." bitfld.long 0x4 3. "DOUT,Output Data movement is done" "0,1" bitfld.long 0x4 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x4 1. "COUT,Context output is done" "0,1" bitfld.long 0x4 0. "CIN,context input is done" "0,1" wgroup.long 0x2C++0x3 line.long 0x0 "HSM_DTHE_S_AES_ICIS,Secured AES Interrupt Clear Interrupt Status Register." bitfld.long 0x0 3. "DOUT,Clear'output Data movement done' flag" "0,1" bitfld.long 0x0 2. "DIN,Clear'input Data movement done' flag" "0,1" bitfld.long 0x0 1. "COUT,Clear'Context output done' flag" "0,1" bitfld.long 0x0 0. "CIN,Clear'context input done' flag" "0,1" wgroup.long 0x200++0x7 line.long 0x0 "HSM_DTHE_S_EIP_CGCFG,Secured EIP Clock gating configuration." bitfld.long 0x0 4. "PKA_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 3. "TRNG_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 2. "EIP16_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 1. "AES_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 0. "SHA_CFG,0- request to un-gate 1- request to gate the clock." "0,1" line.long 0x4 "HSM_DTHE_S_EIP_CGREQ,Secured EIP Clock gating Request." hexmask.long.byte 0x4 28.--31. 1. "KEY,When'0x5' write'1' to lower bits [4:0] will set the bit. Write'0' will be ignoredWhen'0x2' write'1' to lower bit [4:0] will clear the bit. Write'0' will be ignoredfor other key value regular read write operation" bitfld.long 0x4 4. "PKA_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 3. "TRNG_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 2. "EIP16_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 1. "AES_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 0. "SHA_REQ,0- request to un-gate 1- request to gate the clock." "0,1" group.long 0x400++0x3 line.long 0x0 "HSM_DTHE_S_CRC_CTRL,Secured CRC Control register." bitfld.long 0x0 15. "FLASH_ACC2CRC,1 if use Flash access port to feed CRC [uses length and address in that block to control data [Reserved]. Only present in DTHE_S_CRC_CTRL register" "0,1" bitfld.long 0x0 13.--14. "INIT,Initialize the CRC 00- use SEED register context as starting value 10- all'zero' 11- all'one' This is self clearing. With first write to data register this value clears to zero and remain zero for rest of the operation unless written again" "0,1,2,3" bitfld.long 0x0 12. "BYTE,Input data size 0- 32 bit 1- 8 bit" "0,1" bitfld.long 0x0 9. "OINV,Inverse the bits of result before storing to CRC_RSLT_PP0" "0,1" bitfld.long 0x0 8. "OBR,Bit reserved the output result byte before storing to CRC_RSLT_PP0. applicable for all bytes in word" "0,1" bitfld.long 0x0 7. "IBR,Bit reverse the input byte. For all bytes in word" "0,1" bitfld.long 0x0 4.--5. "ENDIAN,Endian control [0]- swap byte in half-word [1]- swap half word" "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "TYPE,Type of operation0000 polynomial 0x8005 0001 polynomial 0x10210010 polynomial 0x4C11DB7 0011 polynomial 0x1EDC6F411000 TCP checksumTYPE in DTHE_S_CRC_CTRL & DTHE_S_CRC_CTRL should be exclusive" group.long 0x410++0x7 line.long 0x0 "HSM_DTHE_S_CRC_SEED,SecuredCRC SEED/Context-CRC register." hexmask.long 0x0 0.--31. 1. "SEED,Starting seed of CRC and checksum operation. Please see CTRL register for more detail. This resister also holds the latest result of CRC or checksum operation" line.long 0x4 "HSM_DTHE_S_CRC_DIN,Secured CRC DATA Input register." hexmask.long 0x4 0.--31. 1. "DATA_IN,Input data for CRC or checksum operation" rgroup.long 0x418++0x3 line.long 0x0 "HSM_DTHE_S_CRC_RSLT_PP,Secured CRC post processed output." hexmask.long 0x0 0.--31. 1. "RSLT_PP,Result data of CRC or checksum operation" group.long 0x810++0x3 line.long 0x0 "HSM_DTHE_P_SHA_IMST,Public SHA Interrupt Mask Set Register." bitfld.long 0x0 2. "DIN,Data in: this interrupt is raised when DMA writes last word of input data to internal FIFO of the engine" "0,1" bitfld.long 0x0 1. "COUT,Context out: this interrupt is raised when DMA complets the output context movement from internal register" "0,1" bitfld.long 0x0 0. "CIN,context in: this interrupt is raised when DMA complets Context write to internal register" "0,1" rgroup.long 0x814++0x7 line.long 0x0 "HSM_DTHE_P_SHA_IRIS,Public SHA Interrupt Raw Interrupt Status Register." bitfld.long 0x0 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x0 1. "COUT,Context output is done" "0,1" bitfld.long 0x0 0. "CIN,context input is done" "0,1" line.long 0x4 "HSM_DTHE_P_SHA_IMIS,Public SHA Interrupt Masked interrupt Status Registe." bitfld.long 0x4 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x4 1. "COUT,Context output is done" "0,1" bitfld.long 0x4 0. "CIN,context input is done" "0,1" wgroup.long 0x81C++0x3 line.long 0x0 "HSM_DTHE_P_SHA_ICIS,Public SHA Interrupt Clear Interrupt Status Register." bitfld.long 0x0 2. "DIN,Clear'input Data movement done' flag" "0,1" bitfld.long 0x0 1. "COUT,Clear'Context output done' flag" "0,1" bitfld.long 0x0 0. "CIN,Clear'context input done' flag" "0,1" group.long 0x820++0x3 line.long 0x0 "HSM_DTHE_P_AES_IMST,Public AES Interrupt Mask Set Register." bitfld.long 0x0 3. "DOUT,Data out: this interrupt is raised when DMA finishes Writing last word of the process result" "0,1" bitfld.long 0x0 2. "DIN,Data in: this interrupt is raised when DMA writes last word of input data to internal FIFO of the engine" "0,1" bitfld.long 0x0 1. "COUT,Context out: this interrupt is raised when DMA complets the output context movement from internal register" "0,1" bitfld.long 0x0 0. "CIN,context in: this interrupt is raised when DMA complets Context write to internal register" "0,1" rgroup.long 0x824++0x7 line.long 0x0 "HSM_DTHE_P_AES_IRIS,Public AES Interrupt Raw Interrupt Status Register." bitfld.long 0x0 3. "DOUT,Output Data movement is done" "0,1" bitfld.long 0x0 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x0 1. "COUT,Context output is done" "0,1" bitfld.long 0x0 0. "CIN,context input is done" "0,1" line.long 0x4 "HSM_DTHE_P_AES_IMIS,Public AES Interrupt Masked interrupt Status Register." bitfld.long 0x4 3. "DOUT,Output Data movement is done" "0,1" bitfld.long 0x4 2. "DIN,Input Data movement is done" "0,1" bitfld.long 0x4 1. "COUT,Context output is done" "0,1" bitfld.long 0x4 0. "CIN,context input is done" "0,1" group.long 0x82C++0x3 line.long 0x0 "HSM_DTHE_P_AES_ICIS,Public AES Interrupt Clear Interrupt Status Register." bitfld.long 0x0 3. "DOUT,Clear'output Data movement done' flag" "0,1" bitfld.long 0x0 2. "DIN,Clear'input Data movement done' flag" "0,1" bitfld.long 0x0 1. "COUT,Clear'Context output done' flag" "0,1" bitfld.long 0x0 0. "CIN,Clear'context input done' flag" "0,1" wgroup.long 0xA00++0x7 line.long 0x0 "HSM_DTHE_P_EIP_CGCFG,Public EIP Clock gating configuration." bitfld.long 0x0 4. "PKA_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 3. "TRNG_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 2. "EIP16_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 1. "AES_CFG,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x0 0. "SHA_CFG,0- request to un-gate 1- request to gate the clock." "0,1" line.long 0x4 "HSM_DTHE_P_EIP_CGREQ,Public EIP Clock gating Request." hexmask.long.byte 0x4 28.--31. 1. "KEY,When'0x5' write'1' to lower bits [4:0] will set the bit. Write'0' will be ignoredWhen'0x2' write'1' to lower bit [4:0] will clear the bit. Write'0' will be ignoredfor other key value regular read write operation" bitfld.long 0x4 4. "PKA_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 3. "TRNG_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 2. "EIP16_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 1. "AES_REQ,0- request to un-gate 1- request to gate the clock." "0,1" bitfld.long 0x4 0. "SHA_REQ,0- request to un-gate 1- request to gate the clock." "0,1" group.long 0xC00++0x3 line.long 0x0 "HSM_DTHE_P_CRC_CTRL,Public CRC Control register." bitfld.long 0x0 15. "FLASH_ACC2CRC,1 if use Flash access port to feed CRC [uses length and address in that block to control data [Reserved]. Only present in DTHE_S_CRC_CTRL register" "0,1" bitfld.long 0x0 13.--14. "INIT,Initialize the CRC 00- use SEED register context as starting value 10- all'zero' 11- all'one' This is self clearing. With first write to data register this value clears to zero and remain zero for rest of the operation unless written again" "0,1,2,3" bitfld.long 0x0 12. "BYTE,Input data size 0- 32 bit 1- 8 bit" "0,1" bitfld.long 0x0 9. "OINV,Inverse the bits of result before storing to CRC_RSLT_PP0" "0,1" bitfld.long 0x0 8. "OBR,Bit reserved the output result byte before storing to CRC_RSLT_PP0. applicable for all bytes in word" "0,1" bitfld.long 0x0 7. "IBR,Bit reverse the input byte. For all bytes in word" "0,1" bitfld.long 0x0 4.--5. "ENDIAN,Endian control [0]- swap byte in half-word [1]- swap half word" "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "TYPE,Type of operation0000 polynomial 0x8005 0001 polynomial 0x10210010 polynomial 0x4C11DB7 0011 polynomial 0x1EDC6F411000 TCP checksumTYPE in DTHE_S_CRC_CTRL & DTHE_S_CRC_CTRL should be exclusive" group.long 0xC10++0x7 line.long 0x0 "HSM_DTHE_P_CRC_SEED,PublicCRC SEED/Context-CRC register." hexmask.long 0x0 0.--31. 1. "SEED,Starting seed of CRC and checksum operation. Please see CTRL register for more detail. This resister also holds the latest result of CRC or checksum operation" line.long 0x4 "HSM_DTHE_P_CRC_DIN,Public CRC DATA Input register." hexmask.long 0x4 0.--31. 1. "DATA_IN,Input data for CRC or checksum operation" rgroup.long 0xC18++0x3 line.long 0x0 "HSM_DTHE_P_CRC_RSLT_PP,Public CRC post processed output." hexmask.long 0x0 0.--31. 1. "RSLT_PP,Result data of CRC or checksum operation" rgroup.long 0xF00++0xF line.long 0x0 "HSM_DTHE_P_RAND_KEY0,Device Specific Randon key [31:0]." hexmask.long 0x0 0.--31. 1. "KEY31_0,Device Specific Randon key [31:0]" line.long 0x4 "HSM_DTHE_P_RAND_KEY1,Device Specific Randon key [63:32]." hexmask.long 0x4 0.--31. 1. "KEY63_32,Device Specific Randon key [63:32]" line.long 0x8 "HSM_DTHE_P_RAND_KEY2,Device Specific Randon key [95:64]." hexmask.long 0x8 0.--31. 1. "KEY95_64,Device Specific Randon key [95:64]" line.long 0xC "HSM_DTHE_P_RAND_KEY3,Device Specific Randon key [127:96]." hexmask.long 0xC 0.--31. 1. "KEY127_96,Device Specific Randon key [127:96]" tree.end tree "HSM0_HSM_PKA" base ad:0xCE010000 group.long 0x0++0x2B line.long 0x0 "HSM_PKA_PKA_APTR,A operand address offset." hexmask.long.word 0x0 12.--21. 1. "RESERVED_1,Set to zero on Write ignore on Read." bitfld.long 0x0 11. "GF2M_ACC,When set this bit specifies that Vector A is located within the operand registers of the GF2m Engine." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "APTR,These bits specify the location of Vector A within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary." line.long 0x4 "HSM_PKA_PKA_BPTR,B operand address offset." hexmask.long.word 0x4 12.--21. 1. "RESERVED_1,Set to zero on Write ignore on Read." bitfld.long 0x4 11. "GF2M_ACC,When set this bit specifies that Vector B is located within the operand registers of the GF2m Engine." "0,1" newline hexmask.long.word 0x4 0.--10. 1. "BPTR,These bits specify the location of Vector B within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary." line.long 0x8 "HSM_PKA_PKA_CPTR,C operand/result address offset." hexmask.long.word 0x8 12.--21. 1. "RESERVED_1,Set to zero on Write ignore on Read." bitfld.long 0x8 11. "GF2M_ACC,When set this bit specifies that Vector C is located within the operand registers of the GF2m Engine." "0,1" newline hexmask.long.word 0x8 0.--10. 1. "CPTR,These bits specify the location of Vector C within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary." line.long 0xC "HSM_PKA_PKA_DPTR,D operand/result address offset." hexmask.long.word 0xC 12.--21. 1. "RESERVED_1,Set to zero on Write ignore on Read." bitfld.long 0xC 11. "GF2M_ACC,When set this bit specifies that Vector D is located within the operand registers of the GF2m Engine." "0,1" newline hexmask.long.word 0xC 0.--10. 1. "DPTR,These bits specify the location of Vector D within the PKA RAM. Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary." line.long 0x10 "HSM_PKA_PKA_ALENGTH,Length of A operand." hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED_1,Set to zero on Write ignore on Read." hexmask.long.word 0x10 0.--9. 1. "ALENGTH,This register specifies the length [in 32-bit words] of Vector A." line.long 0x14 "HSM_PKA_PKA_BLENGTH,Length of B operand." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED_1,Set to zero on Write ignore on Read." hexmask.long.word 0x14 0.--9. 1. "BLENGTH,This register specifies the length [in 32-bit words] of Vector A." line.long 0x18 "HSM_PKA_PKA_SHIFT,Bits to shift." hexmask.long 0x18 6.--31. 1. "RESERVED_1,Set to zero on Write ignore on Read." hexmask.long.byte 0x18 0.--4. 1. "BITS_TO_SHIFT,This register specifies the number of bits to shift the input vector [in the range 0- 31] during a Rshift or Lshift operation" line.long 0x1C "HSM_PKA_PKA_FUNCTION,Function code. Run control/status. Stall Result control." hexmask.long.byte 0x1C 25.--31. 1. "RESERVED_3,Set to zero on Write ignore on Read" bitfld.long 0x1C 24. "STALL_RESULT,When written with a1b updating of the PKA_COMPARE PKA_MSW and PKA_DIVMSW registers as well as resetting the Run bit is stalled beyond the point that a running operation is actually finished. Use this to allow software enough time to read.." "0,1" newline hexmask.long.byte 0x1C 19.--23. 1. "RESERVED_2,Set to zero on Write ignore on Read." bitfld.long 0x1C 16.--18. "SEQUENCER_OPERATIONS_EXTEND,These bits are an extend of bits [14:12] to select the complex Sequencer operation to perform" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 15. "RUN,The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex Sequencer operation. This bit is reset low automatically when the operation is complete. The complement of this bit is available as interrupt see sections.." "0,1" bitfld.long 0x1C 12.--14. "SEQ_OP,These bits in combination with bits [18:16] select the complex Sequencer operation to perform" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 11. "COPY,Perform copy operation." "0,1" bitfld.long 0x1C 10. "COMPARE,Perform compare operation" "0,1" newline bitfld.long 0x1C 9. "MODULO,Perform modulo operation." "0,1" bitfld.long 0x1C 8. "DIVIDE,Perform divide operation." "0,1" newline bitfld.long 0x1C 7. "LSHIFT,Perform left shift operation." "0,1" bitfld.long 0x1C 6. "RSHIFT,Perform right shift operation" "0,1" newline bitfld.long 0x1C 5. "SUBTRACT,Perform subtract operation" "0,1" bitfld.long 0x1C 4. "ADD,Perform add operation" "0,1" newline bitfld.long 0x1C 3. "MS_ONE,Loads the location of the Most Significant one bit within the result word indicated in the PKA_MSW register into bits [4:0] of the PKA_DIVMSW register - can only be used with basic PKCP operations8 except for Divide Modulo and Compare." "0,1" bitfld.long 0x1C 2. "RESERVED_1,Set to zero on Write ignore on Read" "0,1" newline bitfld.long 0x1C 1. "ADDSUB,Perform combined Add/Subtract operation" "0,1" bitfld.long 0x1C 0. "MULTIPLY,Perform multiply operation." "0,1" line.long 0x20 "HSM_PKA_PKA_COMPARE,Result of compare." hexmask.long 0x20 3.--31. 1. "RESERVED_1,Ignore on Read." rbitfld.long 0x20 2. "A_GREATER_THAN_B,Vector_A is greater than Vector_B." "0,1" newline rbitfld.long 0x20 1. "A_LESS_THAN_B,Vector_A is less than Vector_B." "0,1" rbitfld.long 0x20 0. "A_EQUAL_B,Vector_A is equal to Vector_B." "0,1" line.long 0x24 "HSM_PKA_PKA_MSW,MS non-zero word address." hexmask.long.word 0x24 16.--31. 1. "RESERVED_2,Ignore on Read." rbitfld.long 0x24 15. "RESULT_IS_ZERO,The result vector is all zeroes; ignore the address returned in bits [10:0]." "0,1" newline bitfld.long 0x24 12.--14. "RESERVED_1,Ignore on Read." "0,1,2,3,4,5,6,7" rbitfld.long 0x24 11. "GF2M_ACC,When set this bit specifies that the result vector is located within the operand registers of the GF2m Engine." "0,1" newline hexmask.long.word 0x24 0.--10. 1. "MSW_ADDRESS,Address of the most significant non-zero 32-bit word of the result vector in PKA RAM." line.long 0x28 "HSM_PKA_PKA_DIVMSW,MS non-zero word address for remainder (MOD and DIV ops)." hexmask.long.word 0x28 16.--31. 1. "RESERVED_2,Ignore on Read." rbitfld.long 0x28 15. "RESULT_IS_ZERO,The result vector is all zeroes; ignore the address returned in bits [10:0]." "0,1" newline bitfld.long 0x28 12.--14. "RESERVED_1,Ignore on Read." "0,1,2,3,4,5,6,7" rbitfld.long 0x28 11. "GF2M_ACC,When set this bit specifies that the result vector is located within the operand registers of the GF2m Engine." "0,1" newline hexmask.long.word 0x28 0.--10. 1. "MSW_ADDRESS,The description of the bits in this field depends on the value of the MS one bit in PKA_FUNCTION register. When MS one bit is0b Msw_Address[10:0] Address of the most significant non-zero 32-bit word of the Remainder result vector in PKA RAM." group.long 0x40++0x7 line.long 0x0 "HSM_PKA_LNME1_STATUS,LNME 1 status register." hexmask.long 0x0 6.--31. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x0 5. "STICKY_ZERO,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to zero or equal to the modulus N. Updated at the end of an operation [setonly] not cleared to0bby hardware on start of any operation [must be.." "0,1" newline bitfld.long 0x0 4. "STICKY_OFLO,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to- or greater than the modulus N. Updated at the end of an operation [setonly] not cleared to0bby hardware on start of any operation [must be.." "0,1" bitfld.long 0x0 3. "RESULT_ZERO,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to zero or equal to the modulus N. Updated at the end of an operation automatically cleared to0bby hardware on start of any operation" "0,1" newline bitfld.long 0x0 2. "CMD_ERROR,Read/write reset value0b set to1bby hardware when trying to start multiple operations in one command automatically cleared to0bby hardware on start of any [legal] operation" "0,1" bitfld.long 0x0 1. "MMM_BUSY,Read/write reset value0b set to1bby hardware when the LNME executes an MMM* or EXP operation [cannot be written to0bduring execution of an operation]. Automatically cleared to0bby hardware when finishing an operation. The LNME interrupt is the.." "0,1" newline bitfld.long 0x0 0. "OVERFLOW,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to- or greater than the modulus N. Updated at the end of an operation automatically cleared to0bby hardware on start of any operation" "0,1" line.long 0x4 "HSM_PKA_LNME1_CONTROL,LNME 1 control register (no SW reset)." hexmask.long 0x4 6.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x4 5. "RESET,Set-only reset value0b When set to1b the LNME is reset and all internal storage locations are flushed [including the LNME FIFO RAM[s]] cleared to0bby hardware at the end of the operation. This command has priority over the MMM* and EXP commands.." "0,1" newline bitfld.long 0x4 3.--4. "RESERVED_1,Bits should be written with 0 and should be ignored on a read. For backward compatibility these bits are actually connected to flip-flops." "0,1,2,3" bitfld.long 0x4 2. "EXP_CMD,Set-only reset value0b When set to1b the LNME starts an EXP operation; cleared to0bby hardware at the end of the operation or when executing a RESET command" "0,1" newline bitfld.long 0x4 1. "MMMNEXT_CMD,Set-only reset value0b When set to1b the LNME starts an MMMNEXT operation; cleared to0bby hardware at the end of the operation or when executing a RESET command. Note: Setting bits [1] and [0] at the same time starts an MMM3A operation .." "0,1" bitfld.long 0x4 0. "MMM_CMD,Set-only reset value0b When set to1b the LNME starts an MMM operation; cleared to0bby hardware at the end of the operation or when executing a RESET command." "0,1" group.long 0x60++0x17 line.long 0x0 "HSM_PKA_LNME1_NBASE,N-Operand BASE Address. Y-Operand and N-Operand 32-bit 'Digits '" hexmask.long.byte 0x0 26.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read" hexmask.long.word 0x0 16.--25. 1. "NYDIGITS,Y-Operand and N-Operand 32-bit'digits' [offset by 1]. Also used for X-operand length in an EXP operation. Minimum value is 0 [for 32 bit operands] maximum value is 12810 [for4128bit operands actually4096'real ' data bits plus 32 bits to handle.." newline bitfld.long 0x0 15. "MOD_RD,Setting this bit to1bindicates that the modulus should be read from the GF2m Engine 's GF2M_OPERAND_A_0..15 [bits [511:0]] and GF2M_OPERAND_B_0..7 [bits [767:512]] registers. Note: When this bit is set the nbase field contents become 'don 't care.." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." newline hexmask.long.word 0x0 1.--10. 1. "NBASE,N-Operand Base Address." rbitfld.long 0x0 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0x4 "HSM_PKA_LNME1_XBASE,X-Operand BASE Address. X-Operand 32-bit 'Digits '." hexmask.long.byte 0x4 26.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0x4 16.--25. 1. "MMM_CMD,X-Operand 32-bit'digits' [offset by 1] used for MMM* operations only. Minimum value is 0 [for 32 bit X operands] maximum value is 12811 [for4128bit X operands actually4096'real ' data bits plus 2 extra bits to handle X inputs up to four times.." newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0x4 1.--10. 1. "XBASE,X-Operand Base Address." newline rbitfld.long 0x4 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0x8 "HSM_PKA_LNME1_YBASE,Y-Operand BASE Address. MMM Passes." hexmask.long.byte 0x8 24.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." hexmask.long.byte 0x8 16.--23. 1. "NPASSES,MMM passes. Minimum value is 0 [for ONE pass] maximum value is 255 for 256 passes." newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0x8 1.--10. 1. "YBASE,Y-Operand Base Address." newline rbitfld.long 0x8 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0xC "HSM_PKA_LNME1_BBASE,B-Operand BASE Address. B-Operand Bit Count." bitfld.long 0xC 31. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." "0,1" hexmask.long.word 0xC 16.--30. 1. "BCNTR,B-Operand Bit Count. Minimum value is 0 for an exponent length of 2 bits maximum value is 409513 for an exponent of4097bits [to allow exponent blinding]. If no exponent blinding is used the exponent would normally be smaller than the modulus. Note.." newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0xC 1.--10. 1. "BBASE,B-Operand BASE Address." newline rbitfld.long 0xC 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0x10 "HSM_PKA_LNME1_NACC,N '. N ' calculation busy flag. exponent array size for EXP." hexmask.long.byte 0x10 21.--26. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." hexmask.long.byte 0x10 16.--20. 1. "EXPARRAY,Exponent Array. A minimum [default] value of 0 indicates that there is only odd power: AR mod N. This is the value of exparray when exponent re-coding is not used. A maximum value of 31 indicates 32 odd powers can be used for exponent re-coding .." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x10 8. "NACC_BUSY,Reset-only - nacc Calculation Busy set to1bduring 8 clock cycles after Writing nzero in LNME*_NZERO while nacc is being calculated. During this time operation starts are stalled. Writing this bit with0baborts the calculation but can leave.." "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "NACC,N Accent. Any odd [bit [0] is1b 8 bit value can be loaded here [result of calculation]. Automatically loaded with calculated value after Writing nzero in LNME*_NZERO." line.long 0x14 "HSM_PKA_LNME1_NZERO,Lowest byte of N-Operand for N ' calculation." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.byte 0x14 0.--7. 1. "NZERO,N vector Byte 0. Any odd [bit [0] is1b 8 bit value can be loaded here. Writing starts the nacc calculation automatically." group.long 0x80++0xB line.long 0x0 "HSM_PKA_LNME0_STATUS,LNME 0 status register." hexmask.long 0x0 6.--31. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x0 5. "STICKY_ZERO,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to zero or equal to the modulus N. Updated at the end of an operation [setonly] not cleared to0bby hardware on start of any operation [must be.." "0,1" newline bitfld.long 0x0 4. "STICKY_OFLO,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to- or greater than the modulus N. Updated at the end of an operation [setonly] not cleared to0bby hardware on start of any operation [must be.." "0,1" bitfld.long 0x0 3. "RESULT_ZERO,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to zero or equal to the modulus N. Updated at the end of an operation automatically cleared to0bby hardware on start of any operation" "0,1" newline bitfld.long 0x0 2. "CMD_ERROR,Read/write reset value0b set to1bby hardware when trying to start multiple operations in one command automatically cleared to0bby hardware on start of any [legal] operation" "0,1" bitfld.long 0x0 1. "MMM_BUSY,Read/write reset value0b set to1bby hardware when the LNME executes an MMM* or EXP operation [cannot be written to0bduring execution of an operation]. Automatically cleared to0bby hardware when finishing an operation. The LNME interrupt is the.." "0,1" newline bitfld.long 0x0 0. "OVERFLOW,Read/write reset value0b set to1bby hardware when the result of an MMM* or EXP operation is equal to- or greater than the modulus N. Updated at the end of an operation automatically cleared to0bby hardware on start of any operation" "0,1" line.long 0x4 "HSM_PKA_LNME0_CONTROL,LNME 0 control register." hexmask.long 0x4 6.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x4 5. "RESET_CMD,Set-only reset value0b When set to1b the LNME is reset and all internal storage locations are flushed [including the LNME FIFO RAM[s]] cleared to0bby hardware at the end of the operation. This command has priority over the MMM* and EXP.." "0,1" newline bitfld.long 0x4 3.--4. "RESERVED_1,Bits should be written with 0 and should be ignored on a read. For backward compatibility these bits are actually connected to flip-flops." "0,1,2,3" bitfld.long 0x4 2. "EXP_CMD,Set-only reset value0b When set to1b the LNME starts an EXP operation; cleared to0bby hardware at the end of the operation or when executing a RESET command" "0,1" newline bitfld.long 0x4 1. "MMMNEXT_CMD,Set-only reset value0b When set to1b the LNME starts an MMMNEXT operation; cleared to0bby hardware at the end of the operation or when executing a RESET command. Note: Setting bits [1] and [0] at the same time starts an MMM3A operation .." "0,1" bitfld.long 0x4 0. "MMM_CMD,Set-only reset value0b When set to1b the LNME starts an MMM operation; cleared to0bby hardware at the end of the operation or when executing a RESET command." "0,1" line.long 0x8 "HSM_PKA_LNME_DATAPATH,PE bypass and dual LNME linking control." hexmask.long.word 0x8 16.--30. 1. "RESERVED_3,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x8 15. "LINKUP,This bit controls the 'linking ' of the two LNME PE chains in a dual LNME [if configured otherwise this field must be treated as 'Reserved ']. When set to1b all PEs of the 2nd chain are inserted at the end of the 1st chain [in front of the.." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x8 8.--10. "BYPASS_1,This field controls the PE chain bypass multiplexers for the 2nd LNME. The number of bits is 3 for 12-PE configurations.Note: This field cannot be changed while an operation is busy in the 2nd LNME." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x8 0.--2. "BYPASS_0,This field controls the PE chain bypass multiplexers for the 1st LNME. The number of bits is 3 for 12-PE configurations.Note: This field cannot be changed while an operation is busy in the 1st LNME." "0,1,2,3,4,5,6,7" group.long 0x90++0xB line.long 0x0 "HSM_PKA_LNME_FAST_CTRL,Fast MMM3A/ADDSUB op control." bitfld.long 0x0 31. "UPDATE,Write-only bit should be written with1bwhen updating bits [30:16] always reads0b When Writing this bit with a0b bits [30:16] will not be changed irrespective the values written there. Updating bits [30:16] can only be done with a single write.." "0,1" hexmask.long.byte 0x0 26.--30. 1. "XOR_VALUE,This field controls the value XOR-ed into the vector index fields of the LNME_FAST_MMM and LNME_FAST_STRT registers when the xor_ctrl is1bupon starting an MMM3A and/or PKCP ADDSUB operation using those registers. The actual XOR is only done.." newline hexmask.long.byte 0x0 21.--25. 1. "CMP_VALUE,This field contains bits that are compared against the vector index fields of the LNME_FAST_MMM and LNME_FAST_STRT registers when starting an MMM3A and/or PKCP ADDSUB operation using those registers. Comparison is only done for the.." hexmask.long.byte 0x0 16.--20. 1. "CMP_MASK,This field controls which bits of the vector index fields of the LNME_FAST_MMM and LNME_FAST_STRT registers are compared against cmp_value when starting an MMM3A and/or PKCP ADDSUB operation using those registers. A1bin this field compares the.." newline hexmask.long.word 0x0 1.--14. 1. "IGNORED,These bits are ignored on a write and will read zero on a read. These bits are intended to allow Writing any value to bits [15:1] while setting the xor_ctrl bit" bitfld.long 0x0 0. "XOR_CTRL,This bit controls whether or not the value in the xor_mask field is XOR-ed into the vector index fields of the LNME_FAST_MMM and LNME_FAST_STRT registers. The state of this bit is logged with an MMM3A or ADDSUB operation request using those.." "0,1" line.long 0x4 "HSM_PKA_LNME_FAST_STRT,Fast ADDSUB operation start (in PKCP)." bitfld.long 0x4 31. "REQUEST_SUB,This bit controls which operation is actually performed in the PKCP:A0brequests an ADD operation which is performed using the ADDSUB A+C-B operation with the A and C vectors controlled by the addsub_a and addsub_bc fields here. The B vector.." "0,1" hexmask.long.byte 0x4 26.--30. 1. "ADDSUB_D,This holds the index for the PKCP ADDSUB result vector 'D ' in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]." newline hexmask.long.byte 0x4 21.--25. 1. "ADDSUB_BC,This holds the index for the PKCP ADDSUB operation 'B ' or 'C ' input vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]." hexmask.long.byte 0x4 16.--20. 1. "ADDSUB_A,This holds the index for the PKCP ADDSUB operation 'A ' input vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]." newline hexmask.long.word 0x4 3.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x4 2. "LNME1_REQUEST,This bit will be set to1bwhen an MMM3A operation is requested in the 2nd LNME by Writing to bits [31:16] of the LNME_FAST_MMM register with a non-zero value. The operation is started as soon as possible i.e. when both LNMEs and the PKCP.." "0,1" newline bitfld.long 0x4 1. "LNME0_REQUEST,This bit will be set to1bwhen an MMM3A operation is requested in the 1st LNME by Writing to bits [15:0] of the LNME_FAST_MMM register with a non-zero value. The operation is started as soon as possible i.e. when both LNMEs and the PKCP are.." "0,1" bitfld.long 0x4 0. "PKCP_REQUEST,This bit will be set to1bwhen an ADDSUB operation is requested in the PKCP by Writing to bits [31:16] of this register with a non-zero value. The operation is started as soon as possible i.e. when both LNMEs and the PKCP are ready for a.." "0,1" line.long 0x8 "HSM_PKA_LNME_FAST_MMM,Fast MMM3A operation start." bitfld.long 0x8 31. "STICKY_1,Bit should be written with1bto request updating the sticky_oflo and sticky_zero status bits in the LNME1_STATUS register. When this bit is written0b those status bits are not modified at the end of the MMM3A operation. Note: This field is.." "0,1" hexmask.long.byte 0x8 26.--30. 1. "RINDEX_1,This holds the index for the 2nd LNME 's result vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]. Note: This field is 'Reserved ' in a normal [non-dual] LNME configuration." newline hexmask.long.byte 0x8 21.--25. 1. "YINDEX_1,This holds the index for the 2nd LNME 's Y input vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]. Note: This field is 'Reserved ' in a normal [non-dual] LNME configuration." hexmask.long.byte 0x8 16.--20. 1. "XINDEX_1,This holds the index for the 2nd LNME 's X input vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]. Note: This field is 'Reserved ' in a normal [non-dual] LNME configuration." newline bitfld.long 0x8 14. "STICKY_0,Bit should be written with1bto request updating the sticky_oflo and sticky_zero status bits in the LNME0_STATUS register. When this bit is written0b those status bits are not modified at the end of the MMM3A operation." "0,1" hexmask.long.byte 0x8 10.--13. 1. "RINDEX_0,This holds the index for the 1st LNME 's result vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]." newline hexmask.long.byte 0x8 5.--9. 1. "YINDEX_0,This holds the index for the 1st LNME 's Y input vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]." hexmask.long.byte 0x8 0.--4. 1. "XINDEX_0,This holds the index for the 1st LNME 's X input vector in the table [before possible XOR-ing with the xor_value field in the LNME_FAST_CTRL register]." group.long 0xA0++0x17 line.long 0x0 "HSM_PKA_LNME0_NBASE,N-Operand BASE Address. Y-Operand and N-Operand 32-bit 'Digits '" hexmask.long.byte 0x0 26.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read" hexmask.long.word 0x0 16.--25. 1. "NYDIGITS,Y-Operand and N-Operand 32-bit'digits' [offset by 1]. Also used for X-operand length in an EXP operation. Minimum value is 0 [for 32 bit operands] maximum value is 12810 [for4128bit operands actually4096'real ' data bits plus 32 bits to handle.." newline bitfld.long 0x0 15. "MOD_RD,Setting this bit to1bindicates that the modulus should be read from the GF2m Engine 's GF2M_OPERAND_A_0..15 [bits [511:0]] and GF2M_OPERAND_B_0..7 [bits [767:512]] registers. Note: When this bit is set the nbase field contents become 'don 't care.." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." newline hexmask.long.word 0x0 1.--10. 1. "NBASE,N-Operand Base Address." rbitfld.long 0x0 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0x4 "HSM_PKA_LNME0_XBASE,X-Operand BASE Address. X-Operand 32-bit 'Digits '." hexmask.long.byte 0x4 26.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0x4 16.--25. 1. "MMM_CMD,X-Operand 32-bit'digits' [offset by 1] used for MMM* operations only. Minimum value is 0 [for 32 bit X operands] maximum value is 12811 [for4128bit X operands actually4096'real ' data bits plus 2 extra bits to handle X inputs up to four times.." newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0x4 1.--10. 1. "XBASE,X-Operand Base Address." newline rbitfld.long 0x4 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0x8 "HSM_PKA_LNME0_YBASE,Y-Operand BASE Address. MMM Passes." hexmask.long.byte 0x8 24.--31. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." hexmask.long.byte 0x8 16.--23. 1. "NPASSES,MMM passes. Minimum value is 0 [for ONE pass] maximum value is 255 for 256 passes." newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0x8 1.--10. 1. "YBASE,Y-Operand Base Address." newline rbitfld.long 0x8 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0xC "HSM_PKA_LNME0_BBASE,B-Operand BASE Address. B-Operand Bit Count." bitfld.long 0xC 31. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." "0,1" hexmask.long.word 0xC 16.--30. 1. "BCNTR,B-Operand Bit Count. Minimum value is 0 for an exponent length of 2 bits maximum value is 409513 for an exponent of4097bits [to allow exponent blinding]. If no exponent blinding is used the exponent would normally be smaller than the modulus. Note.." newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.word 0xC 1.--10. 1. "BBASE,B-Operand BASE Address." newline rbitfld.long 0xC 0. "ZERO,Bit [0] is forced to 0 to locate the first 32 bits word at a 64 bit word boundary." "0,1" line.long 0x10 "HSM_PKA_LNME0_NACC,N '. N ' calculation busy flag. exponent array size for EXP." hexmask.long.byte 0x10 21.--26. 1. "RESERVED_2,Bits should be written with 0 and should be ignored on a read." hexmask.long.byte 0x10 16.--20. 1. "EXPARRAY,Exponent Array. A minimum [default] value of 0 indicates that there is only odd power: AR mod N. This is the value of exparray when exponent re-coding is not used. A maximum value of 31 indicates 32 odd powers can be used for exponent re-coding .." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." bitfld.long 0x10 8. "NACC_BUSY,Reset-only - nacc Calculation Busy set to1bduring 8 clock cycles after Writing nzero in LNME*_NZERO while nacc is being calculated. During this time operation starts are stalled. Writing this bit with0baborts the calculation but can leave.." "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "NACC,N Accent. Any odd [bit [0] is1b 8 bit value can be loaded here [result of calculation]. Automatically loaded with calculated value after Writing nzero in LNME*_NZERO." line.long 0x14 "HSM_PKA_LNME0_NZERO,Lowest byte of N-Operand for N ' calculation." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." hexmask.long.byte 0x14 0.--7. 1. "NZERO,N vector Byte 0. Any odd [bit [0] is1b 8 bit value can be loaded here. Writing starts the nacc calculation automatically." group.long 0xC8++0x3 line.long 0x0 "HSM_PKA_PKA_SEQ_CTRL,PKA Sequencer control/status register." bitfld.long 0x0 31. "RESET,Read/Write reset value0b[ZERO]. Writing1bwill reset the Sequencer write to0bto restart operations again. As the reset value is0b the Sequencer will automatically start operations executing from program ROM. This bit should always be written with.." "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED_1,Bits should be written with 0 and should be ignored on a read." newline hexmask.long.byte 0x0 8.--15. 1. "SEQ_STATUS,These read-only bits can be used by the Sequencer to communicate status to the outside world. Bit [8] is also used as Sequencer interrupt with the complement of this bit OR-ed into the 'Run ' bit in PKA_FUNCTION. Refer to the SafeXcel-IP-29t2.." hexmask.long.byte 0x0 0.--7. 1. "SW_TRIGGERS,These bits can be used by software to trigger Sequencer operations. External logic can set these bits by Writing a1b can not reset them by Writing a0b The Sequencer can reset these bits by Writing a0b can not set them by Writing a1b Setting.." group.long 0xF4++0xB line.long 0x0 "HSM_PKA_PKA_OPTION,PKA HW options register." hexmask.long.byte 0x0 24.--31. 1. "LNME_FIFO_DEPT,Number of words in the LNME 's FIFO RAM should be ignored if LNME configuration is 0." rbitfld.long 0x0 22.--23. "GF2M_CONFIG,Value 0 indicates NO GF2m Engine value 1 indicates one standard GF2m Engine [field size 571 bits mul_depth = 4] other values are reserved." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "LNME_PES,Number of Processing Elements in the pipeline of the LNME should be ignored if LNME configuration is 0." bitfld.long 0x0 15. "RESERVED_1,Ignore on Read." "0,1" newline rbitfld.long 0x0 14. "LNME_BYPASS,Value1bindicates that bypass logic is present in the PEs." "0,1" rbitfld.long 0x0 13. "ZEROIZATION,Value1bindicates that hardware zeroization logic is present." "0,1" newline rbitfld.long 0x0 12. "MMM3A,Value1bindicates that the LNME supports the MMM3A operation." "0,1" rbitfld.long 0x0 11. "INTERRUPT_MASK,Value0bindicates that the main interrupt output [bit [0] of the PKA_IRQSTATUS register] is the direct complement of the Run bit in the PKA_CONTROL register value1bindicates that interrupt masking logic is present for this output." "0,1" newline rbitfld.long 0x0 8.--10. "PROT_OPTION,Value 0 indicates no additional protection against side channel attacks value 1 indicates the 'SCAP ' option value 3 indicates the 'PROT ' option other values reserved." "0,1,2,3,4,5,6,7" rbitfld.long 0x0 7. "PROGRAM_RAM,Value1bindicates Sequencer program storage in RAM value0bin ROM." "0,1" newline rbitfld.long 0x0 5.--6. "SEQ_CONFIG,Value 1 indicates a standard Sequencer other values reserved." "0,1,2,3" rbitfld.long 0x0 2.--4. "LNME_CONFIG,Value 0 indicates NO LNME. Value 1 indicates one standard LNME [with alpha = 32 beta = 8]. Value 2 indicates a dual LNME [with alpha = 32 beta = 8]. Other values are reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 0.--1. "PKCP_CONFIG,Value 1 indicates a PKCP with a 16x16 multiplier value 2 indicates a PKCP with a 32x32 multiplier other values reserved." "0,1,2,3" line.long 0x4 "HSM_PKA_PKA_SW_REV,PKA firmware revision and capabilities register." hexmask.long.byte 0x4 28.--31. 1. "SW_CAPABILITIES,4 bits binary encoding for the functionality implemented in the firmware. Refer to the SafeXcel-IP-29t2 Programmer Manual [3] for the firmware capabilities and the encoding of these bits." hexmask.long.byte 0x4 24.--27. 1. "SW_MAJOR_REV,4 bits binary encoding of the Authentec internal major firmware revision number." newline hexmask.long.byte 0x4 20.--23. 1. "SW_MINOR_REV,4 bits binary encoding of the Authentec internal minor firmware revision number." hexmask.long.byte 0x4 16.--19. 1. "SW_PATCH_LEVEL,4 bits binary encoding of the Authentec internal firmware patch level initial release will carry value zero. Patches are used to remove bugs without changing the functionality or interface of a module - see the release notes delivered.." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED_1,Bits should be ignored on a read." hexmask.long.byte 0x4 8.--11. 1. "CUSTOM_MAJOR_REV,4 bits binary encoding of the TI specific major firmware revision number." newline hexmask.long.byte 0x4 4.--7. 1. "CUSTOM_MINOR_REV,4 bits binary encoding of the TI specific minor firmware revision number." hexmask.long.byte 0x4 0.--3. 1. "CUSTOM_PATCH_LEVEL,4 bits binary encoding of the TI specific firmware patch level initial release will carry value zero. Patches are used to remove bugs without changing the functionality or interface of a module - see the release notes delivered with.." line.long 0x8 "HSM_PKA_PKA_REVISION,PKA HW revision register." hexmask.long.byte 0x8 28.--31. 1. "RESERVED_1,Bits should be ignored on a read." hexmask.long.byte 0x8 24.--27. 1. "HW_MAJOR_REV,4 bits binary encoding of the major hardware revision number." newline hexmask.long.byte 0x8 20.--23. 1. "HW_MINOR_REV,4 bits binary encoding of the minor hardware revision number." hexmask.long.byte 0x8 16.--19. 1. "HW_PATCH_LEVEL,4 bits binary encoding of the hardware patch level initial release will carry value zero. Patches are used to remove bugs without changing the functionality or interface of a module - see the release notes delivered with the package." newline hexmask.long.byte 0x8 8.--15. 1. "EIP_NR_COMPL,Bit-by-bit logic complement of bits [7:0] EIP-28 gives 0xE3." hexmask.long.byte 0x8 0.--7. 1. "EIP_NR,8 bits binary encoding of the EIP number EIP-28 gives 0x1C." group.long 0x400++0x47 line.long 0x0 "HSM_PKA_GF2M_OPERAND_A_0,Operand A registers." hexmask.long 0x0 0.--31. 1. "OPERAND_A,Operand A register [31:0]" line.long 0x4 "HSM_PKA_GF2M_OPERAND_A_1,Operand A registers." hexmask.long 0x4 0.--31. 1. "OPERAND_A,Operand A register [63:32]" line.long 0x8 "HSM_PKA_GF2M_OPERAND_A_2,Operand A registers." hexmask.long 0x8 0.--31. 1. "OPERAND_A,Operand A register [95:64]" line.long 0xC "HSM_PKA_GF2M_OPERAND_A_3,Operand A registers." hexmask.long 0xC 0.--31. 1. "OPERAND_A,Operand A register [127:96]" line.long 0x10 "HSM_PKA_GF2M_OPERAND_A_4,Operand A registers." hexmask.long 0x10 0.--31. 1. "OPERAND_A,Operand A register [159:128]" line.long 0x14 "HSM_PKA_GF2M_OPERAND_A_5,Operand A registers." hexmask.long 0x14 0.--31. 1. "OPERAND_A,Operand A register [191:160]" line.long 0x18 "HSM_PKA_GF2M_OPERAND_A_6,Operand A registers." hexmask.long 0x18 0.--31. 1. "OPERAND_A,Operand A register [223:192]" line.long 0x1C "HSM_PKA_GF2M_OPERAND_A_7,Operand A registers." hexmask.long 0x1C 0.--31. 1. "OPERAND_A,Operand A register [255:224]" line.long 0x20 "HSM_PKA_GF2M_OPERAND_A_8,Operand A registers." hexmask.long 0x20 0.--31. 1. "OPERAND_A,Operand A register [287:256]" line.long 0x24 "HSM_PKA_GF2M_OPERAND_A_9,Operand A registers." hexmask.long 0x24 0.--31. 1. "OPERAND_A,Operand A register [319:288]" line.long 0x28 "HSM_PKA_GF2M_OPERAND_A_10,Operand A registers." hexmask.long 0x28 0.--31. 1. "OPERAND_A,Operand A register [351:320]" line.long 0x2C "HSM_PKA_GF2M_OPERAND_A_11,Operand A registers." hexmask.long 0x2C 0.--31. 1. "OPERAND_A,Operand A register [383:352]" line.long 0x30 "HSM_PKA_GF2M_OPERAND_A_12,Operand A registers." hexmask.long 0x30 0.--31. 1. "OPERAND_A,Operand A register [415:384]" line.long 0x34 "HSM_PKA_GF2M_OPERAND_A_13,Operand A registers." hexmask.long 0x34 0.--31. 1. "OPERAND_A,Operand A register [447:416]" line.long 0x38 "HSM_PKA_GF2M_OPERAND_A_14,Operand A registers." hexmask.long 0x38 0.--31. 1. "OPERAND_A,Operand A register [479:448]" line.long 0x3C "HSM_PKA_GF2M_OPERAND_A_15,Operand A registers." hexmask.long 0x3C 0.--31. 1. "OPERAND_A,Operand A register [511:480]" line.long 0x40 "HSM_PKA_GF2M_OPERAND_A_16,Operand A registers." hexmask.long 0x40 0.--31. 1. "OPERAND_A,Operand A register [543:512]" line.long 0x44 "HSM_PKA_GF2M_OPERAND_A_17,Operand A registers." hexmask.long 0x44 0.--27. 1. "OPERAND_A,Operand A register [571:544]" group.long 0x480++0x47 line.long 0x0 "HSM_PKA_GF2M_OPERAND_B_0,Operand B registers." hexmask.long 0x0 0.--31. 1. "OPERAND_B,Operand B register [31:0]" line.long 0x4 "HSM_PKA_GF2M_OPERAND_B_1,Operand B registers." hexmask.long 0x4 0.--31. 1. "OPERAND_B,Operand B register [63:32]" line.long 0x8 "HSM_PKA_GF2M_OPERAND_B_2,Operand B registers." hexmask.long 0x8 0.--31. 1. "OPERAND_B,Operand B register [95:64]" line.long 0xC "HSM_PKA_GF2M_OPERAND_B_3,Operand B registers." hexmask.long 0xC 0.--31. 1. "OPERAND_B,Operand B register [127:96]" line.long 0x10 "HSM_PKA_GF2M_OPERAND_B_4,Operand B registers." hexmask.long 0x10 0.--31. 1. "OPERAND_B,Operand B register [159:128]" line.long 0x14 "HSM_PKA_GF2M_OPERAND_B_5,Operand B registers." hexmask.long 0x14 0.--31. 1. "OPERAND_B,Operand B register [191:160]" line.long 0x18 "HSM_PKA_GF2M_OPERAND_B_6,Operand B registers." hexmask.long 0x18 0.--31. 1. "OPERAND_B,Operand B register [223:192]" line.long 0x1C "HSM_PKA_GF2M_OPERAND_B_7,Operand B registers." hexmask.long 0x1C 0.--31. 1. "OPERAND_B,Operand B register [255:224]" line.long 0x20 "HSM_PKA_GF2M_OPERAND_B_8,Operand B registers." hexmask.long 0x20 0.--31. 1. "OPERAND_B,Operand B register [287:256]" line.long 0x24 "HSM_PKA_GF2M_OPERAND_B_9,Operand B registers." hexmask.long 0x24 0.--31. 1. "OPERAND_B,Operand B register [319:288]" line.long 0x28 "HSM_PKA_GF2M_OPERAND_B_10,Operand B registers." hexmask.long 0x28 0.--31. 1. "OPERAND_B,Operand B register [351:320]" line.long 0x2C "HSM_PKA_GF2M_OPERAND_B_11,Operand B registers." hexmask.long 0x2C 0.--31. 1. "OPERAND_B,Operand B register [383:352]" line.long 0x30 "HSM_PKA_GF2M_OPERAND_B_12,Operand B registers." hexmask.long 0x30 0.--31. 1. "OPERAND_B,Operand B register [415:384]" line.long 0x34 "HSM_PKA_GF2M_OPERAND_B_13,Operand B registers." hexmask.long 0x34 0.--31. 1. "OPERAND_B,Operand B register [447:416]" line.long 0x38 "HSM_PKA_GF2M_OPERAND_B_14,Operand B registers." hexmask.long 0x38 0.--31. 1. "OPERAND_B,Operand B register [479:448]" line.long 0x3C "HSM_PKA_GF2M_OPERAND_B_15,Operand B registers." hexmask.long 0x3C 0.--31. 1. "OPERAND_B,Operand B register [511:480]" line.long 0x40 "HSM_PKA_GF2M_OPERAND_B_16,Operand B registers." hexmask.long 0x40 0.--31. 1. "OPERAND_B,Operand B register [543:512]" line.long 0x44 "HSM_PKA_GF2M_OPERAND_B_17,Operand B registers." hexmask.long 0x44 0.--27. 1. "OPERAND_B,Operand B register [571:544]" group.long 0x500++0x47 line.long 0x0 "HSM_PKA_GF2M_OPERAND_C_0,Operand C registers." hexmask.long 0x0 0.--31. 1. "OPERAND_C,Operand C register [31:0]" line.long 0x4 "HSM_PKA_GF2M_OPERAND_C_1,Operand C registers." hexmask.long 0x4 0.--31. 1. "OPERAND_C,Operand C register [63:32]" line.long 0x8 "HSM_PKA_GF2M_OPERAND_C_2,Operand C registers." hexmask.long 0x8 0.--31. 1. "OPERAND_C,Operand C register [95:64]" line.long 0xC "HSM_PKA_GF2M_OPERAND_C_3,Operand C registers." hexmask.long 0xC 0.--31. 1. "OPERAND_C,Operand C register [127:96]" line.long 0x10 "HSM_PKA_GF2M_OPERAND_C_4,Operand C registers." hexmask.long 0x10 0.--31. 1. "OPERAND_C,Operand C register [159:128]" line.long 0x14 "HSM_PKA_GF2M_OPERAND_C_5,Operand C registers." hexmask.long 0x14 0.--31. 1. "OPERAND_C,Operand C register [191:160]" line.long 0x18 "HSM_PKA_GF2M_OPERAND_C_6,Operand C registers." hexmask.long 0x18 0.--31. 1. "OPERAND_C,Operand C register [223:192]" line.long 0x1C "HSM_PKA_GF2M_OPERAND_C_7,Operand C registers." hexmask.long 0x1C 0.--31. 1. "OPERAND_C,Operand C register [255:224]" line.long 0x20 "HSM_PKA_GF2M_OPERAND_C_8,Operand C registers." hexmask.long 0x20 0.--31. 1. "OPERAND_C,Operand C register [287:256]" line.long 0x24 "HSM_PKA_GF2M_OPERAND_C_9,Operand C registers." hexmask.long 0x24 0.--31. 1. "OPERAND_C,Operand C register [319:288]" line.long 0x28 "HSM_PKA_GF2M_OPERAND_C_10,Operand C registers." hexmask.long 0x28 0.--31. 1. "OPERAND_C,Operand C register [351:320]" line.long 0x2C "HSM_PKA_GF2M_OPERAND_C_11,Operand C registers." hexmask.long 0x2C 0.--31. 1. "OPERAND_C,Operand C register [383:352]" line.long 0x30 "HSM_PKA_GF2M_OPERAND_C_12,Operand C registers." hexmask.long 0x30 0.--31. 1. "OPERAND_C,Operand C register [415:384]" line.long 0x34 "HSM_PKA_GF2M_OPERAND_C_13,Operand C registers." hexmask.long 0x34 0.--31. 1. "OPERAND_C,Operand C register [447:416]" line.long 0x38 "HSM_PKA_GF2M_OPERAND_C_14,Operand C registers." hexmask.long 0x38 0.--31. 1. "OPERAND_C,Operand C register [479:448]" line.long 0x3C "HSM_PKA_GF2M_OPERAND_C_15,Operand C registers." hexmask.long 0x3C 0.--31. 1. "OPERAND_C,Operand C register [511:480]" line.long 0x40 "HSM_PKA_GF2M_OPERAND_C_16,Operand C registers." hexmask.long 0x40 0.--31. 1. "OPERAND_C,Operand C register [543:512]" line.long 0x44 "HSM_PKA_GF2M_OPERAND_C_17,Operand C registers." hexmask.long 0x44 0.--27. 1. "OPERAND_C,Operand C register [571:544]" group.long 0x580++0x47 line.long 0x0 "HSM_PKA_GF2M_OPERAND_D_0,Operand D registers." hexmask.long 0x0 0.--31. 1. "OPERAND_D,Operand D register [31:0]" line.long 0x4 "HSM_PKA_GF2M_OPERAND_D_1,Operand D registers." hexmask.long 0x4 0.--31. 1. "OPERAND_D,Operand D register [63:32]" line.long 0x8 "HSM_PKA_GF2M_OPERAND_D_2,Operand D registers." hexmask.long 0x8 0.--31. 1. "OPERAND_D,Operand D register [95:64]" line.long 0xC "HSM_PKA_GF2M_OPERAND_D_3,Operand D registers." hexmask.long 0xC 0.--31. 1. "OPERAND_D,Operand D register [127:96]" line.long 0x10 "HSM_PKA_GF2M_OPERAND_D_4,Operand D registers." hexmask.long 0x10 0.--31. 1. "OPERAND_D,Operand D register [159:128]" line.long 0x14 "HSM_PKA_GF2M_OPERAND_D_5,Operand D registers." hexmask.long 0x14 0.--31. 1. "OPERAND_D,Operand D register [191:160]" line.long 0x18 "HSM_PKA_GF2M_OPERAND_D_6,Operand D registers." hexmask.long 0x18 0.--31. 1. "OPERAND_D,Operand D register [223:192]" line.long 0x1C "HSM_PKA_GF2M_OPERAND_D_7,Operand D registers." hexmask.long 0x1C 0.--31. 1. "OPERAND_D,Operand D register [255:224]" line.long 0x20 "HSM_PKA_GF2M_OPERAND_D_8,Operand D registers." hexmask.long 0x20 0.--31. 1. "OPERAND_D,Operand D register [287:256]" line.long 0x24 "HSM_PKA_GF2M_OPERAND_D_9,Operand D registers." hexmask.long 0x24 0.--31. 1. "OPERAND_D,Operand D register [319:288]" line.long 0x28 "HSM_PKA_GF2M_OPERAND_D_10,Operand D registers." hexmask.long 0x28 0.--31. 1. "OPERAND_D,Operand D register [351:320]" line.long 0x2C "HSM_PKA_GF2M_OPERAND_D_11,Operand D registers." hexmask.long 0x2C 0.--31. 1. "OPERAND_D,Operand D register [383:352]" line.long 0x30 "HSM_PKA_GF2M_OPERAND_D_12,Operand D registers." hexmask.long 0x30 0.--31. 1. "OPERAND_D,Operand D register [415:384]" line.long 0x34 "HSM_PKA_GF2M_OPERAND_D_13,Operand D registers." hexmask.long 0x34 0.--31. 1. "OPERAND_D,Operand D register [447:416]" line.long 0x38 "HSM_PKA_GF2M_OPERAND_D_14,Operand D registers." hexmask.long 0x38 0.--31. 1. "OPERAND_D,Operand D register [479:448]" line.long 0x3C "HSM_PKA_GF2M_OPERAND_D_15,Operand D registers." hexmask.long 0x3C 0.--31. 1. "OPERAND_D,Operand D register [511:480]" line.long 0x40 "HSM_PKA_GF2M_OPERAND_D_16,Operand D registers." hexmask.long 0x40 0.--31. 1. "OPERAND_D,Operand D register [543:512]" line.long 0x44 "HSM_PKA_GF2M_OPERAND_D_17,Operand D registers." hexmask.long 0x44 0.--27. 1. "OPERAND_D,Operand D register [571:544]" group.long 0x600++0x47 line.long 0x0 "HSM_PKA_GF2M_POLYNOMIAL_0,GF2M_POLYNOMIAL_0." hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,Polynomial register [31:0]" line.long 0x4 "HSM_PKA_GF2M_POLYNOMIAL_1,GF2M_POLYNOMIAL_1." hexmask.long 0x4 0.--31. 1. "POLYNOMIAL,Polynomial register [63:32]" line.long 0x8 "HSM_PKA_GF2M_POLYNOMIAL_2,GF2M_POLYNOMIAL_2." hexmask.long 0x8 0.--31. 1. "POLYNOMIAL,Polynomial register [95:64]" line.long 0xC "HSM_PKA_GF2M_POLYNOMIAL_3,GF2M_POLYNOMIAL_3." hexmask.long 0xC 0.--31. 1. "POLYNOMIAL,Polynomial register [127:96]" line.long 0x10 "HSM_PKA_GF2M_POLYNOMIAL_4,GF2M_POLYNOMIAL_4." hexmask.long 0x10 0.--31. 1. "POLYNOMIAL,Polynomial register [159:128]" line.long 0x14 "HSM_PKA_GF2M_POLYNOMIAL_5,GF2M_POLYNOMIAL_5." hexmask.long 0x14 0.--31. 1. "POLYNOMIAL,Polynomial register [191:160]" line.long 0x18 "HSM_PKA_GF2M_POLYNOMIAL_6,GF2M_POLYNOMIAL_6." hexmask.long 0x18 0.--31. 1. "POLYNOMIAL,Polynomial register [223:192]" line.long 0x1C "HSM_PKA_GF2M_POLYNOMIAL_7,GF2M_POLYNOMIAL_7." hexmask.long 0x1C 0.--31. 1. "POLYNOMIAL,Polynomial register [255:224]" line.long 0x20 "HSM_PKA_GF2M_POLYNOMIAL_8,GF2M_POLYNOMIAL_8." hexmask.long 0x20 0.--31. 1. "POLYNOMIAL,Polynomial register [287:256]" line.long 0x24 "HSM_PKA_GF2M_POLYNOMIAL_9,GF2M_POLYNOMIAL_9." hexmask.long 0x24 0.--31. 1. "POLYNOMIAL,Polynomial register [319:288]" line.long 0x28 "HSM_PKA_GF2M_POLYNOMIAL_10,GF2M_POLYNOMIAL_10." hexmask.long 0x28 0.--31. 1. "POLYNOMIAL,Polynomial register [351:320]" line.long 0x2C "HSM_PKA_GF2M_POLYNOMIAL_11,GF2M_POLYNOMIAL_11." hexmask.long 0x2C 0.--31. 1. "POLYNOMIAL,Polynomial register [383:352]" line.long 0x30 "HSM_PKA_GF2M_POLYNOMIAL_12,GF2M_POLYNOMIAL_12." hexmask.long 0x30 0.--31. 1. "POLYNOMIAL,Polynomial register [415:384]" line.long 0x34 "HSM_PKA_GF2M_POLYNOMIAL_13,GF2M_POLYNOMIAL_13." hexmask.long 0x34 0.--31. 1. "POLYNOMIAL,Polynomial register [447:416]" line.long 0x38 "HSM_PKA_GF2M_POLYNOMIAL_14,GF2M_POLYNOMIAL_14." hexmask.long 0x38 0.--31. 1. "POLYNOMIAL,Polynomial register [479:448]" line.long 0x3C "HSM_PKA_GF2M_POLYNOMIAL_15,GF2M_POLYNOMIAL_15." hexmask.long 0x3C 0.--31. 1. "POLYNOMIAL,Polynomial register [511:480]" line.long 0x40 "HSM_PKA_GF2M_POLYNOMIAL_16,GF2M_POLYNOMIAL_16." hexmask.long 0x40 0.--31. 1. "POLYNOMIAL,Polynomial register [543:512]" line.long 0x44 "HSM_PKA_GF2M_POLYNOMIAL_17,GF2M_POLYNOMIAL_17." hexmask.long 0x44 0.--27. 1. "POLYNOMIAL,Polynomial register [571:544]" group.long 0x700++0xB line.long 0x0 "HSM_PKA_GF2M_CMD,Command register." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED_4,These bits should be written with zeroes and ignored on a read." bitfld.long 0x0 13.--14. "TGT,Target address1:00b= GF2M_OPERAND_A 01b= GF2M_OPERAND_B 10b= GF2M_OPERAND_C 11b= GF2M_OPERAND_D" "0,1,2,3" newline bitfld.long 0x0 12. "RESERVED_3,These bits should be written with zeroes and ignored on a read." "0,1" bitfld.long 0x0 10.--11. "SRC1,Source address1:00b= GF2M_OPERAND_A 01b= GF2M_OPERAND_B 10b= GF2M_OPERAND_C 11b= GF2M_OPERAND_D" "0,1,2,3" newline bitfld.long 0x0 9. "RESERVED_2,These bits should be written with zeroes and ignored on a read." "0,1" bitfld.long 0x0 7.--8. "OPTION,Source address0:00b= GF2M_OPERAND_A 01b= GF2M_OPERAND_B 10b= GF2M_OPERAND_C 11b= GF2M_OPERAND_D" "0,1,2,3" newline bitfld.long 0x0 4.--5. "RESERVED_1,These bits should be written with zeroes and ignored on a read." "0,1,2,3" bitfld.long 0x0 1.--3. "OPCODE,Command opcode:000bClear tgt operand register.001bCopy src0 operand to tgt operand register.010bGF[2m] Add src0 and src1 operands write result to tgt operand.011bGF[2m] Multilpy src0 and src1 operands write result to tgt.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "CMD_SUBMIT_CMD_BUF_FULL,Setting this bit [cmd_submit] submits the command that is specified by the remaining bits in this register. The cmd_submit bit is self clearing. Writing this bit with0bhas no effect. Submitting a command always sets the busy bit.." "0,1" line.long 0x4 "HSM_PKA_GF2M_STAT,Status register." rbitfld.long 0x4 31. "BUSY,This status bit reads1bwhen the GF2m Engine is processing a command. The irq output is the inverted level of this bit." "0,1" hexmask.long.byte 0x4 26.--30. 1. "RESERVED_2,These bits should be written with zeroes and ignored on a read." newline hexmask.long.word 0x4 16.--25. 1. "SHIFT_VALUE,Represents the number of src0 operand right-shifts that was performed during the last 'shift-xor-loop ' operation. Note: In case the shift-xor-loop command did not find src0 bit [0] to become 'odd ' after [mul_rounds*mul_depth] cycles the.." rbitfld.long 0x4 15. "CMD_ERR,Command error. Set to1bby hardware when trying to start a processing using a non-valid opcode. This bit is automatically cleared to0bby hardware on a start of any [legal] operation. The command error is also triggered when the shift-xor-loop.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RESERVED_1,These bits should be written with zeroes and ignored on a read." rbitfld.long 0x4 5. "NO_MSB,Result of the 'degree ' operation: If the last read operand word contains only zeroes there is no MSB present in this word. In that case this bit will be1b" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "MSB_PTR,Result of the 'degree ' operation: Represents the index location of the MSB within the 32-bit operand word that was last read via the TCM interface." line.long 0x8 "HSM_PKA_GF2M_FIELDSIZE,Field size register." hexmask.long.word 0x8 18.--31. 1. "RESERVED_2,These bits should be written with zeroes and ignored on a read." bitfld.long 0x8 16.--17. "OP_SHIFT,This field must be populated with the 'operand shift ' value for the GF[2m] multiplication operation. The operand shift value is the offset from the MSB with respect to the left-shift boundaries. The operand shift value can be determined using.." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "RESERVED_1,These bits should be written with zeroes and ignored on a read." hexmask.long.byte 0x8 0.--7. 1. "FIELD_SIZE,This field must be populated with the number of multiplier rounds for the GF[2m] operation. The number of multiplier rounds depends on the multiplier depth and the field size:mul_rounds = [field size/mul_depth]+1. The minimum value for this.." group.long 0x7F8++0x7 line.long 0x0 "HSM_PKA_GF2M_OPTIONS,GF2m module options register." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_2,These bits should be written with zeroes and ignored on a read." hexmask.long.word 0x0 16.--27. 1. "OPERAND_SIZE,Operand size. Represents the width of the operand registers inside the GF2m Engine. Value 0x23c means that the operand registers are 572 bits wide. The operand registers are one bit wider than the maximum supported filed size." newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_1,These bits should be written with zeroes and ignored on a read." hexmask.long.byte 0x0 4.--7. 1. "MUL_DEPTH,Multiplier matrix depth. Represents the number of AND-XOR matrix rows implemented in the GF2m Engine. Value 0x4 means that multiplier matrix contains four levels of AND-XOR matrix rows." newline hexmask.long.byte 0x0 0.--3. 1. "OPERANDS,Number of implemented operand registers. Value 0x4 means four operands [A up to D]." line.long 0x4 "HSM_PKA_GF2M_VERSION,GF2m module version register." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_2,These bits should be written with zeroes and ignored on a read." hexmask.long.byte 0x4 24.--27. 1. "PATCH_LEVEL,These bits encode the hardware patch level of the GF2m Engine" newline hexmask.long.byte 0x4 20.--23. 1. "MINOR_VERSION,These bits encode the minor version number of the GF2m Engine" hexmask.long.byte 0x4 16.--19. 1. "MAJOR_VERSION,These bits encode the major version number of the GF2m Engine" newline hexmask.long.word 0x4 0.--15. 1. "RESERVED_1,These bits should be written with zeroes and ignored on a read." rgroup.long 0x1FE0++0x3 line.long 0x0 "HSM_PKA_PKA_REV,Shell HW revision." hexmask.long 0x0 0.--31. 1. "REVISION,The revision number of this EIP-29t2 module" group.long 0x1FE8++0x3 line.long 0x0 "HSM_PKA_PKA_CLK_CTRL,PKA clock control." hexmask.long.byte 0x0 23.--30. 1. "RESERVED_3,This bit should be written with zero and ignored on reads." bitfld.long 0x0 22. "DATA_RAM_CLKEN,Clock enable status of data_ram_clk. The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" newline bitfld.long 0x0 21. "GF2M_CLKEN,Clock enable status of gf2m_clk.The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" bitfld.long 0x0 20. "LNME_REG_CLKEN,Clock enable status of lnme_reg_clk. The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" newline bitfld.long 0x0 19. "LNME_CLKEN,Clock enable status of lnme_clk. The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" bitfld.long 0x0 18. "PKCP_CLKEN,Clock enable status of pkcp_clk.The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" newline bitfld.long 0x0 17. "SEQ_CLKEN,Clock enable status of seq_clk. The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" bitfld.long 0x0 16. "REG_CLKEN,Clock enable status of reg_clk. The reset value of this bit is0bbut after reset this bit is immediately refreshed with the actual clock" "0,1" newline bitfld.long 0x0 15. "RESERVED_2,This bit should be written with zero and ignored on reads." "0,1" bitfld.long 0x0 14. "DATA_RAM_CLK_OFF,Force data_ram_clk OFF" "0,1" newline bitfld.long 0x0 13. "GF2M_CLK_OFF,Force gf2m_clk OFF" "0,1" bitfld.long 0x0 12. "LNME_REG_CLK_OFF,Force lnme_reg_clk OFF" "0,1" newline bitfld.long 0x0 11. "LNME_CLK_OFF,Force lnme_clk OFF" "0,1" bitfld.long 0x0 10. "PKCP_CLK_OFF,Force pkcp_clk OFF" "0,1" newline bitfld.long 0x0 9. "SEQ_CLK_OFF,Force seq_clk OFF" "0,1" bitfld.long 0x0 8. "REG_CLK_OFF,Force reg_clk OFF" "0,1" newline bitfld.long 0x0 7. "RESERVED_1,This bit should be written with zero and ignored on reads." "0,1" bitfld.long 0x0 6. "DATA_RAM_CLK_ON,Force data_ram_clk ON" "0,1" newline bitfld.long 0x0 5. "GF2M_CLK_ON,Force gf2m_clk ON" "0,1" bitfld.long 0x0 4. "LNME_REG_CLK_ON,Force lnme_reg_clk ON" "0,1" newline bitfld.long 0x0 3. "LNME_CLK_ON,Force lnme_clk ON" "0,1" bitfld.long 0x0 2. "PKCP_CLK_ON,Force pkcp_clk ON" "0,1" newline bitfld.long 0x0 1. "SEQ_CLK_ON,Force seq_clk ON" "0,1" bitfld.long 0x0 0. "REG_CLK_ON,Force reg_clk ON" "0,1" group.long 0x1FF0++0xB line.long 0x0 "HSM_PKA_PKA_SYSCONFIG,Shell configuration." hexmask.long 0x0 6.--31. 1. "RESERVED_3,This bit should be written with zero and ignored on reads." bitfld.long 0x0 4.--5. "IDLEMODE,Selects the module Idle mode. These bit combinations are only available: 00 = Force Idle mode: An IdleRequest is immediately acknowledged. 01 = No Idle mode: An IdleRequest is never acknowledged. 10 = Smart Idle mode: An IdleRequest is not.." "0: Force Idle mode: An IdleRequest is immediately..,1: No Idle mode: An IdleRequest is never acknowledged,?,?" newline bitfld.long 0x0 2.--3. "RESERVED_2,This bit should be written with zero and ignored on reads." "0,1,2,3" rbitfld.long 0x0 1. "SOFTRESET,If set to 1 the soft reset sequence is applied to the module." "0,1" newline bitfld.long 0x0 0. "RESERVED_1,This bit should be written with zero and ignored on reads." "0,1" line.long 0x4 "HSM_PKA_PKA_SYSSTATUS,Shell status." hexmask.long 0x4 1.--31. 1. "RESERVED_1,These bits should be written with zero and ignored on reads." rbitfld.long 0x4 0. "RESETDONE,When this bit reads1b the module reset is completed." "0,1" line.long 0x8 "HSM_PKA_PKA_IRQSTATUS,Interrupt status." hexmask.long.word 0x8 19.--31. 1. "RESERVED_2,These bits should not be written and ignored on reads." rbitfld.long 0x8 18. "GF2MIRQSTATRAW,Raw GF2m Engine ready interrupt status. Note: The reset value of this bit is0b but this bit becomes1bdirectly after reset." "0,1" newline rbitfld.long 0x8 17. "LNMEIRQSTATRAW,Raw combined LNME0 & LNME1 ready interrupt status. Note: The reset value of this bit is0b but this bit becomes1bdirectly after reset." "0,1" rbitfld.long 0x8 16. "PKAIRQSTATRAW,Raw main PKA interrupt status. The reset value of this bit is zero but it will become high after a few cycles to indicate that the PKA is ready to be used. For the Program ROM configuration this is within a few cycles after a reset for.." "0,1" newline hexmask.long.word 0x8 3.--15. 1. "RESERVED_1,These bits should not be written and ignored on reads." rbitfld.long 0x8 2. "GF2MIRQSTAT,Masked GF2m Engine ready interrupt status.This interrupt can be enbled when setting the GF2mIrqEn bit in the PKA_IRQENABLE register. This interrupt can be cleared by Writing this bit. Writing1bclears the GF2m Engine ready interrupt.This bit.." "0,1" newline rbitfld.long 0x8 1. "LNMEIRQSTAT,Masked combined LNME0 & LNME1 ready interrupt status.This interrupt can be enbled when setting the LNMEIrqEn bit in the PKA_IRQENABLE register. This interrupt can be cleared by Writing this bit. Writing1bclears the combined LNME0 & LNME1.." "0,1" rbitfld.long 0x8 0. "PKAIRQSTAT,Masked main PKA interrupt status.This interrupt can be enbled when setting the PkaIrqEn bit in the PKA_IRQENABLE register. This interrupt can be cleared by Writing this bit. Writing1bclears the main PKA interrupt. This bit is self-clearing; it.." "0,1" wgroup.long 0x1FFC++0x3 line.long 0x0 "HSM_PKA_PKA_IRQENABLE,Interrupt enable." hexmask.long 0x0 3.--31. 1. "RESERVED_1,These bits should not be written and ignored on reads." bitfld.long 0x0 2. "GF2MIRQEN,Enable the GF2m Engine interrupt." "0,1" newline bitfld.long 0x0 1. "LNMEIRQEN,Enable the combined LNME0 & LNME1 ready interrupt" "0,1" bitfld.long 0x0 0. "PKAIRQEN,Enable the PKA interrupt." "0,1" tree.end tree "HSM0_HSM_PKA_RAM" base ad:0xCE014000 group.long 0x0++0x3 line.long 0x0 "HSM_PKA_RAM_START" hexmask.long 0x0 0.--31. 1. "START,Start address" group.long 0x1FFFC++0x3 line.long 0x0 "HSM_PKA_RAM_END" hexmask.long 0x0 0.--31. 1. "END,End address" tree.end tree "HSM0_HSM_SHA" base ad:0xCE004000 group.long 0x0++0x4B line.long 0x0 "HSM_SHA_S_ODIGEST_A,WRITE: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [31:0] for HMAC key proc READ: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2" hexmask.long 0x0 0.--31. 1. "DATA,data" line.long 0x4 "HSM_SHA_S_ODIGEST_B,WRITE: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [63:32] for HMAC key proc READ: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2" hexmask.long 0x4 0.--31. 1. "DATA,data" line.long 0x8 "HSM_SHA_S_ODIGEST_C,WRITE: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / HMAC Key [95:64] for HMAC key proc READ: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2" hexmask.long 0x8 0.--31. 1. "DATA,data" line.long 0xC "HSM_SHA_S_ODIGEST_D,WRITE: Outer Digest [31:0] for MD5 [63:31] for SHA-1 [159:128] for SHA-2 / HMAC Key [127:96] for HMAC key proc READ: Outer Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2" hexmask.long 0xC 0.--31. 1. "DATA,data" line.long 0x10 "HSM_SHA_S_ODIGEST_E,WRITE: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [159:128] for HMAC key proc READ: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2" hexmask.long 0x10 0.--31. 1. "DATA,data" line.long 0x14 "HSM_SHA_S_ODIGEST_F,WRITE: Outer Digest [95:64] for SHA-2 / HMAC Key [191:160] for HMAC key proc READ: Outer Digest [95:64] for SHA-2" hexmask.long 0x14 0.--31. 1. "DATA,data" line.long 0x18 "HSM_SHA_S_ODIGEST_G,WRITE: Outer Digest [63:32] for SHA-2 / HMAC Key [223:192] for HMAC key proc READ: Outer Digest [63:32] for SHA-2" hexmask.long 0x18 0.--31. 1. "DATA,data" line.long 0x1C "HSM_SHA_S_ODIGEST_H,WRITE: Outer Digest [31:0] for SHA-2 / HMAC Key [255:224] for HMAC key proc READ: Outer Digest [31:0] for SHA-2" hexmask.long 0x1C 0.--31. 1. "DATA,data" line.long 0x20 "HSM_SHA_S_IDIGEST_A,WRITE: Inner / Initial Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [287:256] for HMAC key proc READ: Intermediate / Inner Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / Result.." hexmask.long 0x20 0.--31. 1. "DATA,data" line.long 0x24 "HSM_SHA_S_IDIGEST_B,WRITE: Inner / Initial Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [319:288] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / Result Digest/MAC.." hexmask.long 0x24 0.--31. 1. "DATA,data" line.long 0x28 "HSM_SHA_S_IDIGEST_C,WRITE: Inner / Initial Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA- 2 / HMAC Key [351:320] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / Result Digest/MAC.." hexmask.long 0x28 0.--31. 1. "DATA,data" line.long 0x2C "HSM_SHA_S_IDIGEST_D,WRITE: Inner / Initial Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / HMAC Key [383:352] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / Result Digest/MAC.." hexmask.long 0x2C 0.--31. 1. "DATA,data" line.long 0x30 "HSM_SHA_S_IDIGEST_E,WRITE: Inner / Initial Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [415:384] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-1 [127:96] for SHA-2 / Result Digest/MAC [31:0] for SHA-1 [95:64] for SHA-2 224.." hexmask.long 0x30 0.--31. 1. "DATA,data" line.long 0x34 "HSM_SHA_S_IDIGEST_F,WRITE: Inner / Initial Digest [95:64] for SHA-2 / HMAC Key [447:416] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for SHA-2 / Result Digest/MAC [63:32] for SHA-2 224 [95:64] for SHA-2 256." hexmask.long 0x34 0.--31. 1. "DATA,data" line.long 0x38 "HSM_SHA_S_IDIGEST_G,WRITE: Inner / Initial Digest [63:32] for SHA-2 / HMAC Key [479:448] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 224 [63:32] for SHA-2 256." hexmask.long 0x38 0.--31. 1. "DATA,data" line.long 0x3C "HSM_SHA_S_IDIGEST_H,WRITE: Inner / Initial Digest [31:0] for SHA-2 / HMAC Key [511:480] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 256." hexmask.long 0x3C 0.--31. 1. "DATA,data" line.long 0x40 "HSM_SHA_S_DIGEST_COUNT,WRITE: Initial Digest Count ([31:6] only [5:0] assumed 0) READ: Result / IntermediateDigest Count The initial digest byte count for hash/HMAC continue operations (HMAC Key Processing = 0 and Use Algorithm Constants = 0) on the.." hexmask.long 0x40 0.--31. 1. "DATA,data" line.long 0x44 "HSM_SHA_S_MODE,Register SHA_MODE." bitfld.long 0x44 7. "HMAC_OUTER_HASH,The HMAC Outer Hash is performed on the hash digest when the inner hash hash finished [block length exhausted and final hash performed if close_hash is 1]. This bit should normally be set together with close_hash to finish the inner hash.." "0,1" bitfld.long 0x44 5. "HMAC_KEY_PROC,Performs HMAC key processing on the 512 bit HMAC key loaded into the SHA_P_IDIGEST_{A to H} and SHA_P_ODIGEST_{A to H} register block. Once HMAC key processing is finished this bit is automatically cleared and the resulting Inner and Outer.." "0,1" bitfld.long 0x44 4. "CLOSE_HASH,Performs the padding the hash/HMAC will be 'closed' at the end of the block as per MD5/SHA-1/SHA-2 specification [i.e. appropriate padding is added] or no padding is done allowing the hash to be continued later. However if the hash/HMAC is not.." "0,1" bitfld.long 0x44 3. "ALGO_CONSTANT,The initial digest register will be overwritten with the algorithm constants for the selected algorithm when hashing and the initial digest count register will be reset to 0. This will start a normal hash operation. When continuing an.." "0,1" newline bitfld.long 0x44 1.--2. "ALGO,These bits select the hash algorithm to be used for processing: 0 md5_128 algorithm 0x1 sha1_160 algorithm 0x2 sha2_224 algorithm 0x3 sha2_256 algorithm" "0,1,2,3" line.long 0x48 "HSM_SHA_S_LENGTH,WRITE: Block Length / Remaining Byte Count (bytes) READ: Remaining Byte Count. The value programmed MUST be a 64-byte multiple if Close Hash is set to 0. This register is also the trigger to start processing: once this register is.." hexmask.long 0x48 0.--31. 1. "DATA,data" wgroup.long 0x80++0x3F line.long 0x0 "HSM_SHA_S_DATA0_IN,Data input message 0" hexmask.long 0x0 0.--31. 1. "DATA0_IN,data" line.long 0x4 "HSM_SHA_S_DATA1_IN,Data input message 1" hexmask.long 0x4 0.--31. 1. "DATA1_IN,data" line.long 0x8 "HSM_SHA_S_DATA2_IN,Data input message 2" hexmask.long 0x8 0.--31. 1. "DATA2_IN,data" line.long 0xC "HSM_SHA_S_DATA3_IN,Data input message 3" hexmask.long 0xC 0.--31. 1. "DATA3_IN,data" line.long 0x10 "HSM_SHA_S_DATA4_IN,Data input message 4" hexmask.long 0x10 0.--31. 1. "DATA4_IN,data" line.long 0x14 "HSM_SHA_S_DATA5_IN,Data input message 5" hexmask.long 0x14 0.--31. 1. "DATA5_IN,data" line.long 0x18 "HSM_SHA_S_DATA6_IN,Data input message 6" hexmask.long 0x18 0.--31. 1. "DATA6_IN,data" line.long 0x1C "HSM_SHA_S_DATA7_IN,Data input message 7" hexmask.long 0x1C 0.--31. 1. "DATA7_IN,data" line.long 0x20 "HSM_SHA_S_DATA8_IN,Data input message 8" hexmask.long 0x20 0.--31. 1. "DATA8_IN,data" line.long 0x24 "HSM_SHA_S_DATA9_IN,Data input message 9" hexmask.long 0x24 0.--31. 1. "DATA9_IN,data" line.long 0x28 "HSM_SHA_S_DATA10_IN,Data input message 10." hexmask.long 0x28 0.--31. 1. "DATA10_IN,data" line.long 0x2C "HSM_SHA_S_DATA11_IN,Data input message 11." hexmask.long 0x2C 0.--31. 1. "DATA11_IN,data" line.long 0x30 "HSM_SHA_S_DATA12_IN,Data input message 12." hexmask.long 0x30 0.--31. 1. "DATA12_IN,data" line.long 0x34 "HSM_SHA_S_DATA13_IN,Data input message 13." hexmask.long 0x34 0.--31. 1. "DATA13_IN,data" line.long 0x38 "HSM_SHA_S_DATA14_IN,Data input message 14." hexmask.long 0x38 0.--31. 1. "DATA14_IN,data" line.long 0x3C "HSM_SHA_S_DATA15_IN,Data input message 15." hexmask.long 0x3C 0.--31. 1. "DATA15_IN,data" rgroup.long 0x100++0x3 line.long 0x0 "HSM_SHA_S_REVISION,Register SHA_REV." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current. Read 0 Legacy ASP or WTBU scheme Read 0x1 Highlander 0.8 scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned." hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner. RTL follows a numbering such as X.Y.R.Z which are explained in this table. R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner. X changes ONLY when: [1] There is a major feature addition. An example would be adding Master Mode to Utopia Level2. The Func field [or Class/Type in old PID format] will remain the same. X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers. Read 0 Non custom [standard] revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner. Y changes ONLY when: [1] Features are scaled [up or down]. Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP.." group.long 0x110++0x7 line.long 0x0 "HSM_SHA_S_SYSCONFIG,Register SHA_SYSCONFIG." bitfld.long 0x0 7. "PADVANCED,If set to 1 Advanced mode is enabled for the Secure World. If set to 0 Legacy mode is enabled for the Secure World." "0,1" bitfld.long 0x0 6. "PCONT_SWT,Finish all pending data and context DMA input requests [but will not assert any new requests] finish processing all data in the module and provide a saved context [partial hash result updated digest count remaining length updated mode.." "0,1" bitfld.long 0x0 3. "PDMA_EN,Enable dma Read 0 Interrupt disenabled Read 1 Interrupt enabled" "0,1" bitfld.long 0x0 2. "PIT_EN,Enable interrupt Read 0 Interrupt disenabled Read 1 Interrupt enabled" "0,1" line.long 0x4 "HSM_SHA_S_SYSSTATUS,Register SHA_SYSSTATUS." bitfld.long 0x4 0. "RESETDONE,data" "0,1" rgroup.long 0x118++0x3 line.long 0x0 "HSM_SHA_S_IRQSTATUS,Register SHA_IRQSTATUS." bitfld.long 0x0 3. "CONTEXT_READY,Indicates that the secure side context input registers are available for a new context for the next packet to be processed." "0,1" bitfld.long 0x0 2. "PARTHASH_READY,After a secure side context switch request this bit will read as 1 indicating that the saved context is available from the secure side context output registers. Note that if the context switch request coincides with a final hash [when.." "0,1" bitfld.long 0x0 1. "INPUT_READY,Indicates that the secure side data FIFO is ready to receive the next 64 byte data block." "0,1" bitfld.long 0x0 0. "OUTPUT_READY,Indicates that a [partial] result or saved context is available from the secure side context output registers." "0,1" group.long 0x11C++0x3 line.long 0x0 "HSM_SHA_S_IRQENABLE,Register SHA_IRQENABLE. The SHA_P_IRQENABLE register contains an enable bit for each unique interrupt for the public side. An interrupt is enabled when both the global enable in SHA_P_SYSCONFIG (PIT_en) and the bit in this register.." bitfld.long 0x0 3. "M_CONTEXT_READY,mask for context ready" "0,1" bitfld.long 0x0 2. "M_PARTHASH_READY,mask for partial hash" "0,1" bitfld.long 0x0 1. "M_INPUT_READY,mask for input_ready" "0,1" bitfld.long 0x0 0. "M_OUTPUT_READY,mask for output_ready" "0,1" group.long 0x140++0x7 line.long 0x0 "HSM_SHA_S_XSSTATUS,Secure/Private world Register read/write status." bitfld.long 0x0 3. "PDIRTY,This bit is set to 1 by the module if any of the Public World registers is written. It can be cleared by the host by Writing a 1 in this location." "0,1" bitfld.long 0x0 2. "PACCESSED,This bit is set to 1 by the module if any of the Public World registers is read. It can be cleared by the host by Writing a 1 in this location" "0,1" bitfld.long 0x0 1. "SDIRTY,This bit is set to 1 by the module if any of the Secure World registers is written. It can be cleared by the host by Writing a 1 in this location." "0,1" bitfld.long 0x0 0. "SACCESSED,This bit is set to 1 by the module if any of the Secure World registers is read. It can be cleared by the host by Writing a 1 in this location." "0,1" line.long 0x4 "HSM_SHA_S_LOCKDOWN,Use this Register to lock the algorithm preventing further use." rbitfld.long 0x4 29.--31. "RESERVED2,These bits should be written with zeroes and ignored on reads." "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "BLOCK_ODIGEST_RD,This makes the P_HASH_ODIGEST_A through P_HASH_ODIGEST_H write-only further protecting the HMAC key from being read by Public World software. Note: setting this bit also makes HMAC continue operations impossible!" "0,1" bitfld.long 0x4 27. "LOCK_LENGTH,When this bit is set the P_HASH_LENGTH register cannot be overwritten. This prevents Public World software from truncating or extending the block to be hashed or starting hash/HMAC operations by itself." "0,1" bitfld.long 0x4 26. "LOCK_DIGESTCOUNT,When this bit is set the P_HASH_DIGEST_COUNT register cannot be overwritten. This in combination with bits 3 and 24 prevents the Public World software from adding data at the front of the block to be hashed." "0,1" newline bitfld.long 0x4 25. "LOCK_ODIGEST,When this bit is set the P_HASH_ODIGEST_A through P_HASH_ODIGEST_H registers cannot be overwritten. This prevents Public World software from loading a weak and/or known HMAC key or an outer digest value." "0,1" bitfld.long 0x4 24. "LOCK_IDIGEST,When this bit is set the P_HASH_IDIGEST_A through P_HASH_IDIGEST_H registers cannot be overwritten. This prevents Public World software from loading a weak and/or known key or an initial digest value" "0,1" bitfld.long 0x4 7. "LOCK_HMAC_OUTER_HASH,When this bit is set HMAC Outer Hash bit in P_HASH_MODE cannot be modified.This prevents Public World software from bypassing the HMAC closure by clearing the corresponding mode bit during processing." "0,1" bitfld.long 0x4 6. "LOCK_REUSE_HMAC_KEY,When this bit is set the Reuse HMAC Key bit in P_HASH_MODE cannot be modified" "0,1" newline bitfld.long 0x4 5. "LOCK_HMAC_KEY,When this bit is set the HMAC Key Preprocessing bit in P_HASH_MODE cannot be modified. This prevents Public World software from bypassing the HMAC key preprocessing step and using the key data directly" "0,1" bitfld.long 0x4 4. "LOCK_CLOSE_HASH,When this bit is set the Close Hash bit in P_HASH_MODE cannot be modified.This prevents Public World software from bypassing the hash closure by clearing the corresponding mode bit during processing." "0,1" bitfld.long 0x4 3. "LOCK_USE_ALOG_CONST,When this bit is set the Use Alg Constants bit in P_HASH_MODE cannot be modified. This e.g. prevents Public World software from switching to [known!] algorithm constants instead of the [secret key based?] loaded & locked initial.." "0,1" bitfld.long 0x4 0.--2. "LOCK_ALGO,When either lock bit is set the corresponding Algorithm bit in P_HASH_MODE cannot be modified. This locks the algorithm preventing further use." "0,1,2,3,4,5,6,7" group.long 0x200++0x8B line.long 0x0 "HSM_SHA_S_HASH512_ODIGEST_A,Public World Outer SHA-512 Digest ." hexmask.long 0x0 0.--31. 1. "ODIGEST_A,W: Outer Digest [511:480] for SHA-384 and SHA-512 / SHA512_HMAC Key [31:0] for HMAC key procR: Outer Digest [511:480] for SHA-384 and SHA-512" line.long 0x4 "HSM_SHA_S_HASH512_ODIGEST_B,Public World Outer SHA-512 Digest ." hexmask.long 0x4 0.--31. 1. "ODIGEST_B,W: Outer Digest [479:448] for SHA-384 and SHA-512 / SHA512_HMAC Key [63:32] for HMAC key procR: Outer Digest [479:448] for SHA-384 and SHA-512" line.long 0x8 "HSM_SHA_S_HASH512_ODIGEST_C,Public World Outer SHA-512 Digest ." hexmask.long 0x8 0.--31. 1. "ODIGEST_C,W: Outer Digest [447:416] for SHA-384 and SHA-512 / SHA512_HMAC Key [95:64] for HMAC key procR: Outer Digest [447:416] for SHA-384 and SHA-512" line.long 0xC "HSM_SHA_S_HASH512_ODIGEST_D,Public World Outer SHA-512 Digest ." hexmask.long 0xC 0.--31. 1. "ODIGEST_D,W: Outer Digest [415:384] for SHA-384 and SHA-512 / SHA512_HMAC Key [127:96] for HMAC key procR: Outer Digest [415:384] for SHA-384 and SHA-512" line.long 0x10 "HSM_SHA_S_HASH512_ODIGEST_E,Public World Outer SHA-512 Digest ." hexmask.long 0x10 0.--31. 1. "ODIGEST_E,W: Outer Digest [383:352] for SHA-384 and SHA-512 / SHA512_HMAC Key [159:128] for HMAC key procR: Outer Digest [383:352] for SHA-384 and SHA-512" line.long 0x14 "HSM_SHA_S_HASH512_ODIGEST_F,Public World Outer SHA-512 Digest ." hexmask.long 0x14 0.--31. 1. "ODIGEST_F,W: Outer Digest [351:320] for SHA-384 and SHA-512 / SHA512_HMAC Key [191:160] for HMAC key procR: Outer Digest [351:320] for SHA-384 and SHA-512" line.long 0x18 "HSM_SHA_S_HASH512_ODIGEST_G,Public World Outer SHA-512 Digest ." hexmask.long 0x18 0.--31. 1. "ODIGEST_G,W: Outer Digest [319:288] for SHA-384 and SHA-512 / SHA512_HMAC Key [223:192] for HMAC key procR: Outer Digest [319:288] for SHA-384 and SHA-512" line.long 0x1C "HSM_SHA_S_HASH512_ODIGEST_H,Public World Outer SHA-512 Digest ." hexmask.long 0x1C 0.--31. 1. "ODIGEST_H,W: Outer Digest [287:256] for SHA-384 and SHA-512 / SHA512_HMAC Key [255:244] for HMAC key procR: Outer Digest [287:256] for SHA-384 and SHA-512" line.long 0x20 "HSM_SHA_S_HASH512_ODIGEST_I,Public World Outer SHA-512 Digest ." hexmask.long 0x20 0.--31. 1. "ODIGEST_I,W: Outer Digest [255:224] for SHA-384 and SHA-512 / SHA512_HMAC Key [287:256] for HMAC key procR: Outer Digest [255:224] for SHA-384 and SHA-512" line.long 0x24 "HSM_SHA_S_HASH512_ODIGEST_J,Public World Outer SHA-512 Digest ." hexmask.long 0x24 0.--31. 1. "ODIGEST_J,W: Outer Digest [223:192] for SHA-384 and SHA-512 / SHA512_HMAC Key [319:288] for HMAC key procR: Outer Digest [223:129] for SHA-384 and SHA-512" line.long 0x28 "HSM_SHA_S_HASH512_ODIGEST_K,Public World Outer SHA-512 Digest ." hexmask.long 0x28 0.--31. 1. "ODIGEST_K,W: Outer Digest [191:160] for SHA-384 and SHA-512 / SHA512_HMAC Key [351:320] for HMAC key procR: Outer Digest [191:160] for SHA-384 and SHA-512" line.long 0x2C "HSM_SHA_S_HASH512_ODIGEST_L,Public World Outer SHA-512 Digest ." hexmask.long 0x2C 0.--31. 1. "ODIGEST_L,W: Outer Digest [159:128] for SHA-384 and SHA-512 / SHA512_HMAC Key [383:352] for HMAC key procR: Outer Digest [159:128] for SHA-384 and SHA-512" line.long 0x30 "HSM_SHA_S_HASH512_ODIGEST_M,Public World Outer SHA-512 Digest ." hexmask.long 0x30 0.--31. 1. "ODIGEST_M,W: Outer Digest [128:96] for SHA-384 and SHA-512 / SHA512_HMAC Key [415:384] for HMAC key procR: Outer Digest [128:96] for SHA-384 and SHA-512" line.long 0x34 "HSM_SHA_S_HASH512_ODIGEST_N,Public World Outer SHA-512 Digest ." hexmask.long 0x34 0.--31. 1. "ODIGEST_N,W: Outer Digest [95:64] for SHA-384 and SHA-512 / SHA512_HMAC Key [447:416] for HMAC key procR: Outer Digest [95:64] for SHA-384 and SHA-512" line.long 0x38 "HSM_SHA_S_HASH512_ODIGEST_O,Public World Outer SHA-512 Digest ." hexmask.long 0x38 0.--31. 1. "ODIGEST_O,W: Outer Digest [63:32] for SHA-384 and SHA-512 / SHA512_HMAC Key [479:448] for HMAC key procR: Outer Digest [63:32] for SHA-384 and SHA-512" line.long 0x3C "HSM_SHA_S_HASH512_ODIGEST_P,Public World Outer SHA-512 Digest ." hexmask.long 0x3C 0.--31. 1. "ODIGEST_P,W: Outer Digest [31:0] for SHA-384 and SHA-512 / SHA512_HMAC Key [511:480] for HMAC key procR: Outer Digest [31:0] for SHA-384 and SHA-512" line.long 0x40 "HSM_SHA_S_HASH512_IDIGEST_A,Public World Inner SHA-512 Digest ." hexmask.long 0x40 0.--31. 1. "IDIGEST_A,W: Inner / Initial Digest [383:352] for SHA-384 and [511:480] for SHA-512 / SHA512_HMAC Key [543:512] for HMAC key procR: Intermediate / Inner Digest Digest [383:352] for SHA-384 and [511:480] for SHA-512Result Digest/MAC Digest [383:352] for.." line.long 0x44 "HSM_SHA_S_HASH512_IDIGEST_B,Public World Inner SHA-512 Digest ." hexmask.long 0x44 0.--31. 1. "IDIGEST_B,W: Inner / Initial Digest [531:320] for SHA-384 and [479:448] for SHA-512 / SHA512_HMAC Key [543:512] for HMAC key procR: Intermediate / Inner Digest Digest Digest [531:320] for SHA-384 and [479:448] for SHA-512Result Digest/MAC Digest Digest.." line.long 0x48 "HSM_SHA_S_HASH512_IDIGEST_C,Public World Inner SHA-512 Digest ." hexmask.long 0x48 0.--31. 1. "IDIGEST_C,W: Inner / Initial Digest [319:288] for SHA-384 and [416:447] for SHA-512 / SHA512_HMAC Key [543:512] for HMAC key procR: Intermediate / Inner Digest Digest Digest [319:288] for SHA-384 and [416:447] for SHA-512Result Digest/MAC Digest Digest.." line.long 0x4C "HSM_SHA_S_HASH512_IDIGEST_D,Public World Inner SHA-512 Digest ." hexmask.long 0x4C 0.--31. 1. "IDIGEST_D,W: Inner / Initial Digest [287:256] for SHA-384 and [415:384] for SHA-512 / SHA512_HMAC Key [639:608] for HMAC key procR: Intermediate / Inner Digest [287:256] for SHA-384 and [415:384] for SHA-512Result Digest/MAC Digest Digest [287:256] for.." line.long 0x50 "HSM_SHA_S_HASH512_IDIGEST_E,Public World Inner SHA-512 Digest ." hexmask.long 0x50 0.--31. 1. "IDIGEST_E,W: Inner / Initial Digest [255:224] for SHA-384 and [383:362] for SHA-512 / SHA512_HMAC Key [671:640] for HMAC key procR: Intermediate / Inner Digest [255:224] for SHA-384 and [383:362] for SHA-512Result Digest/MAC Digest Digest [255:224] for.." line.long 0x54 "HSM_SHA_S_HASH512_IDIGEST_F,Public World Inner SHA-512 Digest ." hexmask.long 0x54 0.--31. 1. "IDIGEST_F,W: Inner / Initial Digest [223:192] for SHA-384 and [351:320] for SHA-512 / SHA512_HMAC Key [703:672] for HMAC key procR: Intermediate / Inner Digest [223:192] for SHA-384 and [351:320] for SHA-512Result Digest/MAC Digest Digest [223:192] for.." line.long 0x58 "HSM_SHA_S_HASH512_IDIGEST_G,Public World Inner SHA-512 Digest ." hexmask.long 0x58 0.--31. 1. "IDIGEST_G,W: Inner / Initial Digest [191:160] for SHA-384 and [319:288] for SHA-512 / SHA512_HMAC Key [735:704] for HMAC key procR: Intermediate / Inner Digest [191:160] for SHA-384 and [319:288] for SHA-512Result Digest/MAC Digest Digest [191:160] for.." line.long 0x5C "HSM_SHA_S_HASH512_IDIGEST_H,Public World Inner SHA-512 Digest ." hexmask.long 0x5C 0.--31. 1. "IDIGEST_H,W: Inner / Initial Digest [159:128] for SHA-384 and [287:256] for SHA-512 / SHA512_HMAC Key [767:736] for HMAC key procR: Intermediate / Inner Digest [159:128] for SHA-384 and [287:256] for SHA-512Result Digest/MAC Digest Digest [159:128] for.." line.long 0x60 "HSM_SHA_S_HASH512_IDIGEST_I,Public World Inner SHA-512 Digest ." hexmask.long 0x60 0.--31. 1. "IDIGEST_I,W: Inner / Initial Digest [127:96] for SHA-384 and [255:224] for SHA-512 / SHA512_HMAC Key [799:768] for HMAC key procR: Intermediate / Inner Digest [127:96] for SHA-384 and [255:224] for SHA-512Result Digest/MAC Digest Digest [127:96] for.." line.long 0x64 "HSM_SHA_S_HASH512_IDIGEST_J,Public World Inner SHA-512 Digest ." hexmask.long 0x64 0.--31. 1. "IDIGEST_J,W: Inner / Initial Digest [95:64] for SHA-384 and [223:192] for SHA-512 / SHA512_HMAC Key [831:800] for HMAC key procR: Intermediate / Inner Digest [95:64] for SHA-384 and [223:192] for SHA-512Result Digest/MAC Digest Digest [95:64] for SHA-384.." line.long 0x68 "HSM_SHA_S_HASH512_IDIGEST_K,Public World Inner SHA-512 Digest ." hexmask.long 0x68 0.--31. 1. "IDIGEST_K,W: Inner / Initial Digest [63:32] for SHA-384 and [191:160] for SHA-512 / SHA512_HMAC Key [863:832] for HMAC key procR: Intermediate / Inner Digest [63:32] for SHA-384 and [191:160] for SHA-512Result Digest/MAC Digest Digest [63:32] for SHA-384.." line.long 0x6C "HSM_SHA_S_HASH512_IDIGEST_L,Public World Inner SHA-512 Digest ." hexmask.long 0x6C 0.--31. 1. "IDIGEST_L,W: Inner / Initial Digest [31:0] for SHA-384 and [159:128] for SHA-512 / SHA512_HMAC Key [895:864] for HMAC key procR: Intermediate / Inner Digest [31:0] for SHA-384 and [159:128] for SHA-512Result Digest/MAC Digest Digest [31:0] for SHA-384.." line.long 0x70 "HSM_SHA_S_HASH512_IDIGEST_M,Public World Inner SHA-512 Digest ." hexmask.long 0x70 0.--31. 1. "IDIGEST_M,W: Inner / Initial Digest [127:96] for SHA-512 / SHA512_HMAC Key [927:896] for HMAC key procR: Intermediate / Inner Digest [127:96] for SHA-512Result Digest/MAC Digest Digest [127:96] for SHA-512" line.long 0x74 "HSM_SHA_S_HASH512_IDIGEST_N,Public World Inner SHA-512 Digest ." hexmask.long 0x74 0.--31. 1. "IDIGEST_N,W: Inner / Initial Digest [95:64] for SHA-512 / SHA512_HMAC Key [959:928] for HMAC key procR: Intermediate / Inner Digest [95:64] for SHA-512Result Digest/MAC Digest Digest [95:64] for SHA-512" line.long 0x78 "HSM_SHA_S_HASH512_IDIGEST_O,Public World Inner SHA-512 Digest ." hexmask.long 0x78 0.--31. 1. "IDIGEST_O,W: Inner / Initial Digest [63:32] for SHA-512 / SHA512_HMAC Key [991:960] for HMAC key procR: Intermediate / Inner Digest [63:32] for SHA-512Result Digest/MAC Digest Digest [63:32] for SHA-512" line.long 0x7C "HSM_SHA_S_HASH512_IDIGEST_P,Public World Inner SHA-512 Digest ." hexmask.long 0x7C 0.--31. 1. "IDIGEST_P,W: Inner / Initial Digest [31:0] for SHA-512 / SHA512_HMAC Key 1023992] for HMAC key procR: Intermediate / Inner Digest [31:0] for SHA-512Result Digest/MAC Digest Digest [31:0] for SHA-512" line.long 0x80 "HSM_SHA_S_HASH512_DIGEST_COUNT,Public World SHA-512 Digest Count ." hexmask.long 0x80 0.--31. 1. "DIGEST_COUNT,W: Initial Digest Count [[31:7] only [6:0] assumed 0]R: Result / IntermediateDigest Count" line.long 0x84 "HSM_SHA_S_HASH512_MODE,Public World SHA-512 Hash Mode." hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,These bits should be written with zeroes and ignored on reads." bitfld.long 0x84 7. "HMAC_OUTER_HASH,If set to 1 the HMAC Outer Hash is performed on the hash digest when the inner hash hash finished [block length exhausted and final hash performed if Close Hash is 1].This bit should normally be set together with Close Hash to finish the.." "0,1" bitfld.long 0x84 6. "REUSE_HMAC_KEY,If set to 1 an HMAC operation is started using the HMAC key that was loaded at the time HMAC Key Processing was last performed provided that the P_HASH512_ODIGEST registers have not been overwritten since. This makes it possible to.." "0,1" bitfld.long 0x84 5. "HMAC_KEY_PROCESSING,If set to 1 the hash core will perform HMAC key processing on the HMAC key [with block size length] loaded into the P_HASH512_IDIGEST:P_HASH512_ODIGEST register block. Once HMAC key processing is finished this bit is automatically.." "0,1" newline bitfld.long 0x84 4. "CLOSE_HASH,If set to 1 then the hash/HMAC will be 'closed' at the end of the block as per MD5/SHA-1/SHA-2 specification [i.e. appropriate padding is added]. If set to 0 then the hash/HMAC will not be closed and can be continued later. However if the.." "0,1" bitfld.long 0x84 3. "USE_ALG_CONSTANTS,If set to 1 the initial digest register will be overwritten with the algorithm constants for the selected algorithm when hashing and the initial digest count register will be reset to 0. This will start a normal hash operation. When.." "0,1" bitfld.long 0x84 0.--2. "ALGORITHM,These bits select the hash algorithm to be used for processing:000 - MD5010 - SHA-1100 - SHA-224110 - SHA-256001 - SHA-384011 - SHA-512" "0,1,2,3,4,5,6,7" line.long 0x88 "HSM_SHA_S_HASH512_LENGTH,Public World SHA-512 Block Length ." hexmask.long 0x88 0.--31. 1. "LENGTH,W: Block Length / Remaining Byte Count [bytes]R: Remaining Byte Count" group.long 0x1000++0x4B line.long 0x0 "HSM_SHA_P_ODIGEST_A,WRITE: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [31:0] for HMAC key proc READ: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2" hexmask.long 0x0 0.--31. 1. "DATA,data" line.long 0x4 "HSM_SHA_P_ODIGEST_B,WRITE: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [63:32] for HMAC key proc READ: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2" hexmask.long 0x4 0.--31. 1. "DATA,data" line.long 0x8 "HSM_SHA_P_ODIGEST_C,WRITE: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / HMAC Key [95:64] for HMAC key proc READ: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2" hexmask.long 0x8 0.--31. 1. "DATA,data" line.long 0xC "HSM_SHA_P_ODIGEST_D,WRITE: Outer Digest [31:0] for MD5 [63:31] for SHA-1 [159:128] for SHA-2 / HMAC Key [127:96] for HMAC key proc READ: Outer Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2" hexmask.long 0xC 0.--31. 1. "DATA,data" line.long 0x10 "HSM_SHA_P_ODIGEST_E,WRITE: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [159:128] for HMAC key proc READ: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2" hexmask.long 0x10 0.--31. 1. "DATA,data" line.long 0x14 "HSM_SHA_P_ODIGEST_F,WRITE: Outer Digest [95:64] for SHA-2 / HMAC Key [191:160] for HMAC key proc READ: Outer Digest [95:64] for SHA-2" hexmask.long 0x14 0.--31. 1. "DATA,data" line.long 0x18 "HSM_SHA_P_ODIGEST_G,WRITE: Outer Digest [63:32] for SHA-2 / HMAC Key [223:192] for HMAC key proc READ: Outer Digest [63:32] for SHA-2" hexmask.long 0x18 0.--31. 1. "DATA,data" line.long 0x1C "HSM_SHA_P_ODIGEST_H,WRITE: Outer Digest [31:0] for SHA-2 / HMAC Key [255:224] for HMAC key proc READ: Outer Digest [31:0] for SHA-2" hexmask.long 0x1C 0.--31. 1. "DATA,data" line.long 0x20 "HSM_SHA_P_IDIGEST_A,WRITE: Inner / Initial Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [287:256] for HMAC key proc READ: Intermediate / Inner Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / Result.." hexmask.long 0x20 0.--31. 1. "DATA,data" line.long 0x24 "HSM_SHA_P_IDIGEST_B,WRITE: Inner / Initial Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [319:288] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / Result Digest/MAC.." hexmask.long 0x24 0.--31. 1. "DATA,data" line.long 0x28 "HSM_SHA_P_IDIGEST_C,WRITE: Inner / Initial Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA- 2 / HMAC Key [351:320] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / Result Digest/MAC.." hexmask.long 0x28 0.--31. 1. "DATA,data" line.long 0x2C "HSM_SHA_P_IDIGEST_D,WRITE: Inner / Initial Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / HMAC Key [383:352] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / Result Digest/MAC.." hexmask.long 0x2C 0.--31. 1. "DATA,data" line.long 0x30 "HSM_SHA_P_IDIGEST_E,WRITE: Inner / Initial Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [415:384] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-1 [127:96] for SHA-2 / Result Digest/MAC [31:0] for SHA-1 [95:64] for SHA-2 224.." hexmask.long 0x30 0.--31. 1. "DATA,data" line.long 0x34 "HSM_SHA_P_IDIGEST_F,WRITE: Inner / Initial Digest [95:64] for SHA-2 / HMAC Key [447:416] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for SHA-2 / Result Digest/MAC [63:32] for SHA-2 224 [95:64] for SHA-2 256." hexmask.long 0x34 0.--31. 1. "DATA,data" line.long 0x38 "HSM_SHA_P_IDIGEST_G,WRITE: Inner / Initial Digest [63:32] for SHA-2 / HMAC Key [479:448] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 224 [63:32] for SHA-2 256." hexmask.long 0x38 0.--31. 1. "DATA,data" line.long 0x3C "HSM_SHA_P_IDIGEST_H,WRITE: Inner / Initial Digest [31:0] for SHA-2 / HMAC Key [511:480] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 256." hexmask.long 0x3C 0.--31. 1. "DATA,data" line.long 0x40 "HSM_SHA_P_DIGEST_COUNT,WRITE: Initial Digest Count ([31:6] only [5:0] assumed 0) READ: Result / IntermediateDigest Count The initial digest byte count for hash/HMAC continue operations (HMAC Key Processing = 0 and Use Algorithm Constants = 0) on the.." hexmask.long 0x40 0.--31. 1. "DATA,data" line.long 0x44 "HSM_SHA_P_MODE,Register SHA_MODE." bitfld.long 0x44 7. "HMAC_OUTER_HASH,The HMAC Outer Hash is performed on the hash digest when the inner hash hash finished [block length exhausted and final hash performed if close_hash is 1]. This bit should normally be set together with close_hash to finish the inner hash.." "0,1" bitfld.long 0x44 5. "HMAC_KEY_PROC,Performs HMAC key processing on the 512 bit HMAC key loaded into the SHA_P_IDIGEST_{A to H} and SHA_P_ODIGEST_{A to H} register block. Once HMAC key processing is finished this bit is automatically cleared and the resulting Inner and Outer.." "0,1" bitfld.long 0x44 4. "CLOSE_HASH,Performs the padding the hash/HMAC will be 'closed' at the end of the block as per MD5/SHA-1/SHA-2 specification [i.e. appropriate padding is added] or no padding is done allowing the hash to be continued later. However if the hash/HMAC is not.." "0,1" bitfld.long 0x44 3. "ALGO_CONSTANT,The initial digest register will be overwritten with the algorithm constants for the selected algorithm when hashing and the initial digest count register will be reset to 0. This will start a normal hash operation. When continuing an.." "0,1" newline bitfld.long 0x44 1.--2. "ALGO,These bits select the hash algorithm to be used for processing: 0 md5_128 algorithm 0x1 sha1_160 algorithm 0x2 sha2_224 algorithm 0x3 sha2_256 algorithm" "0,1,2,3" line.long 0x48 "HSM_SHA_P_LENGTH,WRITE: Block Length / Remaining Byte Count (bytes) READ: Remaining Byte Count. The value programmed MUST be a 64-byte multiple if Close Hash is set to 0. This register is also the trigger to start processing: once this register is.." hexmask.long 0x48 0.--31. 1. "DATA,data" wgroup.long 0x1080++0x3F line.long 0x0 "HSM_SHA_P_DATA0_IN,Data input message 0" hexmask.long 0x0 0.--31. 1. "DATA0_IN,data" line.long 0x4 "HSM_SHA_P_DATA1_IN,Data input message 1" hexmask.long 0x4 0.--31. 1. "DATA1_IN,data" line.long 0x8 "HSM_SHA_P_DATA2_IN,Data input message 2" hexmask.long 0x8 0.--31. 1. "DATA2_IN,data" line.long 0xC "HSM_SHA_P_DATA3_IN,Data input message 3" hexmask.long 0xC 0.--31. 1. "DATA3_IN,data" line.long 0x10 "HSM_SHA_P_DATA4_IN,Data input message 4" hexmask.long 0x10 0.--31. 1. "DATA4_IN,data" line.long 0x14 "HSM_SHA_P_DATA5_IN,Data input message 5" hexmask.long 0x14 0.--31. 1. "DATA5_IN,data" line.long 0x18 "HSM_SHA_P_DATA6_IN,Data input message 6" hexmask.long 0x18 0.--31. 1. "DATA6_IN,data" line.long 0x1C "HSM_SHA_P_DATA7_IN,Data input message 7" hexmask.long 0x1C 0.--31. 1. "DATA7_IN,data" line.long 0x20 "HSM_SHA_P_DATA8_IN,Data input message 8" hexmask.long 0x20 0.--31. 1. "DATA8_IN,data" line.long 0x24 "HSM_SHA_P_DATA9_IN,Data input message 9" hexmask.long 0x24 0.--31. 1. "DATA9_IN,data" line.long 0x28 "HSM_SHA_P_DATA10_IN,Data input message 10." hexmask.long 0x28 0.--31. 1. "DATA10_IN,data" line.long 0x2C "HSM_SHA_P_DATA11_IN,Data input message 11." hexmask.long 0x2C 0.--31. 1. "DATA11_IN,data" line.long 0x30 "HSM_SHA_P_DATA12_IN,Data input message 12." hexmask.long 0x30 0.--31. 1. "DATA12_IN,data" line.long 0x34 "HSM_SHA_P_DATA13_IN,Data input message 13." hexmask.long 0x34 0.--31. 1. "DATA13_IN,data" line.long 0x38 "HSM_SHA_P_DATA14_IN,Data input message 14." hexmask.long 0x38 0.--31. 1. "DATA14_IN,data" line.long 0x3C "HSM_SHA_P_DATA15_IN,Data input message 15." hexmask.long 0x3C 0.--31. 1. "DATA15_IN,data" rgroup.long 0x1100++0x3 line.long 0x0 "HSM_SHA_P_REVISION,Register SHA_REV." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current. Read 0 Legacy ASP or WTBU scheme Read 0x1 Highlander 0.8 scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned." hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner. RTL follows a numbering such as X.Y.R.Z which are explained in this table. R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner. X changes ONLY when: [1] There is a major feature addition. An example would be adding Master Mode to Utopia Level2. The Func field [or Class/Type in old PID format] will remain the same. X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers. Read 0 Non custom [standard] revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner. Y changes ONLY when: [1] Features are scaled [up or down]. Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP.." group.long 0x1110++0x7 line.long 0x0 "HSM_SHA_P_SYSCONFIG,Register SHA_SYSCONFIG." bitfld.long 0x0 7. "PADVANCED,If set to 1 Advanced mode is enabled for the Secure World. If set to 0 Legacy mode is enabled for the Secure World." "0,1" bitfld.long 0x0 6. "PCONT_SWT,Finish all pending data and context DMA input requests [but will not assert any new requests] finish processing all data in the module and provide a saved context [partial hash result updated digest count remaining length updated mode.." "0,1" bitfld.long 0x0 3. "PDMA_EN,Enable dma Read 0 Interrupt disenabled Read 1 Interrupt enabled" "0,1" bitfld.long 0x0 2. "PIT_EN,Enable interrupt Read 0 Interrupt disenabled Read 1 Interrupt enabled" "0,1" line.long 0x4 "HSM_SHA_P_SYSSTATUS,Register SHA_SYSSTATUS." bitfld.long 0x4 0. "RESETDONE,data" "0,1" rgroup.long 0x1118++0x3 line.long 0x0 "HSM_SHA_P_IRQSTATUS,Register SHA_IRQSTATUS." bitfld.long 0x0 3. "CONTEXT_READY,Indicates that the secure side context input registers are available for a new context for the next packet to be processed." "0,1" bitfld.long 0x0 2. "PARTHASH_READY,After a secure side context switch request this bit will read as 1 indicating that the saved context is available from the secure side context output registers. Note that if the context switch request coincides with a final hash [when.." "0,1" bitfld.long 0x0 1. "INPUT_READY,Indicates that the secure side data FIFO is ready to receive the next 64 byte data block." "0,1" bitfld.long 0x0 0. "OUTPUT_READY,Indicates that a [partial] result or saved context is available from the secure side context output registers." "0,1" group.long 0x111C++0x3 line.long 0x0 "HSM_SHA_P_IRQENABLE,Register SHA_IRQENABLE. The SHA_P_IRQENABLE register contains an enable bit for each unique interrupt for the public side. An interrupt is enabled when both the global enable in SHA_P_SYSCONFIG (PIT_en) and the bit in this register.." bitfld.long 0x0 3. "M_CONTEXT_READY,mask for context ready" "0,1" bitfld.long 0x0 2. "M_PARTHASH_READY,mask for partial hash" "0,1" bitfld.long 0x0 1. "M_INPUT_READY,mask for input_ready" "0,1" bitfld.long 0x0 0. "M_OUTPUT_READY,mask for output_ready" "0,1" group.long 0x1200++0x8B line.long 0x0 "HSM_SHA_P_HASH512_ODIGEST_A,Public World Outer SHA-512 Digest ." hexmask.long 0x0 0.--31. 1. "ODIGEST_A,W: Outer Digest [511:480] for SHA-384 and SHA-512 / SHA512_HMAC Key [31:0] for HMAC key procR: Outer Digest [511:480] for SHA-384 and SHA-512" line.long 0x4 "HSM_SHA_P_HASH512_ODIGEST_B,Public World Outer SHA-512 Digest ." hexmask.long 0x4 0.--31. 1. "ODIGEST_B,W: Outer Digest [479:448] for SHA-384 and SHA-512 / SHA512_HMAC Key [63:32] for HMAC key procR: Outer Digest [479:448] for SHA-384 and SHA-512" line.long 0x8 "HSM_SHA_P_HASH512_ODIGEST_C,Public World Outer SHA-512 Digest ." hexmask.long 0x8 0.--31. 1. "ODIGEST_C,W: Outer Digest [447:416] for SHA-384 and SHA-512 / SHA512_HMAC Key [95:64] for HMAC key procR: Outer Digest [447:416] for SHA-384 and SHA-512" line.long 0xC "HSM_SHA_P_HASH512_ODIGEST_D,Public World Outer SHA-512 Digest ." hexmask.long 0xC 0.--31. 1. "ODIGEST_D,W: Outer Digest [415:384] for SHA-384 and SHA-512 / SHA512_HMAC Key [127:96] for HMAC key procR: Outer Digest [415:384] for SHA-384 and SHA-512" line.long 0x10 "HSM_SHA_P_HASH512_ODIGEST_E,Public World Outer SHA-512 Digest ." hexmask.long 0x10 0.--31. 1. "ODIGEST_E,W: Outer Digest [383:352] for SHA-384 and SHA-512 / SHA512_HMAC Key [159:128] for HMAC key procR: Outer Digest [383:352] for SHA-384 and SHA-512" line.long 0x14 "HSM_SHA_P_HASH512_ODIGEST_F,Public World Outer SHA-512 Digest ." hexmask.long 0x14 0.--31. 1. "ODIGEST_F,W: Outer Digest [351:320] for SHA-384 and SHA-512 / SHA512_HMAC Key [191:160] for HMAC key procR: Outer Digest [351:320] for SHA-384 and SHA-512" line.long 0x18 "HSM_SHA_P_HASH512_ODIGEST_G,Public World Outer SHA-512 Digest ." hexmask.long 0x18 0.--31. 1. "ODIGEST_G,W: Outer Digest [319:288] for SHA-384 and SHA-512 / SHA512_HMAC Key [223:192] for HMAC key procR: Outer Digest [319:288] for SHA-384 and SHA-512" line.long 0x1C "HSM_SHA_P_HASH512_ODIGEST_H,Public World Outer SHA-512 Digest ." hexmask.long 0x1C 0.--31. 1. "ODIGEST_H,W: Outer Digest [287:256] for SHA-384 and SHA-512 / SHA512_HMAC Key [255:244] for HMAC key procR: Outer Digest [287:256] for SHA-384 and SHA-512" line.long 0x20 "HSM_SHA_P_HASH512_ODIGEST_I,Public World Outer SHA-512 Digest ." hexmask.long 0x20 0.--31. 1. "ODIGEST_I,W: Outer Digest [255:224] for SHA-384 and SHA-512 / SHA512_HMAC Key [287:256] for HMAC key procR: Outer Digest [255:224] for SHA-384 and SHA-512" line.long 0x24 "HSM_SHA_P_HASH512_ODIGEST_J,Public World Outer SHA-512 Digest ." hexmask.long 0x24 0.--31. 1. "ODIGEST_J,W: Outer Digest [223:192] for SHA-384 and SHA-512 / SHA512_HMAC Key [319:288] for HMAC key procR: Outer Digest [223:129] for SHA-384 and SHA-512" line.long 0x28 "HSM_SHA_P_HASH512_ODIGEST_K,Public World Outer SHA-512 Digest ." hexmask.long 0x28 0.--31. 1. "ODIGEST_K,W: Outer Digest [191:160] for SHA-384 and SHA-512 / SHA512_HMAC Key [351:320] for HMAC key procR: Outer Digest [191:160] for SHA-384 and SHA-512" line.long 0x2C "HSM_SHA_P_HASH512_ODIGEST_L,Public World Outer SHA-512 Digest ." hexmask.long 0x2C 0.--31. 1. "ODIGEST_L,W: Outer Digest [159:128] for SHA-384 and SHA-512 / SHA512_HMAC Key [383:352] for HMAC key procR: Outer Digest [159:128] for SHA-384 and SHA-512" line.long 0x30 "HSM_SHA_P_HASH512_ODIGEST_M,Public World Outer SHA-512 Digest ." hexmask.long 0x30 0.--31. 1. "ODIGEST_M,W: Outer Digest [128:96] for SHA-384 and SHA-512 / SHA512_HMAC Key [415:384] for HMAC key procR: Outer Digest [128:96] for SHA-384 and SHA-512" line.long 0x34 "HSM_SHA_P_HASH512_ODIGEST_N,Public World Outer SHA-512 Digest ." hexmask.long 0x34 0.--31. 1. "ODIGEST_N,W: Outer Digest [95:64] for SHA-384 and SHA-512 / SHA512_HMAC Key [447:416] for HMAC key procR: Outer Digest [95:64] for SHA-384 and SHA-512" line.long 0x38 "HSM_SHA_P_HASH512_ODIGEST_O,Public World Outer SHA-512 Digest ." hexmask.long 0x38 0.--31. 1. "ODIGEST_O,W: Outer Digest [63:32] for SHA-384 and SHA-512 / SHA512_HMAC Key [479:448] for HMAC key procR: Outer Digest [63:32] for SHA-384 and SHA-512" line.long 0x3C "HSM_SHA_P_HASH512_ODIGEST_P,Public World Outer SHA-512 Digest ." hexmask.long 0x3C 0.--31. 1. "ODIGEST_P,W: Outer Digest [31:0] for SHA-384 and SHA-512 / SHA512_HMAC Key [511:480] for HMAC key procR: Outer Digest [31:0] for SHA-384 and SHA-512" line.long 0x40 "HSM_SHA_P_HASH512_IDIGEST_A,Public World Inner SHA-512 Digest ." hexmask.long 0x40 0.--31. 1. "IDIGEST_A,W: Inner / Initial Digest [383:352] for SHA-384 and [511:480] for SHA-512 / SHA512_HMAC Key [543:512] for HMAC key procR: Intermediate / Inner Digest Digest [383:352] for SHA-384 and [511:480] for SHA-512Result Digest/MAC Digest [383:352] for.." line.long 0x44 "HSM_SHA_P_HASH512_IDIGEST_B,Public World Inner SHA-512 Digest ." hexmask.long 0x44 0.--31. 1. "IDIGEST_B,W: Inner / Initial Digest [531:320] for SHA-384 and [479:448] for SHA-512 / SHA512_HMAC Key [543:512] for HMAC key procR: Intermediate / Inner Digest Digest Digest [531:320] for SHA-384 and [479:448] for SHA-512Result Digest/MAC Digest Digest.." line.long 0x48 "HSM_SHA_P_HASH512_IDIGEST_C,Public World Inner SHA-512 Digest ." hexmask.long 0x48 0.--31. 1. "IDIGEST_C,W: Inner / Initial Digest [319:288] for SHA-384 and [416:447] for SHA-512 / SHA512_HMAC Key [543:512] for HMAC key procR: Intermediate / Inner Digest Digest Digest [319:288] for SHA-384 and [416:447] for SHA-512Result Digest/MAC Digest Digest.." line.long 0x4C "HSM_SHA_P_HASH512_IDIGEST_D,Public World Inner SHA-512 Digest ." hexmask.long 0x4C 0.--31. 1. "IDIGEST_D,W: Inner / Initial Digest [287:256] for SHA-384 and [415:384] for SHA-512 / SHA512_HMAC Key [639:608] for HMAC key procR: Intermediate / Inner Digest [287:256] for SHA-384 and [415:384] for SHA-512Result Digest/MAC Digest Digest [287:256] for.." line.long 0x50 "HSM_SHA_P_HASH512_IDIGEST_E,Public World Inner SHA-512 Digest ." hexmask.long 0x50 0.--31. 1. "IDIGEST_E,W: Inner / Initial Digest [255:224] for SHA-384 and [383:362] for SHA-512 / SHA512_HMAC Key [671:640] for HMAC key procR: Intermediate / Inner Digest [255:224] for SHA-384 and [383:362] for SHA-512Result Digest/MAC Digest Digest [255:224] for.." line.long 0x54 "HSM_SHA_P_HASH512_IDIGEST_F,Public World Inner SHA-512 Digest ." hexmask.long 0x54 0.--31. 1. "IDIGEST_F,W: Inner / Initial Digest [223:192] for SHA-384 and [351:320] for SHA-512 / SHA512_HMAC Key [703:672] for HMAC key procR: Intermediate / Inner Digest [223:192] for SHA-384 and [351:320] for SHA-512Result Digest/MAC Digest Digest [223:192] for.." line.long 0x58 "HSM_SHA_P_HASH512_IDIGEST_G,Public World Inner SHA-512 Digest ." hexmask.long 0x58 0.--31. 1. "IDIGEST_G,W: Inner / Initial Digest [191:160] for SHA-384 and [319:288] for SHA-512 / SHA512_HMAC Key [735:704] for HMAC key procR: Intermediate / Inner Digest [191:160] for SHA-384 and [319:288] for SHA-512Result Digest/MAC Digest Digest [191:160] for.." line.long 0x5C "HSM_SHA_P_HASH512_IDIGEST_H,Public World Inner SHA-512 Digest ." hexmask.long 0x5C 0.--31. 1. "IDIGEST_H,W: Inner / Initial Digest [159:128] for SHA-384 and [287:256] for SHA-512 / SHA512_HMAC Key [767:736] for HMAC key procR: Intermediate / Inner Digest [159:128] for SHA-384 and [287:256] for SHA-512Result Digest/MAC Digest Digest [159:128] for.." line.long 0x60 "HSM_SHA_P_HASH512_IDIGEST_I,Public World Inner SHA-512 Digest ." hexmask.long 0x60 0.--31. 1. "IDIGEST_I,W: Inner / Initial Digest [127:96] for SHA-384 and [255:224] for SHA-512 / SHA512_HMAC Key [799:768] for HMAC key procR: Intermediate / Inner Digest [127:96] for SHA-384 and [255:224] for SHA-512Result Digest/MAC Digest Digest [127:96] for.." line.long 0x64 "HSM_SHA_P_HASH512_IDIGEST_J,Public World Inner SHA-512 Digest ." hexmask.long 0x64 0.--31. 1. "IDIGEST_J,W: Inner / Initial Digest [95:64] for SHA-384 and [223:192] for SHA-512 / SHA512_HMAC Key [831:800] for HMAC key procR: Intermediate / Inner Digest [95:64] for SHA-384 and [223:192] for SHA-512Result Digest/MAC Digest Digest [95:64] for SHA-384.." line.long 0x68 "HSM_SHA_P_HASH512_IDIGEST_K,Public World Inner SHA-512 Digest ." hexmask.long 0x68 0.--31. 1. "IDIGEST_K,W: Inner / Initial Digest [63:32] for SHA-384 and [191:160] for SHA-512 / SHA512_HMAC Key [863:832] for HMAC key procR: Intermediate / Inner Digest [63:32] for SHA-384 and [191:160] for SHA-512Result Digest/MAC Digest Digest [63:32] for SHA-384.." line.long 0x6C "HSM_SHA_P_HASH512_IDIGEST_L,Public World Inner SHA-512 Digest ." hexmask.long 0x6C 0.--31. 1. "IDIGEST_L,W: Inner / Initial Digest [31:0] for SHA-384 and [159:128] for SHA-512 / SHA512_HMAC Key [895:864] for HMAC key procR: Intermediate / Inner Digest [31:0] for SHA-384 and [159:128] for SHA-512Result Digest/MAC Digest Digest [31:0] for SHA-384.." line.long 0x70 "HSM_SHA_P_HASH512_IDIGEST_M,Public World Inner SHA-512 Digest ." hexmask.long 0x70 0.--31. 1. "IDIGEST_M,W: Inner / Initial Digest [127:96] for SHA-512 / SHA512_HMAC Key [927:896] for HMAC key procR: Intermediate / Inner Digest [127:96] for SHA-512Result Digest/MAC Digest Digest [127:96] for SHA-512" line.long 0x74 "HSM_SHA_P_HASH512_IDIGEST_N,Public World Inner SHA-512 Digest ." hexmask.long 0x74 0.--31. 1. "IDIGEST_N,W: Inner / Initial Digest [95:64] for SHA-512 / SHA512_HMAC Key [959:928] for HMAC key procR: Intermediate / Inner Digest [95:64] for SHA-512Result Digest/MAC Digest Digest [95:64] for SHA-512" line.long 0x78 "HSM_SHA_P_HASH512_IDIGEST_O,Public World Inner SHA-512 Digest ." hexmask.long 0x78 0.--31. 1. "IDIGEST_O,W: Inner / Initial Digest [63:32] for SHA-512 / SHA512_HMAC Key [991:960] for HMAC key procR: Intermediate / Inner Digest [63:32] for SHA-512Result Digest/MAC Digest Digest [63:32] for SHA-512" line.long 0x7C "HSM_SHA_P_HASH512_IDIGEST_P,Public World Inner SHA-512 Digest ." hexmask.long 0x7C 0.--31. 1. "IDIGEST_P,W: Inner / Initial Digest [31:0] for SHA-512 / SHA512_HMAC Key 1023992] for HMAC key procR: Intermediate / Inner Digest [31:0] for SHA-512Result Digest/MAC Digest Digest [31:0] for SHA-512" line.long 0x80 "HSM_SHA_P_HASH512_DIGEST_COUNT,Public World SHA-512 Digest Count ." hexmask.long 0x80 0.--31. 1. "DIGEST_COUNT,W: Initial Digest Count [[31:7] only [6:0] assumed 0]R: Result / IntermediateDigest Count" line.long 0x84 "HSM_SHA_P_HASH512_MODE,Public World SHA-512 Hash Mode." hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,These bits should be written with zeroes and ignored on reads." bitfld.long 0x84 7. "HMAC_OUTER_HASH,If set to 1 the HMAC Outer Hash is performed on the hash digest when the inner hash hash finished [block length exhausted and final hash performed if Close Hash is 1].This bit should normally be set together with Close Hash to finish the.." "0,1" bitfld.long 0x84 6. "REUSE_HMAC_KEY,If set to 1 an HMAC operation is started using the HMAC key that was loaded at the time HMAC Key Processing was last performed provided that the P_HASH512_ODIGEST registers have not been overwritten since. This makes it possible to.." "0,1" bitfld.long 0x84 5. "HMAC_KEY_PROCESSING,If set to 1 the hash core will perform HMAC key processing on the HMAC key [with block size length] loaded into the P_HASH512_IDIGEST:P_HASH512_ODIGEST register block. Once HMAC key processing is finished this bit is automatically.." "0,1" newline bitfld.long 0x84 4. "CLOSE_HASH,If set to 1 then the hash/HMAC will be 'closed' at the end of the block as per MD5/SHA-1/SHA-2 specification [i.e. appropriate padding is added]. If set to 0 then the hash/HMAC will not be closed and can be continued later. However if the.." "0,1" bitfld.long 0x84 3. "USE_ALG_CONSTANTS,If set to 1 the initial digest register will be overwritten with the algorithm constants for the selected algorithm when hashing and the initial digest count register will be reset to 0. This will start a normal hash operation. When.." "0,1" bitfld.long 0x84 0.--2. "ALGORITHM,These bits select the hash algorithm to be used for processing:000 - MD5010 - SHA-1100 - SHA-224110 - SHA-256001 - SHA-384011 - SHA-512" "0,1,2,3,4,5,6,7" line.long 0x88 "HSM_SHA_P_HASH512_LENGTH,Public World SHA-512 Block Length ." hexmask.long 0x88 0.--31. 1. "LENGTH,W: Block Length / Remaining Byte Count [bytes]R: Remaining Byte Count" tree.end tree "HSM0_HSM_TRNG" base ad:0xCE00A000 group.long 0x0++0x3F line.long 0x0 "HSM_TRNG_TRNG_INPUT_0,These registers are used as input for [SP 800-90A] AES-256 DRBG testing. They share theiraddresses with the TRNG_OUTPUT_0 to TRNG_OUTPUT_3 registers." hexmask.long 0x0 0.--31. 1. "TRNG_INPUT,These registers are used as input for [SP 800-90A] AES-256 DRBG testing." line.long 0x4 "HSM_TRNG_TRNG_INPUT_1,These registers are used as input for [SP 800-90A] AES-256 DRBG testing. They share theiraddresses with the TRNG_OUTPUT_0 to TRNG_OUTPUT_3 registers." hexmask.long 0x4 0.--31. 1. "TRNG_INPUT,These registers are used as input for [SP 800-90A] AES-256 DRBG testing." line.long 0x8 "HSM_TRNG_TRNG_INPUT_2,These registers are used as input for [SP 800-90A] AES-256 DRBG testing. They share theiraddresses with the TRNG_OUTPUT_0 to TRNG_OUTPUT_3 registers." hexmask.long 0x8 0.--31. 1. "TRNG_INPUT,These registers are used as input for [SP 800-90A] AES-256 DRBG testing." line.long 0xC "HSM_TRNG_TRNG_INPUT_3,These registers are used as input for [SP 800-90A] AES-256 DRBG testing. They share theiraddresses with the TRNG_OUTPUT_0 to TRNG_OUTPUT_3 registers." hexmask.long 0xC 0.--31. 1. "TRNG_INPUT,These registers are used as input for [SP 800-90A] AES-256 DRBG testing." line.long 0x10 "HSM_TRNG_TRNG_STATUS,Status register." rbitfld.long 0x10 31. "NEED_CLOCK,1' indicates that the TRNG is busy generating entropy or is in one of its test modes - the module clock may not be turned off. This bit is a direct mirror of the 'need_clock'output signal of the module." "0,1" newline hexmask.long.byte 0x10 24.--30. 1. "BLOCKS_THRESH,The threshold value for the 'blocks_available' field to indicate 'ready' here. The value iswritten via bits [30:24] of the TRNG_INTACK register. The number of blocks availablein the RAM buffer must be equal to or greater than the value in.." newline hexmask.long.byte 0x10 16.--23. 1. "BLOCKS_AVAILABLE,This field indicates the number of 128 bits blocks of random data that are available inthe random data RAM buffer [if configured]. If this value is non-zero the outputregisters will be re-filled from the random data RAM buffer.." newline rbitfld.long 0x10 15. "TEST_STUCK_OUT,1' = indication that 'stuck_out' functionality testing is enabled [via TRNG_INTACKregister bit [15]]. This bit will automatically fall back to '0' when a stuck output isactually detected." "?,1: indication that 'stuck_out' functionality.." newline rbitfld.long 0x10 14. "APROP_FAIL,1' = the [SP 800-90B] 'Adaptive Proportion' test logic monitoring the data shifted intothe main shift register detected too many 8-bit Noise Source output samples matchingthe first sample taken in the test window. Bits [31:30] of the.." "?,1: the [SP 800-90B] 'Adaptive Proportion' test.." newline rbitfld.long 0x10 13. "REPCNT_FAIL,1' = the [SP 800-90B] 'Repetition Count' test logic monitoring the data shifted into themain shift register detected a number of consecutive identical 8-bit Noise Source outputsamples that matched the programmed cutoff value. Writing a '1' to.." "?,1: the [SP 800-90B] 'Repetition Count' test logic.." newline bitfld.long 0x10 11.--12. "RESERVED_0,Bits should be ignored on a read." "0,1,2,3" newline rbitfld.long 0x10 10. "RESEED_AI,For the EIP-76d configurations with BC_DF functionality this bit indicates when theTRNG_PS_AI_ - registers must be written for an 'Instantiate' or 'Reseed' operation[Writing the highest Byte of the TRNG_PS_AI_11 register then clears this.." "0,1" newline rbitfld.long 0x10 9. "STUCK_NRBG,1' = NRBG stuck error; this happens when two identical values were extracted fromthe main shift register [configuration without Conditioning Function] or theConditioning Function output [when configured]." "?,1: NRBG stuck error" newline rbitfld.long 0x10 8. "TEST_READY,Multi-purpose bit:> For known-answer tests on the 'Repetition Count' 'Adaptive Proportion' 'monobit' 'run' and 'poker' tests BC_DF functionality and Conditioning Function a '1' indicates that data can be written to the TRNG_RAW_..." "0,1" newline rbitfld.long 0x10 7. "MONOBIT_FAIL,1' = the [AIS-31] 'monobit test' logic monitoring data shifted into the main shiftregister detected an out-of-bounds number of '1's after checking 20 000 bits [test T1 asspecified in the [AIS-31] standard]. Writing a '1' to bit [7] of the.." "?,1: the [AIS-31] 'monobit test' logic monitoring.." newline rbitfld.long 0x10 6. "POKER_FAIL,1' = the [AIS-31] 'poker test' logic monitoring data shifted into the main shift registerdetected an out-of-bounds value in at least one of the 16 'poker_count_X' counters or anout of bounds 'sum of squares' value after checking 20 000 bits.." "?,1: the [AIS-31] 'poker test' logic monitoring data.." newline rbitfld.long 0x10 5. "LONG_RUN_FAIL,1' = the [AIS-31] 'run test' logic monitoring data shifted into the main shift registerdetected a sequence of 34 identical bits [test T4 as specified in the [AIS-31] standard].Writing a '1' to bit [5] of the TRNG_INTACK register clears this.." "?,1: the [AIS-31] 'run test' logic monitoring data.." newline rbitfld.long 0x10 4. "RUN_FAIL,1' = the [AIS-31] 'run test' logic monitoring data shifted into the main shift registerdetected an out-of-bounds value for at least one of the 'run_X_count_...' counters afterchecking 20 000 bits [test T3 as specified in the [AIS-31] standard]." "?,1: the [AIS-31] 'run test' logic monitoring data.." newline rbitfld.long 0x10 3. "NOISE_FAIL,1' = the [AIS-31] 'run test' logic monitoring data shifted into the main shift registerdetected a sequence of 48 identical bits which is considered a 'Noise Source failure' asproposed in section E.5 of the [AIS-31] standard. Writing a '1' to.." "?,1: the [AIS-31] 'run test' logic monitoring data.." newline rbitfld.long 0x10 2. "STUCK_OUT,1' = logic around the output data registers4 detected that the EIP-76 generates the samevalue twice in a row. The word size for this comparison is 128 bits. Writing a '1' to bit[2] of the TRNG_INTACK register clears this bit to '0'." "?,1: logic around the output data registers4 detected.." newline rbitfld.long 0x10 1. "SHUTDOWN_OFLO,1' = the number of FROs shut down after a second 'error event' [i.e. the number of '1'bits in the TRNG_ALARMSTOP register] has exceeded the threshold set by'shutdown_threshold' in the TRNG_ALARMCNT register. Writing a '1' to bit [1] of.." "?,1: the number of FROs shut down after a second.." newline rbitfld.long 0x10 0. "READY,1' = data is available in the TRNG_OUTPUT_0 - 3 registers. Acknowledging this stateby Writing a '1' to bit [0] of the TRNG_INTACK register clears this bit to '0'. If a newnumber is already available in the random data buffer that number is.." "?,1: data is available in the TRNG_OUTPUT_0" line.long 0x14 "HSM_TRNG_TRNG_CONTROL,Control register." hexmask.long.word 0x14 20.--31. 1. "DATA_BLOCKS,This field indicates the number of 128 bit data blocks that must be generated by the [SP800-90A] AES-256 DRBG in a single 'Generate_function'. It is loaded in a write to thisregister where the 'request_data' bit is '1' [and the 're_seed' bit.." newline bitfld.long 0x14 18.--19. "RESERVED_0,Bits should be written with '0' and should be ignored on a read." "0,1,2,3" newline bitfld.long 0x14 17. "REQUEST_HOLD,Read/write this bit can only be set to '1' when the 'data_blocks' field has value zero andByte Writing only bits [23:16] setting the 'request_data' bit to '1' and loading bits[23:20] of the 'data_blocks' field. Value '1' in this bit.." "0,1" newline bitfld.long 0x14 16. "REQUEST_DATA,Write-only Writing a '1' indicates that the 'data_blocks' field contains the number of128 bit data blocks that the [SP 800-90A] AES-256 DRBG should generate in a single'Generate_function'. Writing a '0' has no effect.Note: This bit is only.." "0,1" newline bitfld.long 0x14 15. "RE_SEED,Set-only Writing a '1' starts a 'Reseed' as described in section 5.2.5.4 below Writing a'0' has no effect.This bit falls back to '0' automatically after the 'Reseed' operation is complete - at thattime the 'block_count' field in the.." "0,1" newline bitfld.long 0x14 14. "APROP_FAIL_MASK,1' = allow the 'aprop_fail' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output." "?,1: allow the 'aprop_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 13. "REPCNT_FAIL_MASK,1' = allow the 'repcnt_fail' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output." "?,1: allow the 'repcnt_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 12. "DRBG_EN,Enable the [SP 800-90A] AES-256 DRBG. If this bit is reset to '0' the DRBG is forcedback into the idle state immediately.Note: This bit is only present when the SP 800-90A AES-256 DRBG is available andcan only be changed when 'enable_trng' was.." "0,1" newline bitfld.long 0x14 11. "NO_WHITENING,The default value of '0' means that toggle-flop whitening of the noise source is enabled.Set this bit to '1' to disable the toggle flip-flop based whitening of the noise source seesection 3.2 for details. In this mode the sampling interval.." "0,1" newline bitfld.long 0x14 10. "ENABLE_TRNG,Setting this bit to '1' starts the EIP-76 gathering entropy from the FROs. Resetting thisbit to '0' forces all NRBG logic back into the idle state immediately.For the [SP 800-90A] DRBG option starting the EIP-76 with the 'drbg_en' bit value.." "0,1" newline bitfld.long 0x14 9. "STUCK_NRBG_MASK,1' = allow the 'stuck_nrbg' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output." "?,1: allow the 'stuck_nrbg' bit in the TRNG_STATUS.." newline bitfld.long 0x14 8. "TEST_MODE,1' = Enables access to [amongst others] the TRNG_COUNT and TRNG_RAW_L/Hregisters [the latter are cleared before enabling access] and keep 'need_clock' outputactive 'high' for testing purposes. This bit must be set to '1' before various test.." "?,1: Enables access to [amongst others] the.." newline bitfld.long 0x14 7. "MONOBIT_FAIL_MASK,1' = allow the 'monobit_fail' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output.Note: This bit is only available if AIS-31 testing logic is configured otherwise it mustbe treated as 'Reserved'." "?,1: allow the 'monobit_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 6. "POKER_FAIL_MASK,1' = allow the 'poker_fail' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output.Note: This bit is only available if AIS-31 testing logic is configured otherwise it mustbe treated as 'Reserved'" "?,1: allow the 'poker_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 5. "LONG_RUN_FAIL_MASK,1' = allow the 'long_run_fail' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output.Note: This bit is only available if AIS-31 testing logic is configured otherwise it mustbe treated as 'Reserved'." "?,1: allow the 'long_run_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 4. "RUN_FAIL_MASK,1' = allow the 'run_fail' bit in the TRNG_STATUS register to activate the [active 'high']'irq' output.Note: This bit is only available if AIS-31 testing logic is configured otherwise it mustbe treated as 'Reserved'." "?,1: allow the 'run_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 3. "NOISE_FAIL_MASK,1' = allow the 'noise_fail' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output.Note: This bit is only available if AIS-31 testing logic is configured otherwise it mustbe treated as 'Reserved'." "?,1: allow the 'noise_fail' bit in the TRNG_STATUS.." newline bitfld.long 0x14 2. "STUCK_OUT_MASK,1' = allow the 'stuck_out' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output." "?,1: allow the 'stuck_out' bit in the TRNG_STATUS.." newline bitfld.long 0x14 1. "SHUTDOWN_OFLO_MASK,1' = allow the 'shutdown_oflo' bit in the TRNG_STATUS register to activate the [active'high'] 'irq' output." "?,1: allow the 'shutdown_oflo' bit in the TRNG_STATUS.." newline bitfld.long 0x14 0. "READY_MASK,1' = allow the 'ready' bit in the TRNG_STATUS register to activate the [active 'high']'irq' output." "?,1: allow the 'ready' bit in the TRNG_STATUS.." line.long 0x18 "HSM_TRNG_TRNG_CONFIG,Configuration register." hexmask.long.word 0x18 16.--31. 1. "SAMPLE_CYCLES,This field together with the 'scale' field defines the number of clock cycles beforeshifting the main shift register and thereby freezing the noise sample. This value mustbe such that there is at least one bit of entropy [in total] in.." newline hexmask.long.byte 0x18 12.--15. 1. "READ_TIMEOUT,This field controls the secure Reading mode [see section 5.2.6.2]. Value 0 disablessecure Reading values in the range 1 - 15 enable secure Reading and set a read gateclosure timeout of approximately [read_timeout] x 16 'clk' input.." newline hexmask.long.byte 0x18 8.--11. 1. "SAMPLE_DIV,This field directly controls the number of 'clk' input cycles between samples takenfrom the FROs. The default value 0 indicates that samples are taken every 'clk' cycle maximum value 15 [decimal] takes one sample every 16 'clk' cycles.This.." newline bitfld.long 0x18 6.--7. "SCALE,This field sets the scale factor for the 'sample_cycles' value:0 -> number of XOR-ed FRO samples equals 'sample_cycles'1 -> number of XOR-ed FRO samples equals 'sample_cycles' x 42 -> number of XOR-ed FRO samples equals 'sample_cycles' x 163 ->.." "0: number of XOR-ed FRO samples equals..,?,?,?" newline bitfld.long 0x18 5. "USE_STARTUP_BITS,Do not discard the first 512 bits of raw data. This reduces the start-up time but maymore frequently cause start-up health test failures.For configurations without Conditioning function: When enabled the first 128 bits willstill be.." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "NOISE_BLOCKS,This field sets the number of 512-bit blocks of raw Noise Source output data that mustbe processed by either the Conditioning Function or the SP 800-90 DRBG 'BC_DF'functionality to yield a 'full entropy' output value. As according to [SP.." line.long 0x1C "HSM_TRNG_TRNG_ALARMCNT,Shutdown interr. ctrl register." bitfld.long 0x1C 30.--31. "RESERVED_2,Bits should be written with a '0' and should be ignored on a read." "0,1,2,3" newline hexmask.long.byte 0x1C 24.--29. 1. "SHUTDOWN_COUNT,Read-only indicates the number of '1' bits in the TRNG_ALARMSTOP register.This field is 6 bits wide to allow up to 32 'ones' to be indicated. The actual maximumvalue equals the number of FROs." newline bitfld.long 0x1C 23. "SHUTDOWN_FATAL,1' = Consider the 'shutdown_oflo' interrupt as a fatal error requiring taking the completeTRNG engine off-line" "?,1: Consider the 'shutdown_oflo' interrupt as a.." newline bitfld.long 0x1C 21.--22. "RESERVED_1,Bits should be written with a '0' and should be ignored on a read." "0,1,2,3" newline hexmask.long.byte 0x1C 16.--20. 1. "SHUTDOWN_THRESHOLD,Threshold setting for generating the 'shutdown_oflo' interrupt which is activated whenthe 'shutdown_count' value in this register exceeds the threshold value set here." newline bitfld.long 0x1C 15. "STALL_RUN_POKER,1' = Stall the 'monobit test' 'run test' and 'poker test' circuits when either the'monobit_fail' 'run_fail' or 'poker_fail' bits in the TRNG_STATUS register are set to '1' - this allows inspecting the state of the result counters [which.." "?,1: Stall the 'monobit test'" newline hexmask.long.byte 0x1C 8.--14. 1. "RESERVED_0,Bits should be written with a '0' and should be ignored on a read." newline hexmask.long.byte 0x1C 0.--7. 1. "ALARM_THRESHOLD,Alarm detection threshold for the repeating pattern detectors on each FRO. A FRO'alarm event' is declared when a repeating pattern [of up to four samples length] isdetected continuously for the number of samples defined by this field's.." line.long 0x20 "HSM_TRNG_TRNG_FROENABLE,FRO enables register." hexmask.long.byte 0x20 24.--31. 1. "RESERVED_4,Bits should be written with a '0' and should be ignored on a read." newline hexmask.long.tbyte 0x20 0.--23. 1. "TRNG_FROENABLE,Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. The default stateis all ones to enable all FROs after power-up. Note that they are not actually started upbefore the 'enable_trng' bit in the TRNG_CONTROL register is.." line.long 0x24 "HSM_TRNG_TRNG_FRODETUNE,FRO de-tune bits register." hexmask.long.byte 0x24 24.--31. 1. "RESERVED_5,Bits should be written with a '0' and should be ignored on a read." newline hexmask.long.tbyte 0x24 0.--23. 1. "TRNG_FRODETUNE,De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run approximately5 0.000000aster. The value of one of these bits may only be changed while the correspondingFRO is turned off [by temporarily Writing a '0' in the.." line.long 0x28 "HSM_TRNG_TRNG_ALARMMASK,Alarm event log register." hexmask.long.byte 0x28 24.--31. 1. "RESERVED_6,Bits should be written with a '0' and should be ignored on a read." newline hexmask.long.tbyte 0x28 0.--23. 1. "TRNG_ALARMMASK,Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO'n' experienced an 'alarm event'." line.long 0x2C "HSM_TRNG_TRNG_ALARMSTOP,Alarm shutdown register." hexmask.long.byte 0x2C 24.--31. 1. "RESERVED_7,Bits should be written with a '0' and should be ignored on a read." newline hexmask.long.tbyte 0x2C 0.--23. 1. "TRNG_ALARMSTOP,Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] indicates FRO'n' experienced more than one 'alarm event' in quick succession and has been turnedoff. A '1' in this field forces the corresponding bit in the.." line.long 0x30 "HSM_TRNG_TRNG_RAW_L,Raw noise bits [31:0]." hexmask.long 0x30 0.--31. 1. "TRNG_RAW_L,When 'test_mode' in TRNG_CONTROL = '1' 'test_noise' in TRNG_TEST = '1' and'test_shiftreg' in TRNG_TEST = '0': read-only access to the main shift register's readbuffer register bits [31:0].When 'test_mode' in TRNG_CONTROL = '1' 'test_noise'.." line.long 0x34 "HSM_TRNG_TRNG_RAW_H,Raw noise bits [63:32]." hexmask.long 0x34 0.--31. 1. "TRNG_RAW_H,When 'test_mode' in TRNG_CONTROL = '1' 'test_noise' in TRNG_TEST = '1' and'test_shiftreg' in TRNG_TEST = '0': read-only access to the main shift register's readbuffer register bits [63:32].When 'test_mode' in TRNG_CONTROL = '1' 'test_noise'.." line.long 0x38 "HSM_TRNG_TRNG_SPB_TESTS,SP 800-90B tests control/state." bitfld.long 0x38 31. "APROP_512_FAIL,Bit indicating that the 'aprop_512_counter' was equal to the 'aprop_512_cutoff' setting.The state of this bit is OR-ed with the 'aprop_64_fail' bit into the 'aprop_fail' bit in theTRNG_STATUS register and cleared to '0' when Writing a '1'.." "0,1" newline bitfld.long 0x38 30. "APROP_64_FAIL,Bit indicating that the 'aprop_64_counter' was equal to the 'aprop_64_cutoff' setting. Thestate of this bit is OR-ed with the 'aprop_512_fail' bit into the 'aprop_fail' bit in theTRNG_STATUS register and cleared to '0' when Writing a '1' to.." "0,1" newline bitfld.long 0x38 29. "SHOW_VALUES,Bit controlling what is actually accessible in this register; can only be set to '1' when'test_spb' in TRNG_TEST is '1'. When Writing this bit to a different value all other bitsin this register are preserved.When Writing both.." "0,1" newline bitfld.long 0x38 28. "SHOW_COUNTERS,Bit controlling what is actually accessible in this register; can only be set to '1' when'show_values' is written '0' and 'test_spb' in TRNG_TEST is '1'. When Writing this bitto a different value all other bits in this register are.." "0,1" newline bitfld.long 0x38 25.--27. "RESERVED_2,Bits should be written with a '0' and should be ignored on a read while 'show_values'equals '1'." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 16.--24. 1. "APROP_512_CUTOFF,Adaptive Proportion' test cutoff value for the 512 Noise Source samples window sizetest accessible when 'show_counters' and 'show_values' are both '0'. The reset value of325 corresponds to the cutoff value for a false positive rate of.." newline bitfld.long 0x38 14.--15. "RESERVED_1,Bits should be written with a '0' and should be ignored on a read while 'show_values'equals '0'." "0,1,2,3" newline hexmask.long.byte 0x38 8.--13. 1. "APROP_64_CUTOFF,Adaptive Proportion' Noise Source sample compare value for the 64 Noise Sourcesamples window size test accessible when 'show_values' is '1'. This field is writeablefor testing purposes." newline bitfld.long 0x38 6.--7. "RESERVED_0,Bits should be written with a '0' and should be ignored on a read while 'show_values'equals '0'." "0,1,2,3" newline hexmask.long.byte 0x38 0.--5. 1. "REPCNT_CUTOFF,Repetition Count' test cutoff value accessible when 'show_counters' and 'show_values'are both '0'. The reset value of 31 corresponds to the cutoff value for a false positiverate of 2-30 and 1 bit of entropy per 8-bit Noise Source sample." line.long 0x3C "HSM_TRNG_TRNG_COUNT,Main timing counters register." bitfld.long 0x3C 30.--31. "RESERVED_1,Bits should be written with a '0' and should be ignored on a read." "0,1,2,3" newline hexmask.long.byte 0x3C 24.--29. 1. "SAMPLE_CYC_EXT,Extension bits for the sample cycle counter used when the 'scale' field in theTRNG_CONFIG register is non-zero. This counter can only be accessed when the'test_mode' bit in TRNG_CONTROL is set to '1'." newline bitfld.long 0x3C 21.--23. "RESERVED_0,Bits should be written with a '0' and should be ignored on a read." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 16.--20. 1. "NOISE_BLK_CNT,Noise blocks counter used to control the number of 512-bits noise blocks to be handledby the SHA-1/SHA-256 Conditioning Function or BC_DF functionality in the SP 800-90A DRBG [depending on configuration]. The start value of this counter is.." newline hexmask.long.word 0x3C 0.--15. 1. "SAMPLE_CYC_CNT,Lowest 16 bits of the sample cycle counter used to control the number of [XOR-ed]FRO samples that are XOR-ed together into a single noise bit. The start value of thiscounter is 1 which is also the value to which it is reset when it.." wgroup.long 0x40++0x2F line.long 0x0 "HSM_TRNG_TRNG_PS_AI_0,DRBG input (LSW)." hexmask.long 0x0 0.--31. 1. "VECTOR,Bits [31:0] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function] or'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x4 "HSM_TRNG_TRNG_PS_AI_1,DRBG input." hexmask.long 0x4 0.--31. 1. "VECTOR,Bits [63:32] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x8 "HSM_TRNG_TRNG_PS_AI_2,DRBG input." hexmask.long 0x8 0.--31. 1. "VECTOR,Bits [95:64] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0xC "HSM_TRNG_TRNG_PS_AI_3,DRBG input." hexmask.long 0xC 0.--31. 1. "VECTOR,Bits [127:96] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x10 "HSM_TRNG_TRNG_PS_AI_4,DRBG input." hexmask.long 0x10 0.--31. 1. "VECTOR,Bits [159:128] of the SP 800-90 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90 DRBG is configured." line.long 0x14 "HSM_TRNG_TRNG_PS_AI_5,DRBG input." hexmask.long 0x14 0.--31. 1. "VECTOR,Bits [191:160] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x18 "HSM_TRNG_TRNG_PS_AI_6,DRBG input." hexmask.long 0x18 0.--31. 1. "VECTOR,Bits [223:192] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x1C "HSM_TRNG_TRNG_PS_AI_7,DRBG input." hexmask.long 0x1C 0.--31. 1. "VECTOR,Bits [255:224] of the SP 800-90 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90 DRBG is configured." line.long 0x20 "HSM_TRNG_TRNG_PS_AI_8,DRBG input." hexmask.long 0x20 0.--31. 1. "VECTOR,Bits [287:256] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x24 "HSM_TRNG_TRNG_PS_AI_9,DRBG input." hexmask.long 0x24 0.--31. 1. "VECTOR,Bits [319:288] of the SP 800-90 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90 DRBG is configured." line.long 0x28 "HSM_TRNG_TRNG_PS_AI_10,DRBG input." hexmask.long 0x28 0.--31. 1. "VECTOR,Bits [351:320] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured." line.long 0x2C "HSM_TRNG_TRNG_PS_AI_11,DRBG input (MSW)." hexmask.long 0x2C 0.--31. 1. "VECTOR,Bits [383:352] of the SP 800-90A 'Personalization String'/'Nonce' [Instantiate function]or 'Additional Input' [Reseed and Generate functions]. This register is only availablewhen an SP 800-90A DRBG is configured.Note: This register must be written.." group.long 0x70++0xF line.long 0x0 "HSM_TRNG_TRNG_TEST,Test control register." bitfld.long 0x0 31. "TEST_IRQ,1' = force 'irq' output 'high' for interrupt signal connectivity testing." "?,1: force 'irq' output 'high' for interrupt signal.." newline bitfld.long 0x0 30. "FRO_TESTIN4,Control bit driving the 'fro_testin4' output of the TRNG module which connects to allthe select inputs on the test multiplexers in the FROs [see Figure 3]. The actual outputhas the state of this bit so a '0' selects the output of the delay.." "0,1" newline bitfld.long 0x0 29. "FRO_TESTIN3,Control bit driving the 'fro_testin3' output of the TRNG module which connects to allthe OR inputs on the AND-OR gates in the FRO chains [see Figure 3]. The actualoutput has the state of this bit so a '0' does not disturb the operation of.." "0,1" newline bitfld.long 0x0 28. "FRO_TESTIN2_NOT,Control bit driving the 'fro_testin2' output of the TRNG module which connects to allthe AND inputs on the AND-OR gates in the FRO chains [see Figure 3]. The actualoutput is the complement of this bit so a '0' does not disturb the.." "0,1" newline hexmask.long.word 0x0 16.--27. 1. "TEST_PATTERN,Repeating sequence of bits to be fed into the selected FRO delay chain ['test_patt_fro' ='1'] and/or the selected FRO error detection circuit ['test_patt_det' = '1']. This field isrotated right over one bit once every sample period when.." newline bitfld.long 0x0 15. "RESERVED_0,RESERVED_0" "0,1" newline bitfld.long 0x0 14. "TEST_SPB,1' = Enable testing of the [SP 800-90B] 'Repetition Count' and 'Adaptive Proportion'tests by allowing the 'show_counters' and 'show_values' bits in the TRNG_SPB_TESTSregister to be set non-zero. To perform Known Answer Tests on those functions .." "?,1: Enable testing of the [SP 800-90B] 'Repetition.." newline bitfld.long 0x0 13. "TEST_NOISE,1' = Enable Noise Source testing making 64 bit blocks of Noise Source outputavailable in the TRNG_RAW_... registers. When 'test_shiftreg' is '0' these must beacknowledged by Writing a '1' to the 'test_ready_ack' bit in the TRNG_ACK.." "?,1: Enable Noise Source testing" newline hexmask.long.byte 0x0 8.--12. 1. "TEST_SELECT,Number of the FRO to be tested value should be in range 0 - 23 for the defaultconfiguration of 24 FROs." newline bitfld.long 0x0 7. "TEST_SP_800_90,1' = Provide direct access to the [SP 800-90A] DRBG [EIP-76d] for NIST compliantknown-answer tests [DRBG state is lost during testing]. The 'need_clock' output isforced active while this bit is '1'. See section 5.2.21.4 below for more.." "?,1: Provide direct access to the [SP 800-90A] DRBG.." newline bitfld.long 0x0 6. "TEST_AES_256,Dual purpose bit that is only present when an [SP 800-90A] DRBG is available [EIP-76d] and can only be set to '1' when the 'drbg_en' bit in the TRNG_CONTROL registeris '1' and the 'test_known_noise' bit in this register is '0'.When.." "0: perform fixed sequence SP 800-90A known answer..,1: perform variable sequence SP 800-90A known.." newline bitfld.long 0x0 5. "TEST_KNOWN_NOISE,1' = Allow Writing of known test data into the main shift register [Writing input data inchunks of 64 bits to the TRNG_RAW_L and TRNG_RAW_H registers] and allow Writingof the 'noise_blocks' 'sample_interval' and 'sample_cycles' fields.." "?,1: Allow Writing of known test data into the main.." newline bitfld.long 0x0 4. "CONT_POKER,1' = Keep 'monobit test' and 'poker test' running continuously by not resetting the'monobit_count' and 'poker_count_X' counters at the end of each 20 000 bits test block.This bit can only be set to '1' when 'test_mode' in TRNG_CONTROL is '1'.." "?,1: Keep 'monobit test' and 'poker test' running.." newline bitfld.long 0x0 3. "TEST_SHIFTREG,1' = Read directly from the main shift register when 'test_noise' is set to '1' '0' = readfrom the shift register buffer [using the 'test_ready' bit in the TRNG_STATUS register toindicate that a new batch of 64 bits can be read].This bit.." "0: readfrom the shift register buffer [using the..,1: Read directly from the main shift register when.." newline bitfld.long 0x0 2. "TEST_PATT_DET,1' = Repeatedly feed 'test_pattern' into the error detection circuit of the FRO selectedby the 'test_select' field.This bit can only be set to '1' when 'test_mode' in TRNG_CONTROL is '1' too." "?,1: Repeatedly feed 'test_pattern' into the error.." newline bitfld.long 0x0 1. "TEST_PATT_FR,1' = Repeatedly feed 'test_pattern' into the delay chain of the FRO selected by the'test_select' field by forcing the corresponding 'fro_enable' output 'low' and forcingthe corresponding 'fro_testin' output to the state of bit [16] of this.." "?,1: Repeatedly feed 'test_pattern' into the delay.." newline bitfld.long 0x0 0. "TEST_EN_OUT,1' = Enable the 'tst_fro_clk_out' output connecting to the FRO selected by the'test_select' field.This bit can only be set to '1' when 'test_mode' in TRNG_CONTROL is '1' too." "?,1: Enable the 'tst_fro_clk_out' output" line.long 0x4 "HSM_TRNG_TRNG_BLOCKCNT,Output blocks counter." hexmask.long 0x4 4.--31. 1. "BLOCK_COUNT,Counter for the number of 128-bit blocks generated by the DRBG. It is forced back tozero when the DRBG is disabled and cleared to zero when an internal 'Reseed'operation has finished. This register can be used by driver software to determine.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_0,Bits should be written with a '0' and should be ignored on a read." line.long 0x8 "HSM_TRNG_TRNG_OPTIONS,Engine options information." hexmask.long.byte 0x8 24.--31. 1. "DETUNE_COUNT,Indicates the number of detune events that occurred on the enabled FROs. The counteris incremented by one on each detune event up to a value 255. The counter will remainat 255 when more detune events occur. The counter can be cleared by.." newline bitfld.long 0x8 23. "AUTO_DETUNE,When written with '1' automatic detuning is enabled. For the 'basic' functionality thedetuning is done when 'shutdown_count' exceeds 'shutdown_threshold'. At that pointFROs that have a '1' in the TRNG_ALARMSTOP register are re-enabled in.." "0,1" newline bitfld.long 0x8 22. "RESERVED_3,Bits should be ignored on a read." "0,1" newline rbitfld.long 0x8 21. "APROP_512,0: [legacy] The Adaptive Proportion test works with a window size of4096bit whichwas the size for earlier draft versions of [SP 800-90B].1:[default] The Adaptive Proportion test works with a window size of 512 bits asspecified in [SP 800-90B]." "0: [legacy] The Adaptive Proportion test works with..,1: [default] The Adaptive Proportion test works.." newline rbitfld.long 0x8 19.--20. "DETUNING_OPTION,0: no automatic detuning functionality is present1:'basic' detuning functionality is present. Default for all standard configurations.Other values are reserved" "0: no automatic detuning functionality is..,?,?,?" newline rbitfld.long 0x8 17.--18. "CONDITIONER,0: no Conditioning Function is present or a BC_DF Conditioning Function is presentwhen an AES DRBG is present as well.1:a SHA1-based Conditioning Function is present.2:a SHA-256 based Conditioning Function is present.Other values are reserved." "0: no Conditioning Function is present or a BC_DF..,1: a SHA1-based Conditioning Function is present,2: a SHA-256 based Conditioning Function is present,?" newline rbitfld.long 0x8 16. "PR_TEST,Indicates that Monobit poker and run test circuits are available." "0,1" newline bitfld.long 0x8 15. "RESERVED_1,Bit should be ignored on a read." "0,1" newline rbitfld.long 0x8 12.--14. "BUFFER_SIZE,Value 0 indicates no random data buffer is implemented values 2 - 7 indicate thenumber of address bits used to address 128 bit buffer blocks in the random data buffer[so value 2 indicates a 4 blocks/512 bits/64 Byte/16 word buffer while.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 6.--11. 1. "NR_OF_FROS,Number of FROs implemented in this TRNG values 24 and 8 [decimal] are standardoptions available." newline bitfld.long 0x8 3.--5. "RESERVED_0,Bits should be ignored on a read." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 0.--2. "POST_PROCESSOR,0: no DRBG is present [EIP-76a]5:an SP 800-90A AES-256 DRBG is present [EIP-76d].Other values reserved.Note: If the DRBG option is selected without selecting a Conditioning Function[conditioner_option = 0] then the DRBG will be fitted.." "0: no DRBG is present [EIP-76a]5:an SP 800-90A..,?,?,?,?,?,?,?" line.long 0xC "HSM_TRNG_TRNG_EIP_REV,EIP number and core revision." hexmask.long.byte 0xC 28.--31. 1. "RESERVED_0,Bits should be ignored on a read." newline hexmask.long.byte 0xC 24.--27. 1. "MAJOR_HW_REVISION,4-bit binary encoding of the major hardware revision number." newline hexmask.long.byte 0xC 20.--23. 1. "MINOR_HW_REVISION,4-bit binary encoding of the minor hardware revision number" newline hexmask.long.byte 0xC 16.--19. 1. "HW_PATCH_LEVEL,4-bit binary encoding of the hardware patch level initial release will carry value zero." newline hexmask.long.byte 0xC 8.--15. 1. "COMPLEMENT_OF_BASIC_EIP_NUMBER,Bit-by-bit logic complement of bits [7:0]" newline hexmask.long.byte 0xC 0.--7. 1. "BASIS_EIP_NUMBER,Bit-by-bit logic complement of bits [7:0]" tree.end tree.end tree "I2C" base ad:0x0 tree "I2C0" base ad:0x52500000 group.long 0x0++0x3F line.long 0x0 "I2C_ICOAR,I2C Own Address register" hexmask.long.tbyte 0x0 10.--31. 1. "NU,Reserved" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C_ICIMR,I2C Interrupt Mask/Status register" hexmask.long 0x4 7.--31. 1. "NU,Reserved" bitfld.long 0x4 6. "AAS,Address As Target interrupt mask bit. Setting a'1' to this bit unmasks the Address As Target interrupt. Setting a'0' to this bit masks the Address As Target interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C_ICSTR,I2C Interrupt Status register" hexmask.long.tbyte 0x8 15.--31. 1. "NU2,Reserved" bitfld.long 0x8 14. "SDIR,Target Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a target receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C target is a transmitter. In DLB.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT 0:A No Acknowledge is not sent. NACKSNT 1:A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB0:The bus is free. BB1:The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register [ICRSR] is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register [ICXSR] is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Target. This bit is set to 1 by the device when it has recognized its own target address or an address of all [8] zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - [RW ]" "0,1" bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all [8] zeros [i.e. general call]. The AD0 bit is reset to 0 [default value] when a'start' or'stop' condition is detected. - [RW ]" "0,1" newline bitfld.long 0x8 6.--7. "NU1,Reserved" "0,1,2,3" bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by Reading ICIVR [as 110] or Writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register [ICXSR]. ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR [as 010].." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C_ICCLKL,I2C Clock Divider Low register" hexmask.long.word 0xC 16.--31. 1. "NU,Reserved" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x10 "I2C_ICCLKH,I2C Clock Divider High register" hexmask.long.word 0x10 16.--31. 1. "NU,Reserved" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x14 "I2C_ICCNT,I2C Data Count register" hexmask.long.word 0x14 16.--31. 1. "NU,Reserved" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified [STP=1]. . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C_ICDRR,I2C Data Receive register" hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C_ICSAR,I2C Slave Address register" hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Target address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C_ICDXR,I2C Data Transmit register" hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C_ICMDR,I2C Mode register" hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved" bitfld.long 0x24 15. "NACKMOD,No Acknowledge [NACK] mode. This bit is used to send an Acknowledge [ACK] or a No Acknowledge [NACK] to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE0:[default] Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL.." "0,1" bitfld.long 0x24 13. "STT,Start Condition [Master only mode]. This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN [IDLE Enable on5509. - [RW ]" "0,1" bitfld.long 0x24 11. "STP,Stop Condition [Master mode only]. This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST0:The I 2 C peripheral is in the'target' mode and clock is received from the'master' device. MST1:The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0,1" bitfld.long 0x24 9. "TRX,Transmitter. TRX0:The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX1:The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes [not.." "0,1" newline bitfld.long 0x24 8. "XA,Expanded Address. XA0:[default] 7-bit address mode [normal address mode]. XA1:10-bit address mode [expanded address mode] Please note that XA needs to be configured even if the I2C is in target mode." "0,1" bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back [in master transmit mode only]. This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after [[CPU freq/I2C freq]8] CPU cycles via.." "0,1" bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte [Master only mode]. The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001' regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Target in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb [excluding the acknowledge bit] of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C_ICIVR,I2C Interrupt Vector register" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY[011] RRDY[100] and XRDY[101]. Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C_ICEMDR,I2C Extended Mode register" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the target. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C_ICPSC,I2C Prescaler register" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset [IRS_=0]. The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C_ICPID1,I2C Peripheral ID register 1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - [RW ]" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - [RW ]" line.long 0x38 "I2C_ICPID2,I2C Peripheral ID register 2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - [RW ]" line.long 0x3C "I2C_ICDMAC,I2C DMA Control Register" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0,1" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0,1" group.long 0x48++0x1B line.long 0x0 "I2C_ICPFUNC,I2C Pin Function register" hexmask.long 0x0 1.--31. 1. "NU,Reserved." bitfld.long 0x0 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4 "I2C_ICPDIR,I2C Pin Direction register" hexmask.long 0x4 2.--31. 1. "NU,Reserved" bitfld.long 0x4 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x8 "I2C_ICPDIN,I2C Pin Data In register" hexmask.long 0x8 2.--31. 1. "NU,Reserved" bitfld.long 0x8 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - [RW ]" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x8 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - [RW ]" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0xC "I2C_ICPDOUT,I2C Pin Data Out register" hexmask.long 0xC 2.--31. 1. "NU,Reserved" bitfld.long 0xC 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0xC 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x10 "I2C_ICPDSET,I2C Pin Data Set register" hexmask.long 0x10 2.--31. 1. "NU,Reserved" bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x14 "I2C_ICPDCLR,I2C Pin Data Clear register" hexmask.long 0x14 2.--31. 1. "NU,Reserved" bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x18 "I2C_ICPDRV,I2C Pin Driver Mode Register" hexmask.long 0x18 2.--31. 1. "NU,Reserved" bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree "I2C1" base ad:0x52501000 group.long 0x0++0x3F line.long 0x0 "I2C_ICOAR,I2C Own Address register" hexmask.long.tbyte 0x0 10.--31. 1. "NU,Reserved" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C_ICIMR,I2C Interrupt Mask/Status register" hexmask.long 0x4 7.--31. 1. "NU,Reserved" bitfld.long 0x4 6. "AAS,Address As Target interrupt mask bit. Setting a'1' to this bit unmasks the Address As Target interrupt. Setting a'0' to this bit masks the Address As Target interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C_ICSTR,I2C Interrupt Status register" hexmask.long.tbyte 0x8 15.--31. 1. "NU2,Reserved" bitfld.long 0x8 14. "SDIR,Target Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a target receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C target is a transmitter. In DLB.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT 0:A No Acknowledge is not sent. NACKSNT 1:A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB0:The bus is free. BB1:The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register [ICRSR] is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register [ICXSR] is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Target. This bit is set to 1 by the device when it has recognized its own target address or an address of all [8] zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - [RW ]" "0,1" bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all [8] zeros [i.e. general call]. The AD0 bit is reset to 0 [default value] when a'start' or'stop' condition is detected. - [RW ]" "0,1" newline bitfld.long 0x8 6.--7. "NU1,Reserved" "0,1,2,3" bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by Reading ICIVR [as 110] or Writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register [ICXSR]. ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR [as 010].." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C_ICCLKL,I2C Clock Divider Low register" hexmask.long.word 0xC 16.--31. 1. "NU,Reserved" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x10 "I2C_ICCLKH,I2C Clock Divider High register" hexmask.long.word 0x10 16.--31. 1. "NU,Reserved" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x14 "I2C_ICCNT,I2C Data Count register" hexmask.long.word 0x14 16.--31. 1. "NU,Reserved" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified [STP=1]. . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C_ICDRR,I2C Data Receive register" hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C_ICSAR,I2C Slave Address register" hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Target address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C_ICDXR,I2C Data Transmit register" hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C_ICMDR,I2C Mode register" hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved" bitfld.long 0x24 15. "NACKMOD,No Acknowledge [NACK] mode. This bit is used to send an Acknowledge [ACK] or a No Acknowledge [NACK] to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE0:[default] Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL.." "0,1" bitfld.long 0x24 13. "STT,Start Condition [Master only mode]. This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN [IDLE Enable on5509. - [RW ]" "0,1" bitfld.long 0x24 11. "STP,Stop Condition [Master mode only]. This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST0:The I 2 C peripheral is in the'target' mode and clock is received from the'master' device. MST1:The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0,1" bitfld.long 0x24 9. "TRX,Transmitter. TRX0:The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX1:The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes [not.." "0,1" newline bitfld.long 0x24 8. "XA,Expanded Address. XA0:[default] 7-bit address mode [normal address mode]. XA1:10-bit address mode [expanded address mode] Please note that XA needs to be configured even if the I2C is in target mode." "0,1" bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back [in master transmit mode only]. This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after [[CPU freq/I2C freq]8] CPU cycles via.." "0,1" bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte [Master only mode]. The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001' regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Target in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb [excluding the acknowledge bit] of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C_ICIVR,I2C Interrupt Vector register" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY[011] RRDY[100] and XRDY[101]. Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C_ICEMDR,I2C Extended Mode register" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the target. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C_ICPSC,I2C Prescaler register" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset [IRS_=0]. The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C_ICPID1,I2C Peripheral ID register 1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - [RW ]" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - [RW ]" line.long 0x38 "I2C_ICPID2,I2C Peripheral ID register 2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - [RW ]" line.long 0x3C "I2C_ICDMAC,I2C DMA Control Register" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0,1" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0,1" group.long 0x48++0x1B line.long 0x0 "I2C_ICPFUNC,I2C Pin Function register" hexmask.long 0x0 1.--31. 1. "NU,Reserved." bitfld.long 0x0 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4 "I2C_ICPDIR,I2C Pin Direction register" hexmask.long 0x4 2.--31. 1. "NU,Reserved" bitfld.long 0x4 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x8 "I2C_ICPDIN,I2C Pin Data In register" hexmask.long 0x8 2.--31. 1. "NU,Reserved" bitfld.long 0x8 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - [RW ]" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x8 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - [RW ]" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0xC "I2C_ICPDOUT,I2C Pin Data Out register" hexmask.long 0xC 2.--31. 1. "NU,Reserved" bitfld.long 0xC 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0xC 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x10 "I2C_ICPDSET,I2C Pin Data Set register" hexmask.long 0x10 2.--31. 1. "NU,Reserved" bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x14 "I2C_ICPDCLR,I2C Pin Data Clear register" hexmask.long 0x14 2.--31. 1. "NU,Reserved" bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x18 "I2C_ICPDRV,I2C Pin Driver Mode Register" hexmask.long 0x18 2.--31. 1. "NU,Reserved" bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree "I2C2" base ad:0x52502000 group.long 0x0++0x3F line.long 0x0 "I2C_ICOAR,I2C Own Address register" hexmask.long.tbyte 0x0 10.--31. 1. "NU,Reserved" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C_ICIMR,I2C Interrupt Mask/Status register" hexmask.long 0x4 7.--31. 1. "NU,Reserved" bitfld.long 0x4 6. "AAS,Address As Target interrupt mask bit. Setting a'1' to this bit unmasks the Address As Target interrupt. Setting a'0' to this bit masks the Address As Target interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C_ICSTR,I2C Interrupt Status register" hexmask.long.tbyte 0x8 15.--31. 1. "NU2,Reserved" bitfld.long 0x8 14. "SDIR,Target Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a target receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C target is a transmitter. In DLB.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT 0:A No Acknowledge is not sent. NACKSNT 1:A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB0:The bus is free. BB1:The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register [ICRSR] is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register [ICXSR] is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Target. This bit is set to 1 by the device when it has recognized its own target address or an address of all [8] zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - [RW ]" "0,1" bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all [8] zeros [i.e. general call]. The AD0 bit is reset to 0 [default value] when a'start' or'stop' condition is detected. - [RW ]" "0,1" newline bitfld.long 0x8 6.--7. "NU1,Reserved" "0,1,2,3" bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by Reading ICIVR [as 110] or Writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register [ICXSR]. ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR [as 010].." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C_ICCLKL,I2C Clock Divider Low register" hexmask.long.word 0xC 16.--31. 1. "NU,Reserved" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x10 "I2C_ICCLKH,I2C Clock Divider High register" hexmask.long.word 0x10 16.--31. 1. "NU,Reserved" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x14 "I2C_ICCNT,I2C Data Count register" hexmask.long.word 0x14 16.--31. 1. "NU,Reserved" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified [STP=1]. . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C_ICDRR,I2C Data Receive register" hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C_ICSAR,I2C Slave Address register" hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Target address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C_ICDXR,I2C Data Transmit register" hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C_ICMDR,I2C Mode register" hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved" bitfld.long 0x24 15. "NACKMOD,No Acknowledge [NACK] mode. This bit is used to send an Acknowledge [ACK] or a No Acknowledge [NACK] to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE0:[default] Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL.." "0,1" bitfld.long 0x24 13. "STT,Start Condition [Master only mode]. This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN [IDLE Enable on5509. - [RW ]" "0,1" bitfld.long 0x24 11. "STP,Stop Condition [Master mode only]. This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST0:The I 2 C peripheral is in the'target' mode and clock is received from the'master' device. MST1:The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0,1" bitfld.long 0x24 9. "TRX,Transmitter. TRX0:The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX1:The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes [not.." "0,1" newline bitfld.long 0x24 8. "XA,Expanded Address. XA0:[default] 7-bit address mode [normal address mode]. XA1:10-bit address mode [expanded address mode] Please note that XA needs to be configured even if the I2C is in target mode." "0,1" bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back [in master transmit mode only]. This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after [[CPU freq/I2C freq]8] CPU cycles via.." "0,1" bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte [Master only mode]. The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001' regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Target in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb [excluding the acknowledge bit] of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C_ICIVR,I2C Interrupt Vector register" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY[011] RRDY[100] and XRDY[101]. Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C_ICEMDR,I2C Extended Mode register" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the target. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C_ICPSC,I2C Prescaler register" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset [IRS_=0]. The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C_ICPID1,I2C Peripheral ID register 1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - [RW ]" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - [RW ]" line.long 0x38 "I2C_ICPID2,I2C Peripheral ID register 2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - [RW ]" line.long 0x3C "I2C_ICDMAC,I2C DMA Control Register" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0,1" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0,1" group.long 0x48++0x1B line.long 0x0 "I2C_ICPFUNC,I2C Pin Function register" hexmask.long 0x0 1.--31. 1. "NU,Reserved." bitfld.long 0x0 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4 "I2C_ICPDIR,I2C Pin Direction register" hexmask.long 0x4 2.--31. 1. "NU,Reserved" bitfld.long 0x4 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x8 "I2C_ICPDIN,I2C Pin Data In register" hexmask.long 0x8 2.--31. 1. "NU,Reserved" bitfld.long 0x8 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - [RW ]" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x8 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - [RW ]" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0xC "I2C_ICPDOUT,I2C Pin Data Out register" hexmask.long 0xC 2.--31. 1. "NU,Reserved" bitfld.long 0xC 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0xC 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x10 "I2C_ICPDSET,I2C Pin Data Set register" hexmask.long 0x10 2.--31. 1. "NU,Reserved" bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x14 "I2C_ICPDCLR,I2C Pin Data Clear register" hexmask.long 0x14 2.--31. 1. "NU,Reserved" bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x18 "I2C_ICPDRV,I2C Pin Driver Mode Register" hexmask.long 0x18 2.--31. 1. "NU,Reserved" bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree "I2C3" base ad:0x52503000 group.long 0x0++0x3F line.long 0x0 "I2C_ICOAR,I2C Own Address register" hexmask.long.tbyte 0x0 10.--31. 1. "NU,Reserved" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C_ICIMR,I2C Interrupt Mask/Status register" hexmask.long 0x4 7.--31. 1. "NU,Reserved" bitfld.long 0x4 6. "AAS,Address As Target interrupt mask bit. Setting a'1' to this bit unmasks the Address As Target interrupt. Setting a'0' to this bit masks the Address As Target interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C_ICSTR,I2C Interrupt Status register" hexmask.long.tbyte 0x8 15.--31. 1. "NU2,Reserved" bitfld.long 0x8 14. "SDIR,Target Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a target receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C target is a transmitter. In DLB.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT 0:A No Acknowledge is not sent. NACKSNT 1:A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB0:The bus is free. BB1:The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register [ICRSR] is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register [ICXSR] is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Target. This bit is set to 1 by the device when it has recognized its own target address or an address of all [8] zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - [RW ]" "0,1" bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all [8] zeros [i.e. general call]. The AD0 bit is reset to 0 [default value] when a'start' or'stop' condition is detected. - [RW ]" "0,1" newline bitfld.long 0x8 6.--7. "NU1,Reserved" "0,1,2,3" bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by Reading ICIVR [as 110] or Writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register [ICXSR]. ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR [as 010].." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C_ICCLKL,I2C Clock Divider Low register" hexmask.long.word 0xC 16.--31. 1. "NU,Reserved" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x10 "I2C_ICCLKH,I2C Clock Divider High register" hexmask.long.word 0x10 16.--31. 1. "NU,Reserved" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset [IRS_=0]." line.long 0x14 "I2C_ICCNT,I2C Data Count register" hexmask.long.word 0x14 16.--31. 1. "NU,Reserved" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified [STP=1]. . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C_ICDRR,I2C Data Receive register" hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C_ICSAR,I2C Slave Address register" hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Target address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C_ICDXR,I2C Data Transmit register" hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C_ICMDR,I2C Mode register" hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved" bitfld.long 0x24 15. "NACKMOD,No Acknowledge [NACK] mode. This bit is used to send an Acknowledge [ACK] or a No Acknowledge [NACK] to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE0:[default] Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL.." "0,1" bitfld.long 0x24 13. "STT,Start Condition [Master only mode]. This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN [IDLE Enable on5509. - [RW ]" "0,1" bitfld.long 0x24 11. "STP,Stop Condition [Master mode only]. This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST0:The I 2 C peripheral is in the'target' mode and clock is received from the'master' device. MST1:The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0,1" bitfld.long 0x24 9. "TRX,Transmitter. TRX0:The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX1:The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes [not.." "0,1" newline bitfld.long 0x24 8. "XA,Expanded Address. XA0:[default] 7-bit address mode [normal address mode]. XA1:10-bit address mode [expanded address mode] Please note that XA needs to be configured even if the I2C is in target mode." "0,1" bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back [in master transmit mode only]. This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after [[CPU freq/I2C freq]8] CPU cycles via.." "0,1" bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte [Master only mode]. The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001' regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Target in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb [excluding the acknowledge bit] of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C_ICIVR,I2C Interrupt Vector register" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY[011] RRDY[100] and XRDY[101]. Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C_ICEMDR,I2C Extended Mode register" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the target. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C_ICPSC,I2C Prescaler register" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset [IRS_=0]. The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C_ICPID1,I2C Peripheral ID register 1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - [RW ]" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - [RW ]" line.long 0x38 "I2C_ICPID2,I2C Peripheral ID register 2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - [RW ]" line.long 0x3C "I2C_ICDMAC,I2C DMA Control Register" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - [RW ]" bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0,1" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0,1" group.long 0x48++0x1B line.long 0x0 "I2C_ICPFUNC,I2C Pin Function register" hexmask.long 0x0 1.--31. 1. "NU,Reserved." bitfld.long 0x0 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4 "I2C_ICPDIR,I2C Pin Direction register" hexmask.long 0x4 2.--31. 1. "NU,Reserved" bitfld.long 0x4 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x8 "I2C_ICPDIN,I2C Pin Data In register" hexmask.long 0x8 2.--31. 1. "NU,Reserved" bitfld.long 0x8 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - [RW ]" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x8 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - [RW ]" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0xC "I2C_ICPDOUT,I2C Pin Data Out register" hexmask.long 0xC 2.--31. 1. "NU,Reserved" bitfld.long 0xC 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0xC 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x10 "I2C_ICPDSET,I2C Pin Data Set register" hexmask.long 0x10 2.--31. 1. "NU,Reserved" bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x14 "I2C_ICPDCLR,I2C Pin Data Clear register" hexmask.long 0x14 2.--31. 1. "NU,Reserved" bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x18 "I2C_ICPDRV,I2C Pin Driver Mode Register" hexmask.long 0x18 2.--31. 1. "NU,Reserved" bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree.end tree "ICSSM0" base ad:0x0 tree "ICSSM0_ECC_AGGR" base ad:0x48100000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REV,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_VECTOR,ECC Vector Register." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_STAT,Misc Status." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_RESERVED_SVBUS_j,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1" bitfld.long 0x4 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1" bitfld.long 0x4 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1" newline bitfld.long 0x4 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1" bitfld.long 0x4 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1" bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1" bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1" newline bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1" bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1" bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1" bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1" newline bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1" bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1" bitfld.long 0x4 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1" bitfld.long 0x4 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1" newline bitfld.long 0x4 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1" bitfld.long 0x4 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1" bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1" bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1" newline bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1" bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1" bitfld.long 0x0 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1" bitfld.long 0x0 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1" newline bitfld.long 0x0 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1" bitfld.long 0x0 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end base ad:0x0 tree "ICSSM0_ICSSM" tree "ICSSM0_ICSSM_DRAM0_SLV_RAM" base ad:0x48000000 group.long 0x0++0x3 line.long 0x0 "ICSSM_DRAM0_SLV_RAM_RAM_REG_j,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "ICSSM0_ICSSM_DRAM1_SLV_RAM" base ad:0x48002000 group.long 0x0++0x3 line.long 0x0 "ICSSM_DRAM1_SLV_RAM_RAM_REG_j,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end base ad:0x0 tree "ICSSM0_ICSSM_PR1" tree "ICSSM0_ICSSM_PR1_CFG_SLV" base ad:0x48026000 rgroup.long 0x0++0x7 line.long 0x0 "ICSSM_PR1_CFG_SLV_PID_REG" hexmask.long 0x0 0.--31. 1. "ICSS_IDVER,Module ID field" line.long 0x4 "ICSSM_PR1_CFG_SLV_HWDIS_REG" hexmask.long.byte 0x4 0.--7. 1. "HWDIS,HW Disable Observation" group.long 0x8++0x17 line.long 0x0 "ICSSM_PR1_CFG_SLV_GPCFG0_REG" hexmask.long.byte 0x0 26.--29. 1. "PR1_PRU0_GP_MUX_SEL" rbitfld.long 0x0 25. "PRU0_GPO_SH1_SEL" "0,1" newline hexmask.long.byte 0x0 20.--24. 1. "PRU0_GPO_DIV1" hexmask.long.byte 0x0 15.--19. 1. "PRU0_GPO_DIV0" newline bitfld.long 0x0 14. "PRU0_GPO_MODE" "0,1" bitfld.long 0x0 13. "PRU0_GPI_SB" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "PRU0_GPI_DIV1" hexmask.long.byte 0x0 3.--7. 1. "PRU0_GPI_DIV0" newline bitfld.long 0x0 2. "PRU0_GPI_CLK_MODE" "0,1" bitfld.long 0x0 0.--1. "PRU0_GPI_MODE" "0,1,2,3" line.long 0x4 "ICSSM_PR1_CFG_SLV_GPCFG1_REG" hexmask.long.byte 0x4 26.--29. 1. "PR1_PRU1_GP_MUX_SEL" rbitfld.long 0x4 25. "PRU1_GPO_SH1_SEL" "0,1" newline hexmask.long.byte 0x4 20.--24. 1. "PRU1_GPO_DIV1" hexmask.long.byte 0x4 15.--19. 1. "PRU1_GPO_DIV0" newline bitfld.long 0x4 14. "PRU1_GPO_MODE" "0,1" bitfld.long 0x4 13. "PRU1_GPI_SB" "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "PRU1_GPI_DIV1" hexmask.long.byte 0x4 3.--7. 1. "PRU1_GPI_DIV0" newline bitfld.long 0x4 2. "PRU1_GPI_CLK_MODE" "0,1" bitfld.long 0x4 0.--1. "PRU1_GPI_MODE" "0,1,2,3" line.long 0x8 "ICSSM_PR1_CFG_SLV_CGR_REG" bitfld.long 0x8 31. "ICSS_STOP_ACK" "0,1" rbitfld.long 0x8 30. "ICSS_STOP_REQ" "0,1" newline bitfld.long 0x8 29. "ICSS_PWR_IDLE" "0,1" bitfld.long 0x8 21. "BOTTOM_HALF_CLK_GATE_EN" "0,1" newline bitfld.long 0x8 20. "TOP_HALF_CLK_GATE_EN" "0,1" bitfld.long 0x8 19. "AUTO_SLICE1_CLK_GATE_EN" "0,1" newline bitfld.long 0x8 18. "AUTO_SLICE0_CLK_GATE_EN" "0,1" bitfld.long 0x8 17. "IEP_CLK_EN" "0,1" newline rbitfld.long 0x8 16. "IEP_CLK_STOP_ACK" "0,1" bitfld.long 0x8 15. "IEP_CLK_STOP_REQ" "0,1" newline bitfld.long 0x8 14. "ECAP_CLK_EN" "0,1" rbitfld.long 0x8 13. "ECAP_CLK_STOP_ACK" "0,1" newline bitfld.long 0x8 12. "ECAP_CLK_STOP_REQ" "0,1" bitfld.long 0x8 11. "UART_CLK_EN" "0,1" newline rbitfld.long 0x8 10. "UART_CLK_STOP_ACK" "0,1" bitfld.long 0x8 9. "UART_CLK_STOP_REQ" "0,1" newline bitfld.long 0x8 8. "INTC_CLK_EN" "0,1" rbitfld.long 0x8 7. "INTC_CLK_STOP_ACK" "0,1" newline bitfld.long 0x8 6. "INTC_CLK_STOP_REQ" "0,1" line.long 0xC "ICSSM_PR1_CFG_SLV_GPECFG0_REG" bitfld.long 0xC 17. "PRU0_GPO_SHIFT_CLK_DONE" "0,1" bitfld.long 0xC 16. "PRU0_GPO_SHIFT_CLK_HIGH" "0,1" newline hexmask.long.byte 0xC 8.--15. 1. "PRU0_GPO_SHIFT_CNT" bitfld.long 0xC 6. "PRU0_GPO_SHIFT_GP_EN" "0,1" newline bitfld.long 0xC 5. "PRU0_GPO_SHIFT_CLK_FREE" "0,1" bitfld.long 0xC 4. "PRU0_GPO_SHIFT_SWAP" "0,1" newline bitfld.long 0xC 1. "PRU0_GPI_SHIFT_EN" "0,1" bitfld.long 0xC 0. "PRU0_GPI_SB_P" "0,1" line.long 0x10 "ICSSM_PR1_CFG_SLV_GPECFG1_REG" bitfld.long 0x10 17. "PRU1_GPO_SHIFT_CLK_DONE" "0,1" bitfld.long 0x10 16. "PRU1_GPO_SHIFT_CLK_HIGH" "0,1" newline hexmask.long.byte 0x10 8.--15. 1. "PRU1_GPO_SHIFT_CNT" bitfld.long 0x10 6. "PRU1_GPO_SHIFT_GP_EN" "0,1" newline bitfld.long 0x10 5. "PRU1_GPO_SHIFT_CLK_FREE" "0,1" bitfld.long 0x10 4. "PRU1_GPO_SHIFT_SWAP" "0,1" newline bitfld.long 0x10 1. "PRU1_GPI_SHIFT_EN" "0,1" bitfld.long 0x10 0. "PRU1_GPI_SB_P" "0,1" line.long 0x14 "ICSSM_PR1_CFG_SLV_RESET_ISO_REG" bitfld.long 0x14 2. "RESET_ISO_EDGE" "0,1" bitfld.long 0x14 1. "RESET_ISO_ACK" "0,1" newline bitfld.long 0x14 0. "RESET_ISO_REQ" "0,1" group.long 0x2C++0xAF line.long 0x0 "ICSSM_PR1_CFG_SLV_MII_RT_REG" bitfld.long 0x0 0. "MII_RT_EVENT_EN" "0,1" line.long 0x4 "ICSSM_PR1_CFG_SLV_IEPCLK_REG" bitfld.long 0x4 1. "IEP1_SLV_EN" "0,1" bitfld.long 0x4 0. "IEP_OCP_CLK_EN" "0,1" line.long 0x8 "ICSSM_PR1_CFG_SLV_SPP_REG" bitfld.long 0x8 3. "RTU_XFR_SHIFT_EN" "0,1" bitfld.long 0x8 2. "XFR_BYTE_SHIFT_EN" "0,1" newline bitfld.long 0x8 1. "XFR_SHIFT_EN" "0,1" bitfld.long 0x8 0. "PRU1_PAD_HP_EN" "0,1" line.long 0xC "ICSSM_PR1_CFG_SLV_SPIN_CFG_REG" bitfld.long 0xC 0. "SPIN_CLOCK_TX_PRU_EN" "0,1" line.long 0x10 "ICSSM_PR1_CFG_SLV_CORE_SYNC_REG" bitfld.long 0x10 0. "CORE_VBUSP_SYNC_EN" "0,1" line.long 0x14 "ICSSM_PR1_CFG_SLV_SA_MX_REG" bitfld.long 0x14 16. "PWM_EFC_EN" "0,1" bitfld.long 0x14 10.--11. "PWM3_REMAP_EN" "0,1,2,3" newline bitfld.long 0x14 8.--9. "PWM0_REMAP_EN" "0,1,2,3" hexmask.long.byte 0x14 0.--7. 1. "SA_MUX_SEL" line.long 0x18 "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_DIV_REG" hexmask.long.byte 0x18 24.--31. 1. "PRU0_SD_MAN_REC_CLK_PERIOD" rbitfld.long 0x18 16. "PRU0_SD_MAN_CLK_CAL_DONE" "0,1" newline rbitfld.long 0x18 15. "PRU0_SD_MAN_STATUS" "0,1" hexmask.long.byte 0x18 11.--14. 1. "PRU0_SD_CH_SEL" newline bitfld.long 0x18 10. "PRU0_SD_MAN_NV_DATA_EN" "0,1" bitfld.long 0x18 9. "PRU0_SD_MAN_EN" "0,1" newline bitfld.long 0x18 8. "PRU0_SD_SHARE_EN" "0,1" line.long 0x1C "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG0" bitfld.long 0x1C 22. "PRU0_FD_ZERO_MAX_0" "0,1" hexmask.long.byte 0x1C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_0" newline bitfld.long 0x1C 16. "PRU0_FD_ZERO_MIN_0" "0,1" hexmask.long.byte 0x1C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_0" newline bitfld.long 0x1C 4.--5. "PRU0_SD_ACC_SEL0" "0,1,2,3" bitfld.long 0x1C 2. "PRU0_SD_CLK_INV0" "0,1" newline bitfld.long 0x1C 0.--1. "PRU0_SD_CLK_SEL0" "0,1,2,3" line.long 0x20 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG0" bitfld.long 0x20 23. "PRU0_FD_EN_0" "0,1" bitfld.long 0x20 22. "PRU0_FD_ONE_MAX_0" "0,1" newline hexmask.long.byte 0x20 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_0" bitfld.long 0x20 16. "PRU0_FD_ONE_MIN_0" "0,1" newline hexmask.long.byte 0x20 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_0" bitfld.long 0x20 8.--10. "PRU0_FD_WINDOW_SIZE_0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0" line.long 0x24 "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG1" bitfld.long 0x24 22. "PRU0_FD_ZERO_MAX_1" "0,1" hexmask.long.byte 0x24 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_1" newline bitfld.long 0x24 16. "PRU0_FD_ZERO_MIN_1" "0,1" hexmask.long.byte 0x24 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_1" newline bitfld.long 0x24 4.--5. "PRU0_SD_ACC_SEL1" "0,1,2,3" bitfld.long 0x24 2. "PRU0_SD_CLK_INV1" "0,1" newline bitfld.long 0x24 0.--1. "PRU0_SD_CLK_SEL1" "0,1,2,3" line.long 0x28 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG1" bitfld.long 0x28 23. "PRU0_FD_EN_1" "0,1" bitfld.long 0x28 22. "PRU0_FD_ONE_MAX_1" "0,1" newline hexmask.long.byte 0x28 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_1" bitfld.long 0x28 16. "PRU0_FD_ONE_MIN_1" "0,1" newline hexmask.long.byte 0x28 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_1" bitfld.long 0x28 8.--10. "PRU0_FD_WINDOW_SIZE_1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "PRU0_SD_SAMPLE_SIZE1" line.long 0x2C "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG2" bitfld.long 0x2C 22. "PRU0_FD_ZERO_MAX_2" "0,1" hexmask.long.byte 0x2C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_2" newline bitfld.long 0x2C 16. "PRU0_FD_ZERO_MIN_2" "0,1" hexmask.long.byte 0x2C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_2" newline bitfld.long 0x2C 4.--5. "PRU0_SD_ACC_SEL2" "0,1,2,3" bitfld.long 0x2C 2. "PRU0_SD_CLK_INV2" "0,1" newline bitfld.long 0x2C 0.--1. "PRU0_SD_CLK_SEL2" "0,1,2,3" line.long 0x30 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG2" bitfld.long 0x30 23. "PRU0_FD_EN_2" "0,1" bitfld.long 0x30 22. "PRU0_FD_ONE_MAX_2" "0,1" newline hexmask.long.byte 0x30 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_2" bitfld.long 0x30 16. "PRU0_FD_ONE_MIN_2" "0,1" newline hexmask.long.byte 0x30 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_2" bitfld.long 0x30 8.--10. "PRU0_FD_WINDOW_SIZE_2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x30 0.--7. 1. "PRU0_SD_SAMPLE_SIZE2" line.long 0x34 "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG3" bitfld.long 0x34 22. "PRU0_FD_ZERO_MAX_3" "0,1" hexmask.long.byte 0x34 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_3" newline bitfld.long 0x34 16. "PRU0_FD_ZERO_MIN_3" "0,1" hexmask.long.byte 0x34 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_3" newline bitfld.long 0x34 4.--5. "PRU0_SD_ACC_SEL3" "0,1,2,3" bitfld.long 0x34 2. "PRU0_SD_CLK_INV3" "0,1" newline bitfld.long 0x34 0.--1. "PRU0_SD_CLK_SEL3" "0,1,2,3" line.long 0x38 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG3" bitfld.long 0x38 23. "PRU0_FD_EN_3" "0,1" bitfld.long 0x38 22. "PRU0_FD_ONE_MAX_3" "0,1" newline hexmask.long.byte 0x38 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_3" bitfld.long 0x38 16. "PRU0_FD_ONE_MIN_3" "0,1" newline hexmask.long.byte 0x38 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_3" bitfld.long 0x38 8.--10. "PRU0_FD_WINDOW_SIZE_3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x38 0.--7. 1. "PRU0_SD_SAMPLE_SIZE3" line.long 0x3C "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG4" bitfld.long 0x3C 22. "PRU0_FD_ZERO_MAX_4" "0,1" hexmask.long.byte 0x3C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_4" newline bitfld.long 0x3C 16. "PRU0_FD_ZERO_MIN_4" "0,1" hexmask.long.byte 0x3C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_4" newline bitfld.long 0x3C 4.--5. "PRU0_SD_ACC_SEL4" "0,1,2,3" bitfld.long 0x3C 2. "PRU0_SD_CLK_INV4" "0,1" newline bitfld.long 0x3C 0.--1. "PRU0_SD_CLK_SEL4" "0,1,2,3" line.long 0x40 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG4" bitfld.long 0x40 23. "PRU0_FD_EN_4" "0,1" bitfld.long 0x40 22. "PRU0_FD_ONE_MAX_4" "0,1" newline hexmask.long.byte 0x40 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_4" bitfld.long 0x40 16. "PRU0_FD_ONE_MIN_4" "0,1" newline hexmask.long.byte 0x40 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_4" bitfld.long 0x40 8.--10. "PRU0_FD_WINDOW_SIZE_4" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 0.--7. 1. "PRU0_SD_SAMPLE_SIZE4" line.long 0x44 "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG5" bitfld.long 0x44 22. "PRU0_FD_ZERO_MAX_5" "0,1" hexmask.long.byte 0x44 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_5" newline bitfld.long 0x44 16. "PRU0_FD_ZERO_MIN_5" "0,1" hexmask.long.byte 0x44 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_5" newline bitfld.long 0x44 4.--5. "PRU0_SD_ACC_SEL5" "0,1,2,3" bitfld.long 0x44 2. "PRU0_SD_CLK_INV5" "0,1" newline bitfld.long 0x44 0.--1. "PRU0_SD_CLK_SEL5" "0,1,2,3" line.long 0x48 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG5" bitfld.long 0x48 23. "PRU0_FD_EN_5" "0,1" bitfld.long 0x48 22. "PRU0_FD_ONE_MAX_5" "0,1" newline hexmask.long.byte 0x48 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_5" bitfld.long 0x48 16. "PRU0_FD_ONE_MIN_5" "0,1" newline hexmask.long.byte 0x48 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_5" bitfld.long 0x48 8.--10. "PRU0_FD_WINDOW_SIZE_5" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x48 0.--7. 1. "PRU0_SD_SAMPLE_SIZE5" line.long 0x4C "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG6" bitfld.long 0x4C 22. "PRU0_FD_ZERO_MAX_6" "0,1" hexmask.long.byte 0x4C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_6" newline bitfld.long 0x4C 16. "PRU0_FD_ZERO_MIN_6" "0,1" hexmask.long.byte 0x4C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_6" newline bitfld.long 0x4C 4.--5. "PRU0_SD_ACC_SEL6" "0,1,2,3" bitfld.long 0x4C 2. "PRU0_SD_CLK_INV6" "0,1" newline bitfld.long 0x4C 0.--1. "PRU0_SD_CLK_SEL6" "0,1,2,3" line.long 0x50 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG6" bitfld.long 0x50 23. "PRU0_FD_EN_6" "0,1" bitfld.long 0x50 22. "PRU0_FD_ONE_MAX_6" "0,1" newline hexmask.long.byte 0x50 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_6" bitfld.long 0x50 16. "PRU0_FD_ONE_MIN_6" "0,1" newline hexmask.long.byte 0x50 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_6" bitfld.long 0x50 8.--10. "PRU0_FD_WINDOW_SIZE_6" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x50 0.--7. 1. "PRU0_SD_SAMPLE_SIZE6" line.long 0x54 "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG7" bitfld.long 0x54 22. "PRU0_FD_ZERO_MAX_7" "0,1" hexmask.long.byte 0x54 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_7" newline bitfld.long 0x54 16. "PRU0_FD_ZERO_MIN_7" "0,1" hexmask.long.byte 0x54 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_7" newline bitfld.long 0x54 4.--5. "PRU0_SD_ACC_SEL7" "0,1,2,3" bitfld.long 0x54 2. "PRU0_SD_CLK_INV7" "0,1" newline bitfld.long 0x54 0.--1. "PRU0_SD_CLK_SEL7" "0,1,2,3" line.long 0x58 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG7" bitfld.long 0x58 23. "PRU0_FD_EN_7" "0,1" bitfld.long 0x58 22. "PRU0_FD_ONE_MAX_7" "0,1" newline hexmask.long.byte 0x58 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_7" bitfld.long 0x58 16. "PRU0_FD_ONE_MIN_7" "0,1" newline hexmask.long.byte 0x58 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_7" bitfld.long 0x58 8.--10. "PRU0_FD_WINDOW_SIZE_7" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 0.--7. 1. "PRU0_SD_SAMPLE_SIZE7" line.long 0x5C "ICSSM_PR1_CFG_SLV_PRU0_SD_CLK_SEL_REG8" bitfld.long 0x5C 22. "PRU0_FD_ZERO_MAX_8" "0,1" hexmask.long.byte 0x5C 17.--21. 1. "PRU0_FD_ZERO_MAX_LIMIT_8" newline bitfld.long 0x5C 16. "PRU0_FD_ZERO_MIN_8" "0,1" hexmask.long.byte 0x5C 11.--15. 1. "PRU0_FD_ZERO_MIN_LIMIT_8" newline bitfld.long 0x5C 4.--5. "PRU0_SD_ACC_SEL8" "0,1,2,3" bitfld.long 0x5C 2. "PRU0_SD_CLK_INV8" "0,1" newline bitfld.long 0x5C 0.--1. "PRU0_SD_CLK_SEL8" "0,1,2,3" line.long 0x60 "ICSSM_PR1_CFG_SLV_PRU0_SD_SAMPLE_SIZE_REG8" bitfld.long 0x60 23. "PRU0_FD_EN_8" "0,1" bitfld.long 0x60 22. "PRU0_FD_ONE_MAX_8" "0,1" newline hexmask.long.byte 0x60 17.--21. 1. "PRU0_FD_ONE_MAX_LIMIT_8" bitfld.long 0x60 16. "PRU0_FD_ONE_MIN_8" "0,1" newline hexmask.long.byte 0x60 11.--15. 1. "PRU0_FD_ONE_MIN_LIMIT_8" bitfld.long 0x60 8.--10. "PRU0_FD_WINDOW_SIZE_8" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x60 0.--7. 1. "PRU0_SD_SAMPLE_SIZE8" line.long 0x64 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_DIV_REG" hexmask.long.byte 0x64 24.--31. 1. "PRU1_SD_MAN_REC_CLK_PERIOD" rbitfld.long 0x64 16. "PRU1_SD_MAN_CLK_CAL_DONE" "0,1" newline rbitfld.long 0x64 15. "PRU1_SD_MAN_STATUS" "0,1" hexmask.long.byte 0x64 11.--14. 1. "PRU1_SD_CH_SEL" newline bitfld.long 0x64 10. "PRU1_SD_MAN_NV_DATA_EN" "0,1" bitfld.long 0x64 9. "PRU1_SD_MAN_EN" "0,1" newline bitfld.long 0x64 8. "PRU1_SD_SHARE_EN" "0,1" line.long 0x68 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG0" bitfld.long 0x68 22. "PRU1_FD_ZERO_MAX_0" "0,1" hexmask.long.byte 0x68 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_0" newline bitfld.long 0x68 16. "PRU1_FD_ZERO_MIN_0" "0,1" hexmask.long.byte 0x68 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_0" newline bitfld.long 0x68 4.--5. "PRU1_SD_ACC_SEL0" "0,1,2,3" bitfld.long 0x68 2. "PRU1_SD_CLK_INV0" "0,1" newline bitfld.long 0x68 0.--1. "PRU1_SD_CLK_SEL0" "0,1,2,3" line.long 0x6C "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG0" bitfld.long 0x6C 23. "PRU1_FD_EN_0" "0,1" bitfld.long 0x6C 22. "PRU1_FD_ONE_MAX_0" "0,1" newline hexmask.long.byte 0x6C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_0" bitfld.long 0x6C 16. "PRU1_FD_ONE_MIN_0" "0,1" newline hexmask.long.byte 0x6C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_0" bitfld.long 0x6C 8.--10. "PRU1_FD_WINDOW_SIZE_0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x6C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0" line.long 0x70 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG1" bitfld.long 0x70 22. "PRU1_FD_ZERO_MAX_1" "0,1" hexmask.long.byte 0x70 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_1" newline bitfld.long 0x70 16. "PRU1_FD_ZERO_MIN_1" "0,1" hexmask.long.byte 0x70 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_1" newline bitfld.long 0x70 4.--5. "PRU1_SD_ACC_SEL1" "0,1,2,3" bitfld.long 0x70 2. "PRU1_SD_CLK_INV1" "0,1" newline bitfld.long 0x70 0.--1. "PRU1_SD_CLK_SEL1" "0,1,2,3" line.long 0x74 "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG1" bitfld.long 0x74 23. "PRU1_FD_EN_1" "0,1" bitfld.long 0x74 22. "PRU1_FD_ONE_MAX_1" "0,1" newline hexmask.long.byte 0x74 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_1" bitfld.long 0x74 16. "PRU1_FD_ONE_MIN_1" "0,1" newline hexmask.long.byte 0x74 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_1" bitfld.long 0x74 8.--10. "PRU1_FD_WINDOW_SIZE_1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x74 0.--7. 1. "PRU1_SD_SAMPLE_SIZE1" line.long 0x78 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG2" bitfld.long 0x78 22. "PRU1_FD_ZERO_MAX_2" "0,1" hexmask.long.byte 0x78 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_2" newline bitfld.long 0x78 16. "PRU1_FD_ZERO_MIN_2" "0,1" hexmask.long.byte 0x78 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_2" newline bitfld.long 0x78 4.--5. "PRU1_SD_ACC_SEL2" "0,1,2,3" bitfld.long 0x78 2. "PRU1_SD_CLK_INV2" "0,1" newline bitfld.long 0x78 0.--1. "PRU1_SD_CLK_SEL2" "0,1,2,3" line.long 0x7C "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG2" bitfld.long 0x7C 23. "PRU1_FD_EN_2" "0,1" bitfld.long 0x7C 22. "PRU1_FD_ONE_MAX_2" "0,1" newline hexmask.long.byte 0x7C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_2" bitfld.long 0x7C 16. "PRU1_FD_ONE_MIN_2" "0,1" newline hexmask.long.byte 0x7C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_2" bitfld.long 0x7C 8.--10. "PRU1_FD_WINDOW_SIZE_2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x7C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE2" line.long 0x80 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG3" bitfld.long 0x80 22. "PRU1_FD_ZERO_MAX_3" "0,1" hexmask.long.byte 0x80 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_3" newline bitfld.long 0x80 16. "PRU1_FD_ZERO_MIN_3" "0,1" hexmask.long.byte 0x80 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_3" newline bitfld.long 0x80 4.--5. "PRU1_SD_ACC_SEL3" "0,1,2,3" bitfld.long 0x80 2. "PRU1_SD_CLK_INV3" "0,1" newline bitfld.long 0x80 0.--1. "PRU1_SD_CLK_SEL3" "0,1,2,3" line.long 0x84 "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG3" bitfld.long 0x84 23. "PRU1_FD_EN_3" "0,1" bitfld.long 0x84 22. "PRU1_FD_ONE_MAX_3" "0,1" newline hexmask.long.byte 0x84 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_3" bitfld.long 0x84 16. "PRU1_FD_ONE_MIN_3" "0,1" newline hexmask.long.byte 0x84 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_3" bitfld.long 0x84 8.--10. "PRU1_FD_WINDOW_SIZE_3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x84 0.--7. 1. "PRU1_SD_SAMPLE_SIZE3" line.long 0x88 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG4" bitfld.long 0x88 22. "PRU1_FD_ZERO_MAX_4" "0,1" hexmask.long.byte 0x88 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_4" newline bitfld.long 0x88 16. "PRU1_FD_ZERO_MIN_4" "0,1" hexmask.long.byte 0x88 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_4" newline bitfld.long 0x88 4.--5. "PRU1_SD_ACC_SEL4" "0,1,2,3" bitfld.long 0x88 2. "PRU1_SD_CLK_INV4" "0,1" newline bitfld.long 0x88 0.--1. "PRU1_SD_CLK_SEL4" "0,1,2,3" line.long 0x8C "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG4" bitfld.long 0x8C 23. "PRU1_FD_EN_4" "0,1" bitfld.long 0x8C 22. "PRU1_FD_ONE_MAX_4" "0,1" newline hexmask.long.byte 0x8C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_4" bitfld.long 0x8C 16. "PRU1_FD_ONE_MIN_4" "0,1" newline hexmask.long.byte 0x8C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_4" bitfld.long 0x8C 8.--10. "PRU1_FD_WINDOW_SIZE_4" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE4" line.long 0x90 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG5" bitfld.long 0x90 22. "PRU1_FD_ZERO_MAX_5" "0,1" hexmask.long.byte 0x90 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_5" newline bitfld.long 0x90 16. "PRU1_FD_ZERO_MIN_5" "0,1" hexmask.long.byte 0x90 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_5" newline bitfld.long 0x90 4.--5. "PRU1_SD_ACC_SEL5" "0,1,2,3" bitfld.long 0x90 2. "PRU1_SD_CLK_INV5" "0,1" newline bitfld.long 0x90 0.--1. "PRU1_SD_CLK_SEL5" "0,1,2,3" line.long 0x94 "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG5" bitfld.long 0x94 23. "PRU1_FD_EN_5" "0,1" bitfld.long 0x94 22. "PRU1_FD_ONE_MAX_5" "0,1" newline hexmask.long.byte 0x94 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_5" bitfld.long 0x94 16. "PRU1_FD_ONE_MIN_5" "0,1" newline hexmask.long.byte 0x94 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_5" bitfld.long 0x94 8.--10. "PRU1_FD_WINDOW_SIZE_5" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x94 0.--7. 1. "PRU1_SD_SAMPLE_SIZE5" line.long 0x98 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG6" bitfld.long 0x98 22. "PRU1_FD_ZERO_MAX_6" "0,1" hexmask.long.byte 0x98 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_6" newline bitfld.long 0x98 16. "PRU1_FD_ZERO_MIN_6" "0,1" hexmask.long.byte 0x98 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_6" newline bitfld.long 0x98 4.--5. "PRU1_SD_ACC_SEL6" "0,1,2,3" bitfld.long 0x98 2. "PRU1_SD_CLK_INV6" "0,1" newline bitfld.long 0x98 0.--1. "PRU1_SD_CLK_SEL6" "0,1,2,3" line.long 0x9C "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG6" bitfld.long 0x9C 23. "PRU1_FD_EN_6" "0,1" bitfld.long 0x9C 22. "PRU1_FD_ONE_MAX_6" "0,1" newline hexmask.long.byte 0x9C 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_6" bitfld.long 0x9C 16. "PRU1_FD_ONE_MIN_6" "0,1" newline hexmask.long.byte 0x9C 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_6" bitfld.long 0x9C 8.--10. "PRU1_FD_WINDOW_SIZE_6" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x9C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE6" line.long 0xA0 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG7" bitfld.long 0xA0 22. "PRU1_FD_ZERO_MAX_7" "0,1" hexmask.long.byte 0xA0 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_7" newline bitfld.long 0xA0 16. "PRU1_FD_ZERO_MIN_7" "0,1" hexmask.long.byte 0xA0 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_7" newline bitfld.long 0xA0 4.--5. "PRU1_SD_ACC_SEL7" "0,1,2,3" bitfld.long 0xA0 2. "PRU1_SD_CLK_INV7" "0,1" newline bitfld.long 0xA0 0.--1. "PRU1_SD_CLK_SEL7" "0,1,2,3" line.long 0xA4 "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG7" bitfld.long 0xA4 23. "PRU1_FD_EN_7" "0,1" bitfld.long 0xA4 22. "PRU1_FD_ONE_MAX_7" "0,1" newline hexmask.long.byte 0xA4 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_7" bitfld.long 0xA4 16. "PRU1_FD_ONE_MIN_7" "0,1" newline hexmask.long.byte 0xA4 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_7" bitfld.long 0xA4 8.--10. "PRU1_FD_WINDOW_SIZE_7" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA4 0.--7. 1. "PRU1_SD_SAMPLE_SIZE7" line.long 0xA8 "ICSSM_PR1_CFG_SLV_PRU1_SD_CLK_SEL_REG8" bitfld.long 0xA8 22. "PRU1_FD_ZERO_MAX_8" "0,1" hexmask.long.byte 0xA8 17.--21. 1. "PRU1_FD_ZERO_MAX_LIMIT_8" newline bitfld.long 0xA8 16. "PRU1_FD_ZERO_MIN_8" "0,1" hexmask.long.byte 0xA8 11.--15. 1. "PRU1_FD_ZERO_MIN_LIMIT_8" newline bitfld.long 0xA8 4.--5. "PRU1_SD_ACC_SEL8" "0,1,2,3" bitfld.long 0xA8 2. "PRU1_SD_CLK_INV8" "0,1" newline bitfld.long 0xA8 0.--1. "PRU1_SD_CLK_SEL8" "0,1,2,3" line.long 0xAC "ICSSM_PR1_CFG_SLV_PRU1_SD_SAMPLE_SIZE_REG8" bitfld.long 0xAC 23. "PRU1_FD_EN_8" "0,1" bitfld.long 0xAC 22. "PRU1_FD_ONE_MAX_8" "0,1" newline hexmask.long.byte 0xAC 17.--21. 1. "PRU1_FD_ONE_MAX_LIMIT_8" bitfld.long 0xAC 16. "PRU1_FD_ONE_MIN_8" "0,1" newline hexmask.long.byte 0xAC 11.--15. 1. "PRU1_FD_ONE_MIN_LIMIT_8" bitfld.long 0xAC 8.--10. "PRU1_FD_WINDOW_SIZE_8" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xAC 0.--7. 1. "PRU1_SD_SAMPLE_SIZE8" group.long 0xE0++0x3F line.long 0x0 "ICSSM_PR1_CFG_SLV_PRU0_ED_RX_CFG_REG" hexmask.long.word 0x0 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR" bitfld.long 0x0 15. "PRU0_ED_RX_DIV_FACTOR_FRAC" "0,1" newline bitfld.long 0x0 4. "PRU0_ED_RX_CLK_SEL" "0,1" bitfld.long 0x0 3. "PRU0_ED_RX_SB_POL" "0,1" newline bitfld.long 0x0 0.--2. "PRU0_ED_RX_SAMPLE_SIZE" "0,1,2,3,4,5,6,7" line.long 0x4 "ICSSM_PR1_CFG_SLV_PRU0_ED_TX_CFG_REG" hexmask.long.word 0x4 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR" bitfld.long 0x4 15. "PRU0_ED_TX_DIV_FACTOR_FRAC" "0,1" newline bitfld.long 0x4 11. "PRU0_ENDAT_SHARE_EN" "0,1" rbitfld.long 0x4 10. "PRU0_ENDAT2_CLK_SYNC" "0,1" newline rbitfld.long 0x4 9. "PRU0_ENDAT1_CLK_SYNC" "0,1" rbitfld.long 0x4 8. "PRU0_ENDAT0_CLK_SYNC" "0,1" newline rbitfld.long 0x4 7. "PRU0_ED_BUSY_2" "0,1" rbitfld.long 0x4 6. "PRU0_ED_BUSY_1" "0,1" newline rbitfld.long 0x4 5. "PRU0_ED_BUSY_0" "0,1" bitfld.long 0x4 4. "PRU0_ED_TX_CLK_SEL" "0,1" line.long 0x8 "ICSSM_PR1_CFG_SLV_PRU0_ED_CH0_CFG0_REG" bitfld.long 0x8 31. "PRU0_ED_TX_FIFO_SWAP_BITS0" "0,1" bitfld.long 0x8 30. "PRU0_ED_SW_CLK_OUT0" "0,1" newline bitfld.long 0x8 29. "PRU0_ED_CLK_OUT_OVR_EN0" "0,1" rbitfld.long 0x8 28. "PRU0_ED_RX_SNOOP0" "0,1" newline hexmask.long.word 0x8 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0" hexmask.long.byte 0x8 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE0" newline hexmask.long.word 0x8 0.--10. 1. "PRU0_ED_TX_WDLY0" line.long 0xC "ICSSM_PR1_CFG_SLV_PRU0_ED_CH0_CFG1_REG" hexmask.long.word 0xC 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0" hexmask.long.word 0xC 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0" line.long 0x10 "ICSSM_PR1_CFG_SLV_PRU0_ED_CH1_CFG0_REG" bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1" "0,1" bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1" "0,1" newline bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1" "0,1" rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1" "0,1" newline hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1" hexmask.long.byte 0x10 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE1" newline hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1" line.long 0x14 "ICSSM_PR1_CFG_SLV_PRU0_ED_CH1_CFG1_REG" hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1" hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1" line.long 0x18 "ICSSM_PR1_CFG_SLV_PRU0_ED_CH2_CFG0_REG" bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2" "0,1" bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2" "0,1" newline bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2" "0,1" rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2" "0,1" newline hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2" hexmask.long.byte 0x18 11.--15. 1. "PRU0_ED_TX_FRAME_SIZE2" newline hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2" line.long 0x1C "ICSSM_PR1_CFG_SLV_PRU0_ED_CH2_CFG1_REG" hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2" hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2" line.long 0x20 "ICSSM_PR1_CFG_SLV_PRU1_ED_RX_CFG_REG" hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR" bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC" "0,1" newline bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL" "0,1" bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL" "0,1" newline bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE" "0,1,2,3,4,5,6,7" line.long 0x24 "ICSSM_PR1_CFG_SLV_PRU1_ED_TX_CFG_REG" hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR" bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC" "0,1" newline bitfld.long 0x24 11. "PRU1_ENDAT_SHARE_EN" "0,1" rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC" "0,1" newline rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC" "0,1" rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC" "0,1" newline rbitfld.long 0x24 7. "PRU1_ED_BUSY_2" "0,1" rbitfld.long 0x24 6. "PRU1_ED_BUSY_1" "0,1" newline rbitfld.long 0x24 5. "PRU1_ED_BUSY_0" "0,1" bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL" "0,1" line.long 0x28 "ICSSM_PR1_CFG_SLV_PRU1_ED_CH0_CFG0_REG" bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0" "0,1" bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0" "0,1" newline bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0" "0,1" rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0" "0,1" newline hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0" hexmask.long.byte 0x28 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE0" newline hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0" line.long 0x2C "ICSSM_PR1_CFG_SLV_PRU1_ED_CH0_CFG1_REG" hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0" hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0" line.long 0x30 "ICSSM_PR1_CFG_SLV_PRU1_ED_CH1_CFG0_REG" bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1" "0,1" bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1" "0,1" newline bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1" "0,1" rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1" "0,1" newline hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1" hexmask.long.byte 0x30 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE1" newline hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1" line.long 0x34 "ICSSM_PR1_CFG_SLV_PRU1_ED_CH1_CFG1_REG" hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1" hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1" line.long 0x38 "ICSSM_PR1_CFG_SLV_PRU1_ED_CH2_CFG0_REG" bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2" "0,1" bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2" "0,1" newline bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2" "0,1" rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2" "0,1" newline hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2" hexmask.long.byte 0x38 11.--15. 1. "PRU1_ED_TX_FRAME_SIZE2" newline hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2" line.long 0x3C "ICSSM_PR1_CFG_SLV_PRU1_ED_CH2_CFG1_REG" hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2" hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2" group.long 0x124++0x3 line.long 0x0 "ICSSM_PR1_CFG_SLV_RTU0_POKE_EN0_REG" group.long 0x12C++0x6B line.long 0x0 "ICSSM_PR1_CFG_SLV_RTU1_POKE_EN0_REG" line.long 0x4 "ICSSM_PR1_CFG_SLV_PWM0" line.long 0x8 "ICSSM_PR1_CFG_SLV_PWM1" line.long 0xC "ICSSM_PR1_CFG_SLV_PWM2" line.long 0x10 "ICSSM_PR1_CFG_SLV_PWM3" line.long 0x14 "ICSSM_PR1_CFG_SLV_PWM0_0" line.long 0x18 "ICSSM_PR1_CFG_SLV_PWM0_1" line.long 0x1C "ICSSM_PR1_CFG_SLV_PWM0_2" line.long 0x20 "ICSSM_PR1_CFG_SLV_PWM1_0" line.long 0x24 "ICSSM_PR1_CFG_SLV_PWM1_1" line.long 0x28 "ICSSM_PR1_CFG_SLV_PWM1_2" line.long 0x2C "ICSSM_PR1_CFG_SLV_PWM2_0" line.long 0x30 "ICSSM_PR1_CFG_SLV_PWM2_1" line.long 0x34 "ICSSM_PR1_CFG_SLV_PWM2_2" line.long 0x38 "ICSSM_PR1_CFG_SLV_PWM3_0" line.long 0x3C "ICSSM_PR1_CFG_SLV_PWM3_1" line.long 0x40 "ICSSM_PR1_CFG_SLV_PWM3_2" line.long 0x44 "ICSSM_PR1_CFG_SLV_SPIN_LOCK0" line.long 0x48 "ICSSM_PR1_CFG_SLV_SPIN_LOCK1" line.long 0x4C "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_CFG0" line.long 0x50 "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_STAT0" line.long 0x54 "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_CFG1" line.long 0x58 "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_STAT1" line.long 0x5C "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_CFG2" line.long 0x60 "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_STAT2" line.long 0x64 "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_CFG3" line.long 0x68 "ICSSM_PR1_CFG_SLV_PA_STAT_PDSP_STAT3" tree.end tree "ICSSM0_ICSSM_PR1_ICSS_ECAP0_ECAP_SLV" base ad:0x48030000 group.long 0x0++0x17 line.long 0x0 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_TSCNT,TIME STAMP COUNTER REGISTER." hexmask.long 0x0 0.--31. 1. "TSCNT,ACTIVE 32 BIT COUNTER REGISTER WHICH IS USED AS THE CAPTURE TIME-BASE" line.long 0x4 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_CNTPHS,COUNTER PHASE CONTROL REGISTER." hexmask.long 0x4 0.--31. 1. "CNTPHS,COUNTER PHASE VALUE REGISTER THAT CAN BE PROGRAMMED FOR PHASE LAG/LEAD THIS REGISTER SHADOWS TSCNT AND IS LOADED INTO TSCNT UPON EITHER A SYNCI EVENT OR S/W FORCE VIA A CONTROL BITUSED TO ACHIEVE PHASE CONTROL SYNC WITH RESPECT TO OTHER ECAP AND.." line.long 0x8 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_CAP1,CAPTURE-1 REGISTER." hexmask.long 0x8 0.--31. 1. "CAP1,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSES / INITIALISATIONAPRD SHADOW REGISTER [IE CAP3] WHEN USED IN APWM MODE" line.long 0xC "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_CAP2,CAPTURE-2 REGISTER." hexmask.long 0xC 0.--31. 1. "CAP2,THIS REGISTER CAN BE LOADED [WRITTEN] BY :TIME-STAMP [IE COUNTER VALUE] DURING A CAPTURE EVENTS/W MAY BE USEFUL FOR TEST PURPOSESACMP SHADOW REGISTER [IE CAP4] WHEN USED IN APWM MODE" line.long 0x10 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_CAP3,CAPTURE-3 REGISTER." hexmask.long 0x10 0.--31. 1. "CAP3,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE PERIOD SHADOW [APER] REGISTER USER UPDATES THE PWM PERIOD VALUE VIA THIS REGISTER IN THIS MODE CAP3 [APRD] SHADOWS CAP1" line.long 0x14 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_CAP4,CAPTURE-4 REGISTER." hexmask.long 0x14 0.--31. 1. "CAP4,IN CMP MODE THIS IS A TIME-STAMP CAPTURE REGISTERIN APMW MODE THIS IS THE COMPARE SHADOW [ACMP] REGISTER USER UPDATES THE PWM COMPARE VALUE VIA THIS REGISTER IN THIS MODE CAP4 [ACMP] SHADOWS CAP2" group.long 0x28++0xF line.long 0x0 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECCTL2_ECCTL1,ECAP CONTROL REGISTER 1" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM OUTPUT POLARITY SELECT:0OUTPUT IS ACTIVE HIGH [IE COMPARE VALUE DEFINES HIGH TIME]1OUTPUT IS ACTIVE LOW [IE COMPARE VALUE DEFINES LOW TIME]NOTE: THIS IS APPLICABLE ONLY IN APWM OPERATING MODE" "0,1" bitfld.long 0x0 25. "CAP_APWM,CAP/APWM OPERATING MODE SELECT:0ECAP MODULE OPERATES IN CAPTURE MODETHIS MODE FORCES THE FOLLOWING CONFIGURATION:1] INHIBITS TSCNT RESETS VIA PRD_EQ EVENT2] INHIBITS SHADOW LOADS ON CAP1 &" "0,1" newline bitfld.long 0x0 24. "SWSYNC,SOFTWARE FORCED COUNTER [TSCNT] SYNCING:0WRITING A ZERO HAS NO EFFECT WILL ALWAYS RETURN A ZERO1WRITING A ONE WILL FORCE A TSCNT SHADOW LOAD OF CURRENT ECAP MODULE AND ANY ECAP MODULES DOWN-STREAM PROVIDING THE SYNCO_SEL BITS ARE 0 0 AFTER WRITING.." "0,1" bitfld.long 0x0 22.--23. "SYNCO_SEL,SYNC-OUT SELECT:0 0SELECT SYNC-IN EVENT TO BE THE SYNC-OUT SIGNAL [PASS THROUGH]0 1SELECT PRD_EQ EVENT TO BE THE SYNC-OUT SIGNAL1 0DISABLE SYNC OUT SIGNAL1 1DISABLE SYNC OUT SIGNALNOTE: SELECTION PRD_EQ IS MEANINGFUL ONLY IN APWM MODE HOWEVER.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,COUNTER [TSCNT] SYNC-IN SELECT MODE:0DISABLE SYNC-IN OPTION1ENABLE COUNTER [TSCNT] TO BE LOADED FROM CNTPHS REGISTER UPON EITHER A SYNCI SIGNAL OR A S/W FORCE EVENT" "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,COUNTER STOP [FREEZE] CONTROL:0COUNTER STOPPED1COUNTER FREE RUNNING" "0,1" bitfld.long 0x0 19. "REARM_RESET,ONE-SHOT RE-ARMING IE WAIT FOR STOP TRIGGER:WRITING A ONE ARMS THE ONE-SHOT SEQUENCE IE:1] RESETS THE MOD4 COUNTER TO ZERO2] UN-FREEZES THE MOD4 COUNTER3] ENABLES CAPTURE REGISTER LOADSWRITING A ZERO HAS NO EFFECT ALWAYS RETURNS A 0NOTE:.." "0,1" bitfld.long 0x0 17.--18. "STOPVALUE,STOP VALUE FOR ONE-SHOT MODE:THIS IS THE NUMBER [BETWEEN 1-4] OF CAPTURES ALLOWED TO OCCUR BEFORE THE CAP[1-4] REGISTERS ARE FROZEN IECAPTURE SEQUENCE IS STOPPED0 0STOP AFTER CAPTURE EVENT 10 1STOP AFTER CAPTURE EVENT 21 0STOP AFTER CAPTURE.." "0,1,2,3" newline bitfld.long 0x0 16. "CONT_ONESHT,CONTINUOUS OR ONESHOT MODE CONTROL:[APPLICABLE ONLY IN CAPTURE MODE]0OPERATE IN CONTINUOUS MODE1OPERATE IN ONE-SHOT MODE" "0,1" bitfld.long 0x0 15. "FREE,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1" bitfld.long 0x0 14. "SOFT,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1" newline hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,EVENT FILTER PRESCALE SELECT:0 0 0 0 0DIVIDE BY 1 [IE NO PRESCALE BY-PASS THE PRESCALER]0 0 0 0 1DIVIDE BY 20 0 0 1 0DIVIDE BY 40 0 0 1 1DIVIDE BY 60 0 1 0 0DIVIDE BY 80 0 1 0 1DIVIDE BY 10 1 1 1 1 0DIVIDE BY 601 1 1 1 1DIVIDE BY 62" bitfld.long 0x0 8. "CAPLDEN,ENABLE LOADING OF CAP1-4 REGISTERS ON A CAPTURE EVENT:0DISABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME1ENABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME" "0,1" bitfld.long 0x0 7. "CTRRST4,COUNTER RESET ON CAPTURE EVENT 4:0DO NOT RESET COUNTER ON CAPTURE EVENT 4 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 4 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1" newline bitfld.long 0x0 6. "CAP4POL,CAPTURE EVENT 4 POLARITY SELECT:0CAPTURE EVENT 4 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 4 TRIGGERED ON A FALLING EDGE [FE]" "0,1" bitfld.long 0x0 5. "CTRRST3,COUNTER RESET ON CAPTURE EVENT 3:0DO NOT RESET COUNTER ON CAPTURE EVENT 3 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 3 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1" bitfld.long 0x0 4. "CAP3POL,CAPTURE EVENT 3 POLARITY SELECT:0CAPTURE EVENT 3 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 3 TRIGGERED ON A FALLING EDGE [FE]" "0,1" newline bitfld.long 0x0 3. "CTRRST2,COUNTER RESET ON CAPTURE EVENT 2:0DO NOT RESET COUNTER ON CAPTURE EVENT 2 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 2 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,?" bitfld.long 0x0 2. "CAP2POL,CAPTURE EVENT 2 POLARITY SELECT:0CAPTURE EVENT 2 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 2 TRIGGERED ON A FALLING EDGE [FE]" "0,1" bitfld.long 0x0 1. "CTRRST1,COUNTER RESET ON CAPTURE EVENT 1:0DO NOT RESET COUNTER ON CAPTURE EVENT 1 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 1 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "?,1: 0DO NOT RESET COUNTER ON CAPTURE EVENT 1.." newline bitfld.long 0x0 0. "CAP1POL,CAPTURE EVENT 1 POLARITY SELECT:0CAPTURE EVENT 1 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 1 TRIGGERED ON A FALLING EDGE [FE]" "0,1" line.long 0x4 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECFLG_ECEINT,ECAP INTERRUPT ENABLE REGISTER." hexmask.long.byte 0x4 24.--31. 1. "FLAG_RESV0" rbitfld.long 0x4 23. "FLAG_CMPEQ,COMPARE EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE COMPARE REGISTER VALUE [ACMP]READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1" rbitfld.long 0x4 22. "FLAG_PRDEQ,PERIOD EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE PERIOD REGISTER VALUE [APER] AND WAS RESETREADING A 0 INDICATES NO EVENT OCCURREDNOTES: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1" newline rbitfld.long 0x4 21. "FLAG_CNTOVF,COUNTER OVERFLOW STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] HAS MADE THE TRANSITION FROM FFFFFFFF 00000000READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ACTIVE IN CAP &" "0,1" rbitfld.long 0x4 20. "FLAG_CEVT4,CAPTURE EVENT 4 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FOURTH EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1" rbitfld.long 0x4 19. "FLAG_CEVT3,CAPTURE EVENT 3 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE THIRD EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1" newline rbitfld.long 0x4 18. "FLAG_CEVT2,CAPTURE EVENT 2 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE SECOND EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1" rbitfld.long 0x4 17. "FLAG_CEVT1,CAPTURE EVENT 1 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FIRST EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1" rbitfld.long 0x4 16. "FLAG_INT,GLOBAL INTERRUPT STATUS FLAG: READING A 1 ON THIS BIT INDICATES THAT AN INTERRUPT WAS GENERATED FROM ONE OF THE FOLLOWING EVENTSREADING A 0 INDICATES NO INTERRUPT GENERATED" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "EN__RESV1" bitfld.long 0x4 7. "EN_CMPEQ,COMPARE EQUAL INTERRUPT ENABLE: 0DISABLED COMPARE EQUAL AS AN INTERRUPT SOURCE1ENABLE COMPARE EQUAL AS AN INTERRUPT SOURCE" "0,1" bitfld.long 0x4 6. "EN_PRDEQ,PERIOD EQUAL INTERRUPT ENABLE: 0DISABLED PERIOD EQUAL AS AN INTERRUPT SOURCE1ENABLE PERIOD EQUAL AS AN INTERRUPT SOURCE" "0,1" newline bitfld.long 0x4 5. "EN_CNTOVF,COUNTER OVERFLOW INTERRUPT ENABLE: 0DISABLED COUNTER OVERFLOW AS AN INTERRUPT SOURCE1ENABLE COUNTER OVERFLOW AS AN INTERRUPT SOURCE" "0,1" bitfld.long 0x4 4. "EN_CEVT4,CAPTURE EVENT 4 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1" bitfld.long 0x4 3. "EN_CEVT3,CAPTURE EVENT 3 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1" newline bitfld.long 0x4 2. "EN_CEVT2,CAPTURE EVENT 2 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1" bitfld.long 0x4 1. "EN_CEVT1,CAPTURE EVENT 1 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1" rbitfld.long 0x4 0. "EN_RESV0" "0,1" line.long 0x8 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECCLR,ECAP INTERRUPT CLEAR REGISTER." hexmask.long.byte 0x8 8.--15. 1. "_RESV0" bitfld.long 0x8 7. "CMPEQ,COMPARE EQUAL STATUS FLAG: WRITING A 1 WILL CLEAR THE CMPEQ FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" bitfld.long 0x8 6. "PRDEQ,PERIOD EQUAL STATUS FLAG: WRITING A 1 WILL CLEAR THE PRDEQ FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" newline bitfld.long 0x8 5. "CNTOVF,COUNTER OVERFLOW STATUS FLAG: WRITING A 1 WILL CLEAR THE CNTOVF FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" bitfld.long 0x8 4. "CEVT4,CAPTURE EVENT 4 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT3 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" bitfld.long 0x8 3. "CEVT3,CAPTURE EVENT 3 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT3 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" newline bitfld.long 0x8 2. "CEVT2,CAPTURE EVENT 2 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT2 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" bitfld.long 0x8 1. "CEVT1,CAPTURE EVENT 1 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT1 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" bitfld.long 0x8 0. "INT,GLOBAL INTERRUPT CLEAR FLAG: WRITING A 1 WILL CLEAR THE INT FLAG AND ENABLE FURTHER INTERRUPTS TO BE GENERATED IF ANY OF THE EVENT FLAGS ARE SET TO 1WRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1" line.long 0xC "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECFRC,ECAP INTERRUPT FORCING REGISTER." hexmask.long.byte 0xC 8.--15. 1. "_RESV1" bitfld.long 0xC 7. "CMPEQ,FORCE COMPARE EQUAL: WRITING A 1 TO THIS BIT WILL SET THE CMPEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" bitfld.long 0xC 6. "PRDEQ,FORCE PERIOD EQUAL: WRITING A 1 TO THIS BIT WILL SET THE PRDEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" newline bitfld.long 0xC 5. "CNTOVF,FORCE COUNTER OVERFLOW: WRITING A 1 TO THIS BIT WILL SET THE CNTOVF FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" bitfld.long 0xC 4. "CEVT4,FORCE CAPTURE EVENT4:WRITING A 1 TO THIS BIT WILL SET THE CEVT4 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" bitfld.long 0xC 3. "CEVT3,FORCE CAPTURE EVENT3:WRITING A 1 TO THIS BIT WILL SET THE CEVT3 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" newline bitfld.long 0xC 2. "CEVT2,FORCE CAPTURE EVENT2:WRITING A 1 TO THIS BIT WILL SET THE CEVT2 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" bitfld.long 0xC 1. "CEVT1,FORCE CAPTURE EVENT1:WRITING A 1 TO THIS BIT WILL SET THE CEVT1 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1" rbitfld.long 0xC 0. "_RESV0" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_REVID1,Revision Identification Register 1" hexmask.long 0x0 0.--31. 1. "REVID" tree.end tree "ICSSM0_ICSSM_PR1_ICSSS_UART_UART_SLV" base ad:0x48028000 rgroup.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_RBR,Receiver Buffer Register (read only)The UART receiver section consists of a receiver shift register (RSR) and a receiver buffer register (RBR). When the UART is in the FIFO mode. RBR is a 16-byte FIFO. Timing is supplied.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data" group.long 0x4++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_IER,The interrupt enable register (IER) is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in IER is forwarded to the CPU." bitfld.long 0x0 3. "EDSSI,Enable for Modem Status Interrupt" "0,1" newline bitfld.long 0x0 2. "ELSI,Enable for Receiver Line Status Interrupt 0h Receiver line status interrupt is disabled.1h Received line status is enabled" "0,1" newline bitfld.long 0x0 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt 0h Transmitter holding register empty interrupt is disabled.1h Transmitter holding register empty interrupt is enabled." "0,1" newline bitfld.long 0x0 0. "ERBI,Enable for Receiver Data Available Interrupt 0h Receiver data available interrupt and character timeout indication interrupt is disabled.1h Receiver data available interrupt and character timeout indication interrupt is.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_IIR,The interrupt identification register (IIR) is a read-only register at the same address as the FIFO control register (FCR). which is a write-only register. When an interrupt is generated and enabled in the interrupt.." bitfld.long 0x0 6.--7. "FIFOEN,FIFOs enabled 0h Non-FIFO mode1h-2h Reserved3h FIFOs are enabled. FIFOEN bit in the FIFO control register (FCR) is set to 1." "0,1,2,3" newline bitfld.long 0x0 1.--3. "INTID,Interrupt Type 0h Reserved1h Transmitter holding register empty (priority 3)2h Receiver data available (priority 2)3h Receiver line status (priority 1 highest)4h-5h Reserved6h Character timeout indication (priority 2)7h.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "IPEND,Interrupt pending.When any UART interrupt is generated and is enabled in IER IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled IPEND is never forced to 0." "0,1" group.long 0xC++0x7 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_LCR,Line Control Register (LCR)The system programmer controls the format of the asynchronous data communication exchange by using LCR. In addition. the programmer can retrieve. inspect. and modify the content of LCR; this.." bitfld.long 0x0 7. "DLAB,Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR THR and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If you.." "0,1" newline bitfld.long 0x0 6. "BC,Break Control 0 Break condition is disabled1 Break condition is transmitted to the receiving UART. A break condition is a condition where the UARTn_TXD signal is forced to the spacing (cleared) state." "0,1" newline bitfld.long 0x0 5. "SP,Stick parity. The SP bit works in conjunction with the EPS and PEN bits. 0 Stick parity is disabled1 Stick parity is enabled -When odd parity is selected (EPS = 0) the PARITY bit is transmitted and checked as set. -When even.." "0,1" newline bitfld.long 0x0 4. "EPS,Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. 0 Odd parity is selected (an odd number of logic 1s is transmitted or checked in the data and PARITY.." "0,1" newline bitfld.long 0x0 3. "PEN,Parity enable. The PEN bit works in conjunction with the SP and EPS bits. 0 No PARITY bit is transmitted or checked.1 Parity bit is generated in transmitted data and is checked in received data between the last data word bit and.." "0,1" newline bitfld.long 0x0 2. "STB,Number of STOP bits generated. STB specifies 1 1.5 or 2 STOP bits in each transmitted character. When STB = 1 the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit regardless of the number of STOP bits.." "0,1" newline bitfld.long 0x0 1. "WLS1,Word Length Select Bit 1" "0,1" newline bitfld.long 0x0 0. "WLS,Word length select.Number of bits in each transmitted or received serial character. When STB = 1 the WLS bit determines the number of STOP bits. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1" line.long 0x4 "ICSSM_PR1_ICSSS_UART_UART_SLV_MCR,Modem Control Register (MCR)The modem control register provides the ability to enable/disable the autoflow functions. and enable/disable the loopback function for diagnostic purposes." bitfld.long 0x4 5. "AFE,Autoflow control enable.Autoflow control allows the UARTn_RTS and UARTn_CTS signals to provide handshaking between UARTs during data transfer. When AFE = 1 the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this.." "0,1" newline bitfld.long 0x4 4. "LOOP,Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature. 0 Loop back mode is disabled.1 Loop back mode is enabled. When LOOP is set the following occur: -The UARTn_TXD signal is set high." "0,1" newline bitfld.long 0x4 3. "OUT2,Out2 Bit" "0,1" newline bitfld.long 0x4 2. "OUT1,Out1 Bit" "0,1" newline bitfld.long 0x4 1. "RTS,RTS control. When AFE = 1 the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature see your device-specific data manual for supported features. If this feature is not available this bit is reserved and.." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_LSR,Line Status Register (LSR)LSR provides information to the CPU concerning the status of data transfers. LSR is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions.." bitfld.long 0x0 7. "RXFIFOE,Receiver FIFO error.In non-FIFO mode:0 = There has been no error or RXFIFOE was cleared because the CPU read the erroneous character from the receiver buffer register (RBR).1 = There is a parity error framing error or break indicator in the.." "0: There has been no error,1: At least one parity error" newline bitfld.long 0x0 6. "TEMT,Transmitter empty (TEMT) indicator.In non-FIFO mode:0 = Either the transmitter holding register (THR) or the transmitter shift register (TSR) contains a data character.1 = Both the transmitter holding register (THR) and the transmitter shift.." "0: Either the transmitter FIFO or the transmitter..,1: Both the transmitter FIFO and the transmitter.." newline bitfld.long 0x0 5. "THRE,Transmitter holding register empty (THRE) indicator.If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER) an interrupt request is generated.In non-FIFO mode:0 = Transmitter holding register (THR) is not empty." "0: Transmitter FIFO is not empty,1: Transmitter FIFO is empty" newline bitfld.long 0x0 4. "BI,Break indicator.The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START data PARITY and STOP bits. If.." "0: No break has been detected,1: A break has been detected with the character at.." newline bitfld.long 0x0 3. "FE,Framing error (FE) indicator.A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high .." "0: No framing error has been detected,1: A framing error has been detected with the.." newline bitfld.long 0x0 2. "PE,Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set.." "0: No parity error has been detected,1: A parity error has been detected with the.." newline bitfld.long 0x0 1. "OE,Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER) an interrupt request is generated.In.." "0: No overrun error has been detected,1: Overrun error has been detected" newline bitfld.long 0x0 0. "DR,Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER) an interrupt request is generated.In non-FIFO mode:0 = Data is not ready or the DR bit was cleared because the.." "0: Data is not ready,1: Data is ready" line.long 0x4 "ICSSM_PR1_ICSSS_UART_UART_SLV_MSR,Modem Status Register (MSR)MSR provides information to the CPU concerning the status of modem control signals. MSR is intended for read operations only; do not write to this register." bitfld.long 0x4 7. "CD,Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1) this bit is equal to the MCR bit 3 (OUT2)." "0,1" newline bitfld.long 0x4 6. "RI,Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1) this bit is equal to the MCR bit 2 (OUT1)." "0,1" newline bitfld.long 0x4 5. "DSR,Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1) this bit is equal to the MCR bit 0 (DTR)." "0,1" newline bitfld.long 0x4 4. "CTS,Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1) this bit is equal to the MCR bit 1 (RTS)." "0,1" newline bitfld.long 0x4 3. "DCD,Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled a modem status interrupt is generated." "0,1" newline bitfld.long 0x4 2. "TERI,Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled a modem status interrupt is generated." "0,1" newline bitfld.long 0x4 1. "DDSR,Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled a modem status interrupt is generated." "0,1" newline bitfld.long 0x4 0. "DCTS,Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled) a modem status interrupt is.." "0,1" group.long 0x1C++0xB line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_SCR,Scratch Pad Register (SCR)SCR is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation." hexmask.long.byte 0x0 0.--7. 1. "DATA,Scratch Register BitsThese bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation." line.long 0x4 "ICSSM_PR1_ICSSS_UART_UART_SLV_DLL,Divisor LSB Latch." hexmask.long.byte 0x4 0.--7. 1. "DLL,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." line.long 0x8 "ICSSM_PR1_ICSSS_UART_UART_SLV_DLH,Divisor MSB Latch." hexmask.long.byte 0x8 0.--7. 1. "DLH,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." rgroup.long 0x28++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_REVID1,Revision Identification Register 1" hexmask.long 0x0 0.--31. 1. "REVID1,Peripheral Identification Number" group.long 0x30++0x7 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_PWREMU_MGMT,UART PowerManagement and Emulation Register." bitfld.long 0x0 14. "UTRST,UART transmitter reset. Resets and enables the transmitter. 0 Transmitter is disabled and in reset state.1 Transmitter is enabled." "0,1" newline bitfld.long 0x0 13. "URRST,UART receiver reset. Resets and enables the receiver. 0 Receiver is disabled and in reset state.1 Receiver is enabled." "0,1" newline bitfld.long 0x0 0. "FREE,Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted the UART can handle register read/write requests but does not generate any transmission/reception interrupts or events. 0 If a.." "0,1" line.long 0x4 "ICSSM_PR1_ICSSS_UART_UART_SLV_MDR,UART Mode Definition Register." bitfld.long 0x4 0. "OSM_SEL,Over-Sampling Mode Select 0 16x over-sampling1 13x over-sampling" "0,1" wgroup.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_THR,The transmitter holding register (THR) (write only)The UART transmitter section consists of a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode. THR is a 16-byte.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data to transmit" wgroup.long 0x8++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_FCR,FIFO Control Register (write only)The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification register (IIR). which is a read-only register." bitfld.long 0x0 6.--7. "RXFITL,Receiver FIFO trigger level.RXFIFTL sets the trigger level for the receiver FIFO.When the trigger level is reached a receiver data-ready interrupt is generated (if the interrupt request is enabled).Once the FIFO drops below the trigger level the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMAMODE1,DMA MODE1 enable if FIFOs are enabled.Always write 1 to DMAMODE1.After a hardware reset change DMAMODE1 from 0 to 1.DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. 0h DMA MODE 1 is disabled1h.." "0,1" newline bitfld.long 0x0 2. "TXCLR,Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. 0h No effect1h Clears transmitter FIFO and resets the transmitter FIFO counter. The shift register is not cleared." "0,1" newline bitfld.long 0x0 1. "RXCLR,Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. 0h No effect1h Clears receiver FIFO and resets the receiver FIFO counter. The shift register is not cleared." "0,1" newline bitfld.long 0x0 0. "FIFOEN,Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. 0h Non-FIFO mode. The transmitter and receiver FIFOs are.." "0,1" rgroup.long 0x2C++0x3 line.long 0x0 "ICSSM_PR1_ICSSS_UART_UART_SLV_REVID2,Revision Identification Register 2" hexmask.long.byte 0x0 0.--7. 1. "REVID2,Peripheral Identification Number" tree.end tree "ICSSM0_ICSSM_PR1_IEP0_SLV" base ad:0x4802E000 group.long 0x0++0x1B line.long 0x0 "ICSSM_PR1_IEP0_SLV_GLOBAL_CFG_REG" hexmask.long.word 0x0 8.--19. 1. "CMP_INC" hexmask.long.byte 0x0 4.--7. 1. "DEFAULT_INC" bitfld.long 0x0 0. "CNT_ENABLE" "0,1" line.long 0x4 "ICSSM_PR1_IEP0_SLV_GLOBAL_STATUS_REG" bitfld.long 0x4 0. "CNT_OVF" "0,1" line.long 0x8 "ICSSM_PR1_IEP0_SLV_COMPEN_REG" hexmask.long.tbyte 0x8 0.--22. 1. "COMPEN_CNT" line.long 0xC "ICSSM_PR1_IEP0_SLV_SLOW_COMPEN_REG" hexmask.long 0xC 0.--31. 1. "SLOW_COMPEN_CNT" line.long 0x10 "ICSSM_PR1_IEP0_SLV_COUNT_REG0" hexmask.long 0x10 0.--31. 1. "COUNT_LO" line.long 0x14 "ICSSM_PR1_IEP0_SLV_COUNT_REG1" hexmask.long 0x14 0.--31. 1. "COUNT_HI" line.long 0x18 "ICSSM_PR1_IEP0_SLV_CAP_CFG_REG" hexmask.long.byte 0x18 18.--23. 1. "EXT_CAP_EN" hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN" hexmask.long.word 0x18 0.--9. 1. "CAP_EN" rgroup.long 0x1C++0x53 line.long 0x0 "ICSSM_PR1_IEP0_SLV_CAP_STATUS_REG" hexmask.long.byte 0x0 16.--23. 1. "CAP_RAW" hexmask.long.word 0x0 0.--10. 1. "CAP_VALID" line.long 0x4 "ICSSM_PR1_IEP0_SLV_CAPR0_REG0" hexmask.long 0x4 0.--31. 1. "CAPR0_0" line.long 0x8 "ICSSM_PR1_IEP0_SLV_CAPR0_REG1" hexmask.long 0x8 0.--31. 1. "CAPR0_1" line.long 0xC "ICSSM_PR1_IEP0_SLV_CAPR1_REG0" hexmask.long 0xC 0.--31. 1. "CAPR1_0" line.long 0x10 "ICSSM_PR1_IEP0_SLV_CAPR1_REG1" hexmask.long 0x10 0.--31. 1. "CAPR1_1" line.long 0x14 "ICSSM_PR1_IEP0_SLV_CAPR2_REG0" hexmask.long 0x14 0.--31. 1. "CAPR2_0" line.long 0x18 "ICSSM_PR1_IEP0_SLV_CAPR2_REG1" hexmask.long 0x18 0.--31. 1. "CAPR2_1" line.long 0x1C "ICSSM_PR1_IEP0_SLV_CAPR3_REG0" hexmask.long 0x1C 0.--31. 1. "CAPR3_0" line.long 0x20 "ICSSM_PR1_IEP0_SLV_CAPR3_REG1" hexmask.long 0x20 0.--31. 1. "CAPR3_1" line.long 0x24 "ICSSM_PR1_IEP0_SLV_CAPR4_REG0" hexmask.long 0x24 0.--31. 1. "CAPR4_0" line.long 0x28 "ICSSM_PR1_IEP0_SLV_CAPR4_REG1" hexmask.long 0x28 0.--31. 1. "CAPR4_1" line.long 0x2C "ICSSM_PR1_IEP0_SLV_CAPR5_REG0" hexmask.long 0x2C 0.--31. 1. "CAPR5_0" line.long 0x30 "ICSSM_PR1_IEP0_SLV_CAPR5_REG1" hexmask.long 0x30 0.--31. 1. "CAPR5_1" line.long 0x34 "ICSSM_PR1_IEP0_SLV_CAPR6_REG0" hexmask.long 0x34 0.--31. 1. "CAPR6_0" line.long 0x38 "ICSSM_PR1_IEP0_SLV_CAPR6_REG1" hexmask.long 0x38 0.--31. 1. "CAPR6_1" line.long 0x3C "ICSSM_PR1_IEP0_SLV_CAPF6_REG0" hexmask.long 0x3C 0.--31. 1. "CAPF6_0" line.long 0x40 "ICSSM_PR1_IEP0_SLV_CAPF6_REG1" hexmask.long 0x40 0.--31. 1. "CAPF6_1" line.long 0x44 "ICSSM_PR1_IEP0_SLV_CAPR7_REG0" hexmask.long 0x44 0.--31. 1. "CAPR7_0" line.long 0x48 "ICSSM_PR1_IEP0_SLV_CAPR7_REG1" hexmask.long 0x48 0.--31. 1. "CAPR7_1" line.long 0x4C "ICSSM_PR1_IEP0_SLV_CAPF7_REG0" hexmask.long 0x4C 0.--31. 1. "CAPF7_0" line.long 0x50 "ICSSM_PR1_IEP0_SLV_CAPF7_REG1" hexmask.long 0x50 0.--31. 1. "CAPF7_1" group.long 0x70++0x9B line.long 0x0 "ICSSM_PR1_IEP0_SLV_CMP_CFG_REG" bitfld.long 0x0 17. "SHADOW_EN" "0,1" hexmask.long.word 0x0 1.--16. 1. "CMP_EN" bitfld.long 0x0 0. "CMP0_RST_CNT_EN" "0,1" line.long 0x4 "ICSSM_PR1_IEP0_SLV_CMP_STATUS_REG" hexmask.long.word 0x4 0.--15. 1. "CMP_STATUS" line.long 0x8 "ICSSM_PR1_IEP0_SLV_CMP0_REG0" hexmask.long 0x8 0.--31. 1. "CMP0_0" line.long 0xC "ICSSM_PR1_IEP0_SLV_CMP0_REG1" hexmask.long 0xC 0.--31. 1. "CMP0_1" line.long 0x10 "ICSSM_PR1_IEP0_SLV_CMP1_REG0" hexmask.long 0x10 0.--31. 1. "CMP1_0" line.long 0x14 "ICSSM_PR1_IEP0_SLV_CMP1_REG1" hexmask.long 0x14 0.--31. 1. "CMP1_1" line.long 0x18 "ICSSM_PR1_IEP0_SLV_CMP2_REG0" hexmask.long 0x18 0.--31. 1. "CMP2_0" line.long 0x1C "ICSSM_PR1_IEP0_SLV_CMP2_REG1" hexmask.long 0x1C 0.--31. 1. "CMP2_1" line.long 0x20 "ICSSM_PR1_IEP0_SLV_CMP3_REG0" hexmask.long 0x20 0.--31. 1. "CMP3_0" line.long 0x24 "ICSSM_PR1_IEP0_SLV_CMP3_REG1" hexmask.long 0x24 0.--31. 1. "CMP3_1" line.long 0x28 "ICSSM_PR1_IEP0_SLV_CMP4_REG0" hexmask.long 0x28 0.--31. 1. "CMP4_0" line.long 0x2C "ICSSM_PR1_IEP0_SLV_CMP4_REG1" hexmask.long 0x2C 0.--31. 1. "CMP4_1" line.long 0x30 "ICSSM_PR1_IEP0_SLV_CMP5_REG0" hexmask.long 0x30 0.--31. 1. "CMP5_0" line.long 0x34 "ICSSM_PR1_IEP0_SLV_CMP5_REG1" hexmask.long 0x34 0.--31. 1. "CMP5_1" line.long 0x38 "ICSSM_PR1_IEP0_SLV_CMP6_REG0" hexmask.long 0x38 0.--31. 1. "CMP6_0" line.long 0x3C "ICSSM_PR1_IEP0_SLV_CMP6_REG1" hexmask.long 0x3C 0.--31. 1. "CMP6_1" line.long 0x40 "ICSSM_PR1_IEP0_SLV_CMP7_REG0" hexmask.long 0x40 0.--31. 1. "CMP7_0" line.long 0x44 "ICSSM_PR1_IEP0_SLV_CMP7_REG1" hexmask.long 0x44 0.--31. 1. "CMP7_1" line.long 0x48 "ICSSM_PR1_IEP0_SLV_RXIPG0_REG" hexmask.long.word 0x48 16.--31. 1. "RX_MIN_IPG0" hexmask.long.word 0x48 0.--15. 1. "RX_IPG0" line.long 0x4C "ICSSM_PR1_IEP0_SLV_RXIPG1_REG" hexmask.long.word 0x4C 16.--31. 1. "RX_MIN_IPG1" hexmask.long.word 0x4C 0.--15. 1. "RX_IPG1" line.long 0x50 "ICSSM_PR1_IEP0_SLV_CMP8_REG0" hexmask.long 0x50 0.--31. 1. "CMP8_0" line.long 0x54 "ICSSM_PR1_IEP0_SLV_CMP8_REG1" hexmask.long 0x54 0.--31. 1. "CMP8_1" line.long 0x58 "ICSSM_PR1_IEP0_SLV_CMP9_REG0" hexmask.long 0x58 0.--31. 1. "CMP9_0" line.long 0x5C "ICSSM_PR1_IEP0_SLV_CMP9_REG1" hexmask.long 0x5C 0.--31. 1. "CMP9_1" line.long 0x60 "ICSSM_PR1_IEP0_SLV_CMP10_REG0" hexmask.long 0x60 0.--31. 1. "CMP10_0" line.long 0x64 "ICSSM_PR1_IEP0_SLV_CMP10_REG1" hexmask.long 0x64 0.--31. 1. "CMP10_1" line.long 0x68 "ICSSM_PR1_IEP0_SLV_CMP11_REG0" hexmask.long 0x68 0.--31. 1. "CMP11_0" line.long 0x6C "ICSSM_PR1_IEP0_SLV_CMP11_REG1" hexmask.long 0x6C 0.--31. 1. "CMP11_1" line.long 0x70 "ICSSM_PR1_IEP0_SLV_CMP12_REG0" hexmask.long 0x70 0.--31. 1. "CMP12_0" line.long 0x74 "ICSSM_PR1_IEP0_SLV_CMP12_REG1" hexmask.long 0x74 0.--31. 1. "CMP12_1" line.long 0x78 "ICSSM_PR1_IEP0_SLV_CMP13_REG0" hexmask.long 0x78 0.--31. 1. "CMP13_0" line.long 0x7C "ICSSM_PR1_IEP0_SLV_CMP13_REG1" hexmask.long 0x7C 0.--31. 1. "CMP13_1" line.long 0x80 "ICSSM_PR1_IEP0_SLV_CMP14_REG0" hexmask.long 0x80 0.--31. 1. "CMP14_0" line.long 0x84 "ICSSM_PR1_IEP0_SLV_CMP14_REG1" hexmask.long 0x84 0.--31. 1. "CMP14_1" line.long 0x88 "ICSSM_PR1_IEP0_SLV_CMP15_REG0" hexmask.long 0x88 0.--31. 1. "CMP15_0" line.long 0x8C "ICSSM_PR1_IEP0_SLV_CMP15_REG1" hexmask.long 0x8C 0.--31. 1. "CMP15_1" line.long 0x90 "ICSSM_PR1_IEP0_SLV_COUNT_RESET_VAL_REG0" hexmask.long 0x90 0.--31. 1. "RESET_VAL_0" line.long 0x94 "ICSSM_PR1_IEP0_SLV_COUNT_RESET_VAL_REG1" hexmask.long 0x94 0.--31. 1. "RESET_VAL_1" line.long 0x98 "ICSSM_PR1_IEP0_SLV_PWM_REG" bitfld.long 0x98 3. "PWM3_HIT" "0,1" bitfld.long 0x98 2. "PWM3_RST_CNT_EN" "0,1" bitfld.long 0x98 1. "PWM0_HIT" "0,1" bitfld.long 0x98 0. "PWM0_RST_CNT_EN" "0,1" rgroup.long 0x10C++0x4F line.long 0x0 "ICSSM_PR1_IEP0_SLV_CAPR0_BI_REG0" hexmask.long 0x0 0.--31. 1. "CAPR0_0" line.long 0x4 "ICSSM_PR1_IEP0_SLV_CAPR0_BI_REG1" hexmask.long 0x4 0.--31. 1. "CAPR0_1" line.long 0x8 "ICSSM_PR1_IEP0_SLV_CAPR1_BI_REG0" hexmask.long 0x8 0.--31. 1. "CAPR1_0" line.long 0xC "ICSSM_PR1_IEP0_SLV_CAPR1_BI_REG1" hexmask.long 0xC 0.--31. 1. "CAPR1_1" line.long 0x10 "ICSSM_PR1_IEP0_SLV_CAPR2_BI_REG0" hexmask.long 0x10 0.--31. 1. "CAPR2_0" line.long 0x14 "ICSSM_PR1_IEP0_SLV_CAPR2_BI_REG1" hexmask.long 0x14 0.--31. 1. "CAPR2_1" line.long 0x18 "ICSSM_PR1_IEP0_SLV_CAPR3_BI_REG0" hexmask.long 0x18 0.--31. 1. "CAPR3_0" line.long 0x1C "ICSSM_PR1_IEP0_SLV_CAPR3_BI_REG1" hexmask.long 0x1C 0.--31. 1. "CAPR3_1" line.long 0x20 "ICSSM_PR1_IEP0_SLV_CAPR4_BI_REG0" hexmask.long 0x20 0.--31. 1. "CAPR4_0" line.long 0x24 "ICSSM_PR1_IEP0_SLV_CAPR4_BI_REG1" hexmask.long 0x24 0.--31. 1. "CAPR4_1" line.long 0x28 "ICSSM_PR1_IEP0_SLV_CAPR5_BI_REG0" hexmask.long 0x28 0.--31. 1. "CAPR5_0" line.long 0x2C "ICSSM_PR1_IEP0_SLV_CAPR5_BI_REG1" hexmask.long 0x2C 0.--31. 1. "CAPR5_1" line.long 0x30 "ICSSM_PR1_IEP0_SLV_CAPR6_BI_REG0" hexmask.long 0x30 0.--31. 1. "CAPR6_0" line.long 0x34 "ICSSM_PR1_IEP0_SLV_CAPR6_BI_REG1" hexmask.long 0x34 0.--31. 1. "CAPR6_1" line.long 0x38 "ICSSM_PR1_IEP0_SLV_CAPF6_BI_REG0" hexmask.long 0x38 0.--31. 1. "CAPF6_0" line.long 0x3C "ICSSM_PR1_IEP0_SLV_CAPF6_BI_REG1" hexmask.long 0x3C 0.--31. 1. "CAPF6_1" line.long 0x40 "ICSSM_PR1_IEP0_SLV_CAPR7_BI_REG0" hexmask.long 0x40 0.--31. 1. "CAPR7_0" line.long 0x44 "ICSSM_PR1_IEP0_SLV_CAPR7_BI_REG1" hexmask.long 0x44 0.--31. 1. "CAPR7_1" line.long 0x48 "ICSSM_PR1_IEP0_SLV_CAPF7_BI_REG0" hexmask.long 0x48 0.--31. 1. "CAPF7_0" line.long 0x4C "ICSSM_PR1_IEP0_SLV_CAPF7_BI_REG1" hexmask.long 0x4C 0.--31. 1. "CAPF7_1" group.long 0x180++0x3 line.long 0x0 "ICSSM_PR1_IEP0_SLV_SYNC_CTRL_REG" bitfld.long 0x0 10. "SYNC1_OUT_NV_EN" "0,1" bitfld.long 0x0 9. "SYNC0_OUT_NV_EN" "0,1" bitfld.long 0x0 8. "SYNC1_IND_EN" "0,1" bitfld.long 0x0 7. "SYNC1_CYCLIC_EN" "0,1" newline bitfld.long 0x0 6. "SYNC1_ACK_EN" "0,1" bitfld.long 0x0 5. "SYNC0_CYCLIC_EN" "0,1" bitfld.long 0x0 4. "SYNC0_ACK_EN" "0,1" bitfld.long 0x0 2. "SYNC1_EN" "0,1" newline bitfld.long 0x0 1. "SYNC0_EN" "0,1" bitfld.long 0x0 0. "SYNC_EN" "0,1" rgroup.long 0x184++0xB line.long 0x0 "ICSSM_PR1_IEP0_SLV_SYNC_FIRST_STAT_REG" bitfld.long 0x0 1. "FIRST_SYNC1" "0,1" bitfld.long 0x0 0. "FIRST_SYNC0" "0,1" line.long 0x4 "ICSSM_PR1_IEP0_SLV_SYNC0_STAT_REG" bitfld.long 0x4 0. "SYNC0_PEND" "0,1" line.long 0x8 "ICSSM_PR1_IEP0_SLV_SYNC1_STAT_REG" bitfld.long 0x8 0. "SYNC1_PEND" "0,1" group.long 0x190++0xF line.long 0x0 "ICSSM_PR1_IEP0_SLV_SYNC_PWIDTH_REG" hexmask.long 0x0 0.--31. 1. "SYNC_HPW" line.long 0x4 "ICSSM_PR1_IEP0_SLV_SYNC0_PERIOD_REG" hexmask.long 0x4 0.--31. 1. "SYNC0_PERIOD" line.long 0x8 "ICSSM_PR1_IEP0_SLV_SYNC1_DELAY_REG" hexmask.long 0x8 0.--31. 1. "SYNC1_DELAY" line.long 0xC "ICSSM_PR1_IEP0_SLV_SYNC_START_REG" hexmask.long 0xC 0.--31. 1. "SYNC_START" group.long 0x200++0xB line.long 0x0 "ICSSM_PR1_IEP0_SLV_WD_PREDIV_REG" hexmask.long.word 0x0 0.--15. 1. "PRE_DIV" line.long 0x4 "ICSSM_PR1_IEP0_SLV_PDI_WD_TIM_REG" hexmask.long.word 0x4 0.--15. 1. "PDI_WD_TIME" line.long 0x8 "ICSSM_PR1_IEP0_SLV_PD_WD_TIM_REG" hexmask.long.word 0x8 0.--15. 1. "PD_WD_TIME" rgroup.long 0x20C++0x3 line.long 0x0 "ICSSM_PR1_IEP0_SLV_WD_STATUS_REG" bitfld.long 0x0 16. "PDI_WD_STAT" "0,1" bitfld.long 0x0 0. "PD_WD_STAT" "0,1" group.long 0x210++0x7 line.long 0x0 "ICSSM_PR1_IEP0_SLV_WD_EXP_CNT_REG" hexmask.long.byte 0x0 8.--15. 1. "PD_EXP_CNT" hexmask.long.byte 0x0 0.--7. 1. "PDI_EXP_CNT" line.long 0x4 "ICSSM_PR1_IEP0_SLV_WD_CTRL_REG" bitfld.long 0x4 16. "PDI_WD_EN" "0,1" bitfld.long 0x4 0. "PD_WD_EN" "0,1" group.long 0x300++0x3 line.long 0x0 "ICSSM_PR1_IEP0_SLV_DIGIO_CTRL_REG" bitfld.long 0x0 6.--7. "OUT_MODE" "0,1,2,3" bitfld.long 0x0 4.--5. "IN_MODE" "0,1,2,3" bitfld.long 0x0 3. "WD_MODE" "0,1" rbitfld.long 0x0 2. "BIDI_MODE" "0,1" newline bitfld.long 0x0 1. "OUTVALID_MODE" "0,1" rbitfld.long 0x0 0. "OUTVALID_POL" "0,1" rgroup.long 0x304++0xB line.long 0x0 "ICSSM_PR1_IEP0_SLV_DIGIO_STATUS_REG" hexmask.long 0x0 0.--31. 1. "DIGIO_STAT" line.long 0x4 "ICSSM_PR1_IEP0_SLV_DIGIO_DATA_IN_REG" hexmask.long 0x4 0.--31. 1. "DATA_IN" line.long 0x8 "ICSSM_PR1_IEP0_SLV_DIGIO_DATA_IN_RAW_REG" hexmask.long 0x8 0.--31. 1. "DATA_IN_RAW" group.long 0x310++0xB line.long 0x0 "ICSSM_PR1_IEP0_SLV_DIGIO_DATA_OUT_REG" hexmask.long 0x0 0.--31. 1. "DATA_OUT" line.long 0x4 "ICSSM_PR1_IEP0_SLV_DIGIO_DATA_OUT_EN_REG" hexmask.long 0x4 0.--31. 1. "DATA_OUT_EN" line.long 0x8 "ICSSM_PR1_IEP0_SLV_DIGIO_EXP_REG" bitfld.long 0x8 13. "EOF_SEL" "0,1" bitfld.long 0x8 12. "SOF_SEL" "0,1" hexmask.long.byte 0x8 8.--11. 1. "SOF_DLY" hexmask.long.byte 0x8 4.--7. 1. "OUTVALID_DLY" newline bitfld.long 0x8 2. "SW_OUTVALID" "0,1" bitfld.long 0x8 1. "OUTVALID_OVR_EN" "0,1" bitfld.long 0x8 0. "SW_DATA_OUT_UP" "0,1" tree.end tree "ICSSM0_ICSSM_PR1_MDIO_V1P7_MDIO" base ad:0x48032400 rgroup.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_MDIO_V1P7_MDIO_MDIO_VERSION_REG,version_reg." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID" hexmask.long.byte 0x0 8.--15. 1. "REVMAJ,Major revision value" hexmask.long.byte 0x0 0.--7. 1. "REVMINOR,Minor revision value" group.long 0x4++0x7 line.long 0x0 "ICSSM_PR1_MDIO_V1P7_MDIO_CONTROL_REG,control_reg." rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1" bitfld.long 0x0 30. "ENABLE,Enable control" "0,1" hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel" newline bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1" bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1" bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1" newline bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1" hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider" line.long 0x4 "ICSSM_PR1_MDIO_V1P7_MDIO_ALIVE_REG,Alive_reg." hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive" rgroup.long 0xC++0x3 line.long 0x0 "ICSSM_PR1_MDIO_V1P7_MDIO_LINK_REG,Link_reg." hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state" group.long 0x10++0x37 line.long 0x0 "ICSSM_PR1_MDIO_V1P7_MDIO_LINK_INT_RAW_REG,Link_int_raw_reg." bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x4 "ICSSM_PR1_MDIO_V1P7_MDIO_LINK_INT_MASKED_REG,Link_int_masked_reg." bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" line.long 0x8 "ICSSM_PR1_MDIO_V1P7_MDIO_LINK_INT_MASK_SET_REG,Link_int_mask_set_reg." bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1" line.long 0xC "ICSSM_PR1_MDIO_V1P7_MDIO_LINK_INT_MASK_CLEAR_REG,Link_int_mask_clear_reg." bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1" line.long 0x10 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_INT_RAW_REG,user_int_raw_reg." bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3" line.long 0x14 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_INT_MASKED_REG,user_int_masked_reg." bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3" line.long 0x18 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_INT_MASK_SET_REG,user_int_mask_set_reg." bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3" line.long 0x1C "ICSSM_PR1_MDIO_V1P7_MDIO_USER_INT_MASK_CLEAR_REG,user_int_mask_clear_reg." bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3" line.long 0x20 "ICSSM_PR1_MDIO_V1P7_MDIO_MANUAL_IF_REG,manual_if_reg." bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1" bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1" bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1" line.long 0x24 "ICSSM_PR1_MDIO_V1P7_MDIO_POLL_REG,poll_reg." bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1" bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1" hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG" line.long 0x28 "ICSSM_PR1_MDIO_V1P7_MDIO_POLL_EN_REG,poll_en_reg." hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable" line.long 0x2C "ICSSM_PR1_MDIO_V1P7_MDIO_CLAUS45_REG" hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45" line.long 0x30 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_ADDR0_REG,MDIO USER Address 0" hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0" line.long 0x34 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_ADDR1_REG,MDIO USER Address 1" hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1" group.long 0x80++0x7 line.long 0x0 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_GROUP_USER_ACCESS_REG_j,user_access_reg" bitfld.long 0x0 31. "GO,Go" "0,1" bitfld.long 0x0 30. "WRITE,Write" "0,1" bitfld.long 0x0 29. "ACK,Acknowledge" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address" hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address" hexmask.long.word 0x0 0.--15. 1. "DATA,User data" line.long 0x4 "ICSSM_PR1_MDIO_V1P7_MDIO_USER_GROUP_USER_PHY_SEL_REG_j,user_phy_sel_reg" bitfld.long 0x4 7. "LINKSEL,Link status determination select" "0,1" bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1" hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored" tree.end base ad:0x0 tree "ICSSM0_ICSSM_PR1_MII" tree "ICSSM0_ICSSM_PR1_MII_RT_PR1_MII_RT_CFG" base ad:0x48032000 group.long 0x0++0x7 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RXCFG0,MIIRXCFG0Register." bitfld.long 0x0 9. "RX_EOF_SCLR_DIS0" "0,1" bitfld.long 0x0 8. "RX_ERR_RAW0" "0,1" bitfld.long 0x0 7. "RX_SFD_RAW0" "0,1" newline bitfld.long 0x0 6. "RX_AUTO_FWD_PRE0" "0,1" bitfld.long 0x0 5. "RX_BYTE_SWAP0" "0,1" bitfld.long 0x0 4. "RX_L2_EN0" "0,1" newline bitfld.long 0x0 3. "RX_MUX_SEL0" "0,1" bitfld.long 0x0 2. "RX_CUT_PREAMBLE0" "0,1" bitfld.long 0x0 1. "RX_DATA_RDY_MODE_DIS0" "0,1" newline bitfld.long 0x0 0. "RX_ENABLE0" "0,1" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RXCFG1,MIIRXCFG1Register." bitfld.long 0x4 9. "RX_EOF_SCLR_DIS1" "0,1" bitfld.long 0x4 8. "RX_ERR_RAW1" "0,1" bitfld.long 0x4 7. "RX_SFD_RAW1" "0,1" newline bitfld.long 0x4 6. "RX_AUTO_FWD_PRE1" "0,1" bitfld.long 0x4 5. "RX_BYTE_SWAP1" "0,1" bitfld.long 0x4 4. "RX_L2_EN1" "0,1" newline bitfld.long 0x4 3. "RX_MUX_SEL1" "0,1" bitfld.long 0x4 2. "RX_CUT_PREAMBLE1" "0,1" bitfld.long 0x4 1. "RX_DATA_RDY_MODE_DIS1" "0,1" newline bitfld.long 0x4 0. "RX_ENABLE1" "0,1" group.long 0x10++0x7 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TXCFG0,MIITXCFG0Register." bitfld.long 0x0 28.--30. "TX_CLK_DELAY0" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 16.--25. 1. "TX_START_DELAY0" bitfld.long 0x0 12. "TX_IPG_WIRE_CLK_EN0" "0,1" newline bitfld.long 0x0 11. "TX_32_MODE_EN0" "0,1" bitfld.long 0x0 10. "PRE_TX_AUTO_ESC_ERR0" "0,1" bitfld.long 0x0 9. "PRE_TX_AUTO_SEQUENCE0" "0,1" newline bitfld.long 0x0 8. "TX_MUX_SEL0" "0,1" bitfld.long 0x0 3. "TX_BYTE_SWAP0" "0,1" bitfld.long 0x0 2. "TX_EN_MODE0" "0,1" newline bitfld.long 0x0 1. "TX_AUTO_PREAMBLE0" "0,1" bitfld.long 0x0 0. "TX_ENABLE0" "0,1" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TXCFG1,MIITXCFG1Register." bitfld.long 0x4 28.--30. "TX_CLK_DELAY1" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 16.--25. 1. "TX_START_DELAY1" bitfld.long 0x4 12. "TX_IPG_WIRE_CLK_EN1" "0,1" newline bitfld.long 0x4 11. "TX_32_MODE_EN1" "0,1" bitfld.long 0x4 10. "PRE_TX_AUTO_ESC_ERR1" "0,1" bitfld.long 0x4 9. "PRE_TX_AUTO_SEQUENCE1" "0,1" newline bitfld.long 0x4 8. "TX_MUX_SEL1" "0,1" bitfld.long 0x4 3. "TX_BYTE_SWAP1" "0,1" bitfld.long 0x4 2. "TX_EN_MODE1" "0,1" newline bitfld.long 0x4 1. "TX_AUTO_PREAMBLE1" "0,1" bitfld.long 0x4 0. "TX_ENABLE1" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TX_CRC0,MIITXCRC0Register." hexmask.long 0x0 0.--31. 1. "TX_CRC0,Transmit CRC for last packet" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TX_CRC1,MIITXCRC1Register." hexmask.long 0x4 0.--31. 1. "TX_CRC1,Transmit CRC for last packet" group.long 0x30++0x7 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TX_IPG0,MIITXIPG0Register." hexmask.long.word 0x0 0.--15. 1. "TX_IPG0,Transmit IPG" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TX_IPG1,MIITXIPG1Register." hexmask.long.word 0x4 0.--15. 1. "TX_IPG1,Transmit IPG" rgroup.long 0x38++0x7 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_PRS0,MIIPortStatus0Register." bitfld.long 0x0 1. "SYNC_PORT0_CRS,Sync_port0_crs" "0,1" bitfld.long 0x0 0. "SYNC_PORT0_COL,Sync_port0_col" "0,1" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_PRS1,MIIPortStatus1Register." bitfld.long 0x4 1. "SYNC_PORT1_CRS,Sync_port1_crs" "0,1" bitfld.long 0x4 0. "SYNC_PORT1_COL,Sync_port1_col" "0,1" group.long 0x40++0x17 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_FRMS0,MIIRXFRMS0Register." hexmask.long.word 0x0 16.--31. 1. "RX_MAX_FRM0,Rx_max_frm0" hexmask.long.word 0x0 0.--15. 1. "RX_MIN_FRM0,Rx_min_frm0" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_FRMS1,MIIRXFRMS1Register." hexmask.long.word 0x4 16.--31. 1. "RX_MAX_FRM1,Rx_max_frm1" hexmask.long.word 0x4 0.--15. 1. "RX_MIN_FRM1,Rx_min_frm1" line.long 0x8 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_PCNT0,MIIRXPCNT0Register." hexmask.long.byte 0x8 4.--8. 1. "RX_MAX_PCNT0,Rx_max_pcnt0" hexmask.long.byte 0x8 0.--3. 1. "RX_MIN_PCNT0,Rx_min_pcnt0" line.long 0xC "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_PCNT1,MIIRXPCNT1Register." hexmask.long.byte 0xC 4.--8. 1. "RX_MAX_PCNT1,Rx_max_pcnt1" hexmask.long.byte 0xC 0.--3. 1. "RX_MIN_PCNT1,Rx_min_pcnt1" line.long 0x10 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_ERR0,MIIRXERR0Register." bitfld.long 0x10 3. "RX_MAX_FRM_ERR0,Rx_max_frm_err0" "0,1" bitfld.long 0x10 2. "RX_MIN_FRM_ERR0,Rx_min_frm_err0" "0,1" bitfld.long 0x10 1. "RX_MAX_PCNT_ERR0,Rx_max_pcnt_err0" "0,1" newline bitfld.long 0x10 0. "RX_MIN_PCNT_ERR0,Rx_min_pcnt_err0" "0,1" line.long 0x14 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_ERR1,MIIRXERR1Register." bitfld.long 0x14 3. "RX_MAX_FRM_ERR1,Rx_max_frm_err1" "0,1" bitfld.long 0x14 2. "RX_MIN_FRM_ERR1,Rx_min_frm_err1" "0,1" bitfld.long 0x14 1. "RX_MAX_PCNT_ERR1,Rx_max_pcnt_err1" "0,1" newline bitfld.long 0x14 0. "RX_MIN_PCNT_ERR1,Rx_min_pcnt_err1" "0,1" rgroup.long 0x60++0xF line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_FIFO_LEVEL0,MIIRXFIFOLEVEL0Register." hexmask.long.byte 0x0 0.--7. 1. "RX_FIFO_LEVEL0,Rx_fifo_level0" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_RX_FIFO_LEVEL1,MIIRXFIFOLEVEL1Register." hexmask.long.byte 0x4 0.--7. 1. "RX_FIFO_LEVEL1,Rx_fifo_level1" line.long 0x8 "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TX_FIFO_LEVEL0,MIIRXFIFOLEVEL0Register." hexmask.long.byte 0x8 0.--7. 1. "TX_FIFO_LEVEL0,tx_fifo_level0" line.long 0xC "ICSSM_PR1_MII_RT_PR1_MII_RT_CFG_TX_FIFO_LEVEL1,MIIRXFIFOLEVEL1Register." hexmask.long.byte 0xC 0.--7. 1. "TX_FIFO_LEVEL1,tx_fifo_level1" tree.end tree "ICSSM0_ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" base ad:0x48033000 group.long 0x0++0x1B line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_ICSS_G_CFG,ICSS_G Ethernet Cfg." bitfld.long 0x0 10. "RX_SFD_TX_SOF_EN,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1" bitfld.long 0x0 5.--6. "MII1_MODE,MII1 MODE 0:MII1:RGMII2:SGMII" "0: MII1:RGMII2:SGMII,?,?,?" newline bitfld.long 0x0 3.--4. "MII0_MODE,MII0 MODE 0:MII1:RGMII2:SGMII" "0: MII1:RGMII2:SGMII,?,?,?" bitfld.long 0x0 2. "RX_L2_G_EN,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L20:Disabled1:Enabled" "0,1" newline bitfld.long 0x0 1. "TX_L2_EN,Enable the TX L2 Fifo0:Disabled1:Enabled" "0,1" bitfld.long 0x0 0. "TX_L1_EN,Enable the TX L1 Fifo0:Disabled1:Enabled" "0,1" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_PREEMPT_CFG" hexmask.long.byte 0x4 24.--31. 1. "SMD_R,Response frame TAG" hexmask.long.byte 0x4 16.--23. 1. "SMD_V,Verification frame TAG" newline hexmask.long.byte 0x4 8.--15. 1. "EXP_SMD,None preemptable frame start or express frame" line.long 0x8 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_SMDT1S_CFG" hexmask.long.byte 0x8 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern" hexmask.long.byte 0x8 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern" newline hexmask.long.byte 0x8 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern" hexmask.long.byte 0x8 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern" line.long 0xC "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_SMDT1C_CFG" hexmask.long.byte 0xC 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern" hexmask.long.byte 0xC 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern" newline hexmask.long.byte 0xC 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern" hexmask.long.byte 0xC 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern" line.long 0x10 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_POOL_PTR_CFG" hexmask.long.word 0x10 0.--15. 1. "MAX_PKT_SIZE,Max Pkt Size used in pool ptr logic for wrap around" line.long 0x14 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_TX_EARLY_EOF" line.long 0x18 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_FRAG_CNT_CFG" hexmask.long.byte 0x18 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern" hexmask.long.byte 0x18 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern" newline hexmask.long.byte 0x18 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern" hexmask.long.byte 0x18 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern" group.long 0xD00++0x7F line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE0" hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PTR0,Queue 0" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE1" hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PTR1,Queue 1" line.long 0x8 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE2" hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PTR2,Queue 2" line.long 0xC "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE3" hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PTR3,Queue 3" line.long 0x10 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE4" hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PTR4,Queue 4" line.long 0x14 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE5" hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PTR5,Queue 5" line.long 0x18 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE6" hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PTR6,Queue 6" line.long 0x1C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE7" hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PTR7,Queue 7" line.long 0x20 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE8" hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PTR8,Queue 8" line.long 0x24 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE9" hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PTR9,Queue 9" line.long 0x28 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE10" hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PTR10,Queue 10" line.long 0x2C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE11" hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PTR11,Queue 11" line.long 0x30 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE12" hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PTR12,Queue 12" line.long 0x34 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE13" hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PTR13,Queue 13" line.long 0x38 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE14" hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PTR14,Queue 14" line.long 0x3C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE15" hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PTR15,Queue 15" line.long 0x40 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE16" hexmask.long.word 0x40 0.--15. 1. "QUEUE_H_PTR16,Queue 16" line.long 0x44 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE17" hexmask.long.word 0x44 0.--15. 1. "QUEUE_H_PTR17,Queue 17" line.long 0x48 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE18" hexmask.long.word 0x48 0.--15. 1. "QUEUE_H_PTR18,Queue 18" line.long 0x4C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE19" hexmask.long.word 0x4C 0.--15. 1. "QUEUE_H_PTR19,Queue 19" line.long 0x50 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE20" hexmask.long.word 0x50 0.--15. 1. "QUEUE_H_PTR20,Queue 20" line.long 0x54 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE21" hexmask.long.word 0x54 0.--15. 1. "QUEUE_H_PTR21,Queue 21" line.long 0x58 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE22" hexmask.long.word 0x58 0.--15. 1. "QUEUE_H_PTR22,Queue 22" line.long 0x5C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE23" hexmask.long.word 0x5C 0.--15. 1. "QUEUE_H_PTR23,Queue 23" line.long 0x60 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE24" hexmask.long.word 0x60 0.--15. 1. "QUEUE_H_PTR24,Queue 24" line.long 0x64 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE25" hexmask.long.word 0x64 0.--15. 1. "QUEUE_H_PTR25,Queue 25" line.long 0x68 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE26" hexmask.long.word 0x68 0.--15. 1. "QUEUE_H_PTR26,Queue 26" line.long 0x6C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE27" hexmask.long.word 0x6C 0.--15. 1. "QUEUE_H_PTR27,Queue 27" line.long 0x70 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE28" hexmask.long.word 0x70 0.--15. 1. "QUEUE_H_PTR28,Queue 28" line.long 0x74 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE29" hexmask.long.word 0x74 0.--15. 1. "QUEUE_H_PTR29,Queue 29" line.long 0x78 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE30" hexmask.long.word 0x78 0.--15. 1. "QUEUE_H_PTR30,Queue 30" line.long 0x7C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE31" hexmask.long.word 0x7C 0.--15. 1. "QUEUE_H_PTR31,Queue 31" rgroup.long 0xE00++0xBF line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK0" hexmask.long.word 0x0 0.--15. 1. "QUEUE_H_PEEK_PTR0,Queue 0 Peek portal" line.long 0x4 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK1" hexmask.long.word 0x4 0.--15. 1. "QUEUE_H_PEEK_PTR1,Queue 1 Peek portal" line.long 0x8 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK2" hexmask.long.word 0x8 0.--15. 1. "QUEUE_H_PEEK_PTR2,Queue 2 Peek portal" line.long 0xC "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK3" hexmask.long.word 0xC 0.--15. 1. "QUEUE_H_PEEK_PTR3,Queue 3 Peek portal" line.long 0x10 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK4" hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PEEK_PTR4,Queue 4 Peek portal" line.long 0x14 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK5" hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PEEK_PTR5,Queue 5 Peek portal" line.long 0x18 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK6" hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PEEK_PTR6,Queue 6 Peek portal" line.long 0x1C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK7" hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PEEK_PTR7,Queue 7 Peek portal" line.long 0x20 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK8" hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PEEK_PTR8,Queue 8 Peek portal" line.long 0x24 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK9" hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PEEK_PTR9,Queue 9 Peek portal" line.long 0x28 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK10" hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PEEK_PTR10,Queue 10 Peek portal" line.long 0x2C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK11" hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PEEK_PTR11,Queue 11 Peek portal" line.long 0x30 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK12" hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PEEK_PTR12,Queue 12 Peek portal" line.long 0x34 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK13" hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PEEK_PTR13,Queue 13 Peek portal" line.long 0x38 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK14" hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PEEK_PTR14,Queue 14 Peek portal" line.long 0x3C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_PEEK15" hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PEEK_PTR15,Queue 15 Peek portal" line.long 0x40 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT0" hexmask.long.word 0x40 0.--15. 1. "QUEUE_CNT_ENTRIES_0,Queue Entry Count0" line.long 0x44 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT1" hexmask.long.word 0x44 0.--15. 1. "QUEUE_CNT_ENTRIES_1,Queue Entry Count1" line.long 0x48 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT2" hexmask.long.word 0x48 0.--15. 1. "QUEUE_CNT_ENTRIES_2,Queue Entry Count2" line.long 0x4C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT3" hexmask.long.word 0x4C 0.--15. 1. "QUEUE_CNT_ENTRIES_3,Queue Entry Count3" line.long 0x50 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT4" hexmask.long.word 0x50 0.--15. 1. "QUEUE_CNT_ENTRIES_4,Queue Entry Count4" line.long 0x54 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT5" hexmask.long.word 0x54 0.--15. 1. "QUEUE_CNT_ENTRIES_5,Queue Entry Count5" line.long 0x58 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT6" hexmask.long.word 0x58 0.--15. 1. "QUEUE_CNT_ENTRIES_6,Queue Entry Count6" line.long 0x5C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT7" hexmask.long.word 0x5C 0.--15. 1. "QUEUE_CNT_ENTRIES_7,Queue Entry Count7" line.long 0x60 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT8" hexmask.long.word 0x60 0.--15. 1. "QUEUE_CNT_ENTRIES_8,Queue Entry Count8" line.long 0x64 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT9" hexmask.long.word 0x64 0.--15. 1. "QUEUE_CNT_ENTRIES_9,Queue Entry Count9" line.long 0x68 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT10" hexmask.long.word 0x68 0.--15. 1. "QUEUE_CNT_ENTRIES_10,Queue Entry Count10" line.long 0x6C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT11" hexmask.long.word 0x6C 0.--15. 1. "QUEUE_CNT_ENTRIES_11,Queue Entry Count11" line.long 0x70 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT12" hexmask.long.word 0x70 0.--15. 1. "QUEUE_CNT_ENTRIES_12,Queue Entry Count12" line.long 0x74 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT13" hexmask.long.word 0x74 0.--15. 1. "QUEUE_CNT_ENTRIES_13,Queue Entry Count13" line.long 0x78 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT14" hexmask.long.word 0x78 0.--15. 1. "QUEUE_CNT_ENTRIES_14,Queue Entry Count14" line.long 0x7C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT15" hexmask.long.word 0x7C 0.--15. 1. "QUEUE_CNT_ENTRIES_15,Queue Entry Count15" line.long 0x80 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT16" hexmask.long.word 0x80 0.--15. 1. "QUEUE_CNT_ENTRIES_16,Queue Entry Count16" line.long 0x84 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT17" hexmask.long.word 0x84 0.--15. 1. "QUEUE_CNT_ENTRIES_17,Queue Entry Count17" line.long 0x88 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT18" hexmask.long.word 0x88 0.--15. 1. "QUEUE_CNT_ENTRIES_18,Queue Entry Count18" line.long 0x8C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT19" hexmask.long.word 0x8C 0.--15. 1. "QUEUE_CNT_ENTRIES_19,Queue Entry Count19" line.long 0x90 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT20" hexmask.long.word 0x90 0.--15. 1. "QUEUE_CNT_ENTRIES_20,Queue Entry Count20" line.long 0x94 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT21" hexmask.long.word 0x94 0.--15. 1. "QUEUE_CNT_ENTRIES_21,Queue Entry Count21" line.long 0x98 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT22" hexmask.long.word 0x98 0.--15. 1. "QUEUE_CNT_ENTRIES_22,Queue Entry Count22" line.long 0x9C "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT23" hexmask.long.word 0x9C 0.--15. 1. "QUEUE_CNT_ENTRIES_23,Queue Entry Count23" line.long 0xA0 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT24" hexmask.long.word 0xA0 0.--15. 1. "QUEUE_CNT_ENTRIES_24,Queue Entry Count24" line.long 0xA4 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT25" hexmask.long.word 0xA4 0.--15. 1. "QUEUE_CNT_ENTRIES_25,Queue Entry Count25" line.long 0xA8 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT26" hexmask.long.word 0xA8 0.--15. 1. "QUEUE_CNT_ENTRIES_26,Queue Entry Count26" line.long 0xAC "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT27" hexmask.long.word 0xAC 0.--15. 1. "QUEUE_CNT_ENTRIES_27,Queue Entry Count27" line.long 0xB0 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT28" hexmask.long.word 0xB0 0.--15. 1. "QUEUE_CNT_ENTRIES_28,Queue Entry Count28" line.long 0xB4 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT29" hexmask.long.word 0xB4 0.--15. 1. "QUEUE_CNT_ENTRIES_29,Queue Entry Count29" line.long 0xB8 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT30" hexmask.long.word 0xB8 0.--15. 1. "QUEUE_CNT_ENTRIES_30,Queue Entry Count30" line.long 0xBC "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_CNT31" hexmask.long.word 0xBC 0.--15. 1. "QUEUE_CNT_ENTRIES_31,Queue Entry Count31" group.long 0xF40++0x3 line.long 0x0 "ICSSM_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_QUEUE_RESET" hexmask.long.byte 0x0 0.--5. 1. "RESET_QUEUE_ID,Reset Queue ID" tree.end tree.end tree "ICSSM0_ICSSM_PR1_PDSP0" tree "ICSSM0_ICSSM_PR1_PDSP0_IRAM" base ad:0x48022000 group.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_CONTROL" hexmask.long.word 0x0 16.--31. 1. "PCOUNTER_RST_VAL,Program counter reset value" newline rbitfld.long 0x0 15. "PDSP_STATE,PDSP run state: 0=PDSP is halted 1=PDSP is running" "0: PDSP is halted,1: PDSP is running" newline rbitfld.long 0x0 14. "BIG_ENDIAN,Big-endian input state" "0,1" newline bitfld.long 0x0 8. "SINGLE_STEP,Single step enable: 0=PDSP will free run when enabled 1=PDSP will execute a single instruction and then the pdsp_enable bit will be cleared" "0: PDSP will free run when enabled,1: PDSP will execute a single instruction and then.." newline bitfld.long 0x0 4. "RESTART,Causes PDSP to stop current operation gracefully and return to the PC reset value" "0,1" newline bitfld.long 0x0 3. "COUNTER_ENABLE,PDSP cycle counter enable: 0=Counters not enabled 1=Counters enabled" "0: Counters not enabled,1: Counters enabled" newline bitfld.long 0x0 2. "PDSP_SLEEPING,PDSP sleep indicator: 0=PDSP is not asleep 1=PDSP us asleep" "0: PDSP is not asleep,1: PDSP us asleep" newline bitfld.long 0x0 1. "PDSP_ENABLE,PDSP enable: 0=PDSP is disabled 1=PDSP is enabled" "0: PDSP is disabled,1: PDSP is enabled" newline rbitfld.long 0x0 0. "SOFT_RST_N,Soft reset. When this bit is cleared the PDSP will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_STATUS" hexmask.long.word 0x0 0.--15. 1. "PCOUNTER,Current PDSP program counter" group.long 0x8++0x7 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_WAKEUP_ENABLE" hexmask.long 0x0 0.--31. 1. "BITWISE_ENABLES,Wakeup enables" line.long 0x4 "ICSSM_PR1_PDSP0_IRAM_CYCLE_COUNT" hexmask.long 0x4 0.--31. 1. "CYCLECOUNT,This value is incremented by 1 for every clock cycle during which the PDSP is enabled and the counter is enabled." rgroup.long 0x10++0x3 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_STALL_COUNT" hexmask.long 0x0 0.--31. 1. "STALLCOUNT,This value is incremented by 1 for every clock cycle during which the PDSP is enabled the counter is enabled and the PDSP was unable to fetch a new instruction for any reason." group.long 0x20++0xF line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0" hexmask.long.byte 0x0 16.--23. 1. "C25_BLK_INDEX,PDSP constant entry 25 block index" newline hexmask.long.byte 0x0 0.--7. 1. "C24_BLK_INDEX,PDSP constant entry 24 block index" line.long 0x4 "ICSSM_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_1" hexmask.long.byte 0x4 16.--23. 1. "C27_BLK_INDEX,PDSP constant entry 27 block index" newline hexmask.long.byte 0x4 0.--7. 1. "C26_BLK_INDEX,PDSP constant entry 26 block index" line.long 0x8 "ICSSM_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0" hexmask.long.word 0x8 16.--31. 1. "C29_POINTER,PDSP constant entry 29 pointer" newline hexmask.long.word 0x8 0.--15. 1. "C28_POINTER,PDSP constant entry 28 pointer" line.long 0xC "ICSSM_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_1" hexmask.long.word 0xC 16.--31. 1. "C31_POINTER,PDSP constant entry 31 pointer" newline hexmask.long.word 0xC 0.--15. 1. "C30_POINTER,PDSP constant entry 30 pointer" tree.end tree "ICSSM0_ICSSM_PR1_PDSP0_IRAM_DEBUG" base ad:0x48022400 group.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_DEBUG_IGP_j,PDSP Internal General Purpose Register." hexmask.long 0x0 0.--31. 1. "REGN,PDSP Internal GP Register N" rgroup.long 0x80++0x3 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_DEBUG_ICTE_j,PDSP Internal Contants Table Entry Register." hexmask.long 0x0 0.--31. 1. "CT_ENTRYN,PDSP Internal Constants Table Entry N" tree.end tree "ICSSM0_ICSSM_PR1_PDSP0_IRAM_RAM" base ad:0x48034000 group.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_PDSP0_IRAM_RAM_IRAM,PDSP instruction RAM." hexmask.long 0x0 0.--31. 1. "VALUE,PDSP IRAM" tree.end tree.end tree "ICSSM0_ICSSM_PR1_PDSP1" tree "ICSSM0_ICSSM_PR1_PDSP1_IRAM" base ad:0x48024000 group.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_CONTROL" hexmask.long.word 0x0 16.--31. 1. "PCOUNTER_RST_VAL,Program counter reset value" newline rbitfld.long 0x0 15. "PDSP_STATE,PDSP run state: 0=PDSP is halted 1=PDSP is running" "0: PDSP is halted,1: PDSP is running" newline rbitfld.long 0x0 14. "BIG_ENDIAN,Big-endian input state" "0,1" newline bitfld.long 0x0 8. "SINGLE_STEP,Single step enable: 0=PDSP will free run when enabled 1=PDSP will execute a single instruction and then the pdsp_enable bit will be cleared" "0: PDSP will free run when enabled,1: PDSP will execute a single instruction and then.." newline bitfld.long 0x0 4. "RESTART,Causes PDSP to stop current operation gracefully and return to the PC reset value" "0,1" newline bitfld.long 0x0 3. "COUNTER_ENABLE,PDSP cycle counter enable: 0=Counters not enabled 1=Counters enabled" "0: Counters not enabled,1: Counters enabled" newline bitfld.long 0x0 2. "PDSP_SLEEPING,PDSP sleep indicator: 0=PDSP is not asleep 1=PDSP us asleep" "0: PDSP is not asleep,1: PDSP us asleep" newline bitfld.long 0x0 1. "PDSP_ENABLE,PDSP enable: 0=PDSP is disabled 1=PDSP is enabled" "0: PDSP is disabled,1: PDSP is enabled" newline rbitfld.long 0x0 0. "SOFT_RST_N,Soft reset. When this bit is cleared the PDSP will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_STATUS" hexmask.long.word 0x0 0.--15. 1. "PCOUNTER,Current PDSP program counter" group.long 0x8++0x7 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_WAKEUP_ENABLE" hexmask.long 0x0 0.--31. 1. "BITWISE_ENABLES,Wakeup enables" line.long 0x4 "ICSSM_PR1_PDSP1_IRAM_CYCLE_COUNT" hexmask.long 0x4 0.--31. 1. "CYCLECOUNT,This value is incremented by 1 for every clock cycle during which the PDSP is enabled and the counter is enabled." rgroup.long 0x10++0x3 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_STALL_COUNT" hexmask.long 0x0 0.--31. 1. "STALLCOUNT,This value is incremented by 1 for every clock cycle during which the PDSP is enabled the counter is enabled and the PDSP was unable to fetch a new instruction for any reason." group.long 0x20++0xF line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0" hexmask.long.byte 0x0 16.--23. 1. "C25_BLK_INDEX,PDSP constant entry 25 block index" newline hexmask.long.byte 0x0 0.--7. 1. "C24_BLK_INDEX,PDSP constant entry 24 block index" line.long 0x4 "ICSSM_PR1_PDSP1_IRAM_CONSTANT_TABLE_BLOCK_INDEX_1" hexmask.long.byte 0x4 16.--23. 1. "C27_BLK_INDEX,PDSP constant entry 27 block index" newline hexmask.long.byte 0x4 0.--7. 1. "C26_BLK_INDEX,PDSP constant entry 26 block index" line.long 0x8 "ICSSM_PR1_PDSP1_IRAM_CONSTANT_TABLE_PROG_PTR_0" hexmask.long.word 0x8 16.--31. 1. "C29_POINTER,PDSP constant entry 29 pointer" newline hexmask.long.word 0x8 0.--15. 1. "C28_POINTER,PDSP constant entry 28 pointer" line.long 0xC "ICSSM_PR1_PDSP1_IRAM_CONSTANT_TABLE_PROG_PTR_1" hexmask.long.word 0xC 16.--31. 1. "C31_POINTER,PDSP constant entry 31 pointer" newline hexmask.long.word 0xC 0.--15. 1. "C30_POINTER,PDSP constant entry 30 pointer" tree.end tree "ICSSM0_ICSSM_PR1_PDSP1_IRAM_DEBUG" base ad:0x48024400 group.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_DEBUG_IGP_j,PDSP Internal General Purpose Register." hexmask.long 0x0 0.--31. 1. "REGN,PDSP Internal GP Register N" rgroup.long 0x80++0x3 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_DEBUG_ICTE_j,PDSP Internal Contants Table Entry Register." hexmask.long 0x0 0.--31. 1. "CT_ENTRYN,PDSP Internal Constants Table Entry N" tree.end tree "ICSSM0_ICSSM_PR1_PDSP1_IRAM_RAM" base ad:0x48038000 group.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_PDSP1_IRAM_RAM_IRAM,PDSP instruction RAM." hexmask.long 0x0 0.--31. 1. "VALUE,PDSP IRAM" tree.end tree.end tree "ICSSM0_ICSSM_PR1_PROTECT_SLV" base ad:0x48024C00 group.long 0x0++0x7 line.long 0x0 "ICSSM_PR1_PROTECT_SLV_UNLOCK_KEY" hexmask.long 0x0 0.--31. 1. "UNLOCK_KEY,UnLock Key Pattern 0x83E7_0B13 to UnLock 0x0000_0000 to Lock Must unlock to update MMRs" line.long 0x4 "ICSSM_PR1_PROTECT_SLV_CFG,Config." bitfld.long 0x4 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM10:disable1:enable When enabled only PRU1 can write to DMEM1" "0,1" bitfld.long 0x4 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM00:disable1:enable When enabled only PRU0 can write to DMEM0" "0,1" bitfld.long 0x4 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG0:disable1:enable" "0,1" bitfld.long 0x4 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM0:disable1:enable" "0,1" newline bitfld.long 0x4 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM0:disable1:enable" "0,1" bitfld.long 0x4 1. "PRU1_WP_EN,Write Protect PRU1 access Debug IMEM0:disable1:enable" "0,1" bitfld.long 0x4 0. "PRU0_WP_EN,Write Protect PRU0 access Debug IMEM0:disable1:enable" "0,1" tree.end tree.end tree "ICSSM0_ICSSM_pr1_icss_intc_intc_slv" base ad:0x48020000 rgroup.long 0x0++0x3 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_REVISION_REG" bitfld.long 0x0 30.--31. "REV_SCHEME,Scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "REV_MODULE,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REV_RTL,RTL revisions" newline bitfld.long 0x0 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REV_MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CONTROL_REG" bitfld.long 0x0 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1" bitfld.long 0x0 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3" bitfld.long 0x0 1. "WAKEUP_MODE,Wakeup mode enable" "0,1" group.long 0x10++0x3 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_GLOBAL_ENABLE_HINT_REG" bitfld.long 0x0 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1" group.long 0x1C++0x3 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_GLB_NEST_LEVEL_REG" bitfld.long 0x0 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1" hexmask.long.word 0x0 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level" wgroup.long 0x20++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_STATUS_SET_INDEX_REG" hexmask.long.word 0x0 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_STATUS_CLR_INDEX_REG" hexmask.long.word 0x4 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)" group.long 0x28++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_SET_INDEX_REG" hexmask.long.word 0x0 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_CLR_INDEX_REG" hexmask.long.word 0x4 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)" group.long 0x34++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_HINT_ENABLE_SET_INDEX_REG" hexmask.long.word 0x0 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_HINT_ENABLE_CLR_INDEX_REG" hexmask.long.word 0x4 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts" rgroup.long 0x80++0x3 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_GLB_PRI_INTR_REG" bitfld.long 0x0 31. "GLB_NONE,No interrupt pending flag" "0,1" hexmask.long.word 0x0 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt" group.long 0x200++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_RAW_STATUS_REG0" bitfld.long 0x0 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1" bitfld.long 0x0 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1" bitfld.long 0x0 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1" newline bitfld.long 0x0 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1" bitfld.long 0x0 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1" bitfld.long 0x0 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1" newline bitfld.long 0x0 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1" bitfld.long 0x0 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1" bitfld.long 0x0 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1" newline bitfld.long 0x0 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1" bitfld.long 0x0 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1" bitfld.long 0x0 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1" newline bitfld.long 0x0 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1" bitfld.long 0x0 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1" bitfld.long 0x0 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1" newline bitfld.long 0x0 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1" bitfld.long 0x0 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1" bitfld.long 0x0 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1" newline bitfld.long 0x0 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1" bitfld.long 0x0 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1" bitfld.long 0x0 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1" newline bitfld.long 0x0 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1" bitfld.long 0x0 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1" bitfld.long 0x0 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1" newline bitfld.long 0x0 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1" bitfld.long 0x0 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1" bitfld.long 0x0 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1" newline bitfld.long 0x0 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1" bitfld.long 0x0 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1" bitfld.long 0x0 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1" newline bitfld.long 0x0 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1" bitfld.long 0x0 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_RAW_STATUS_REG1" bitfld.long 0x4 31. "RAW_STATUS_63,Raw Status (write 1 to set) for intr_in[63]" "0,1" bitfld.long 0x4 30. "RAW_STATUS_62,Raw Status (write 1 to set) for intr_in[62]" "0,1" bitfld.long 0x4 29. "RAW_STATUS_61,Raw Status (write 1 to set) for intr_in[61]" "0,1" newline bitfld.long 0x4 28. "RAW_STATUS_60,Raw Status (write 1 to set) for intr_in[60]" "0,1" bitfld.long 0x4 27. "RAW_STATUS_59,Raw Status (write 1 to set) for intr_in[59]" "0,1" bitfld.long 0x4 26. "RAW_STATUS_58,Raw Status (write 1 to set) for intr_in[58]" "0,1" newline bitfld.long 0x4 25. "RAW_STATUS_57,Raw Status (write 1 to set) for intr_in[57]" "0,1" bitfld.long 0x4 24. "RAW_STATUS_56,Raw Status (write 1 to set) for intr_in[56]" "0,1" bitfld.long 0x4 23. "RAW_STATUS_55,Raw Status (write 1 to set) for intr_in[55]" "0,1" newline bitfld.long 0x4 22. "RAW_STATUS_54,Raw Status (write 1 to set) for intr_in[54]" "0,1" bitfld.long 0x4 21. "RAW_STATUS_53,Raw Status (write 1 to set) for intr_in[53]" "0,1" bitfld.long 0x4 20. "RAW_STATUS_52,Raw Status (write 1 to set) for intr_in[52]" "0,1" newline bitfld.long 0x4 19. "RAW_STATUS_51,Raw Status (write 1 to set) for intr_in[51]" "0,1" bitfld.long 0x4 18. "RAW_STATUS_50,Raw Status (write 1 to set) for intr_in[50]" "0,1" bitfld.long 0x4 17. "RAW_STATUS_49,Raw Status (write 1 to set) for intr_in[49]" "0,1" newline bitfld.long 0x4 16. "RAW_STATUS_48,Raw Status (write 1 to set) for intr_in[48]" "0,1" bitfld.long 0x4 15. "RAW_STATUS_47,Raw Status (write 1 to set) for intr_in[47]" "0,1" bitfld.long 0x4 14. "RAW_STATUS_46,Raw Status (write 1 to set) for intr_in[46]" "0,1" newline bitfld.long 0x4 13. "RAW_STATUS_45,Raw Status (write 1 to set) for intr_in[45]" "0,1" bitfld.long 0x4 12. "RAW_STATUS_44,Raw Status (write 1 to set) for intr_in[44]" "0,1" bitfld.long 0x4 11. "RAW_STATUS_43,Raw Status (write 1 to set) for intr_in[43]" "0,1" newline bitfld.long 0x4 10. "RAW_STATUS_42,Raw Status (write 1 to set) for intr_in[42]" "0,1" bitfld.long 0x4 9. "RAW_STATUS_41,Raw Status (write 1 to set) for intr_in[41]" "0,1" bitfld.long 0x4 8. "RAW_STATUS_40,Raw Status (write 1 to set) for intr_in[40]" "0,1" newline bitfld.long 0x4 7. "RAW_STATUS_39,Raw Status (write 1 to set) for intr_in[39]" "0,1" bitfld.long 0x4 6. "RAW_STATUS_38,Raw Status (write 1 to set) for intr_in[38]" "0,1" bitfld.long 0x4 5. "RAW_STATUS_37,Raw Status (write 1 to set) for intr_in[37]" "0,1" newline bitfld.long 0x4 4. "RAW_STATUS_36,Raw Status (write 1 to set) for intr_in[36]" "0,1" bitfld.long 0x4 3. "RAW_STATUS_35,Raw Status (write 1 to set) for intr_in[35]" "0,1" bitfld.long 0x4 2. "RAW_STATUS_34,Raw Status (write 1 to set) for intr_in[34]" "0,1" newline bitfld.long 0x4 1. "RAW_STATUS_33,Raw Status (write 1 to set) for intr_in[33]" "0,1" bitfld.long 0x4 0. "RAW_STATUS_32,Raw Status (write 1 to set) for intr_in[32]" "0,1" group.long 0x280++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENA_STATUS_REG0" bitfld.long 0x0 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1" bitfld.long 0x0 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1" bitfld.long 0x0 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1" newline bitfld.long 0x0 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1" bitfld.long 0x0 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1" bitfld.long 0x0 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1" newline bitfld.long 0x0 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1" bitfld.long 0x0 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1" bitfld.long 0x0 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1" newline bitfld.long 0x0 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1" bitfld.long 0x0 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1" bitfld.long 0x0 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1" newline bitfld.long 0x0 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1" bitfld.long 0x0 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1" bitfld.long 0x0 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1" newline bitfld.long 0x0 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1" bitfld.long 0x0 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1" bitfld.long 0x0 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1" newline bitfld.long 0x0 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1" bitfld.long 0x0 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1" bitfld.long 0x0 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1" newline bitfld.long 0x0 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1" bitfld.long 0x0 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1" bitfld.long 0x0 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1" newline bitfld.long 0x0 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1" bitfld.long 0x0 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1" bitfld.long 0x0 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1" newline bitfld.long 0x0 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1" bitfld.long 0x0 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1" bitfld.long 0x0 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1" newline bitfld.long 0x0 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1" bitfld.long 0x0 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENA_STATUS_REG1" bitfld.long 0x4 31. "ENA_STATUS_63,Enabled Status for intr_in[63]" "0,1" bitfld.long 0x4 30. "ENA_STATUS_62,Enabled Status for intr_in[62]" "0,1" bitfld.long 0x4 29. "ENA_STATUS_61,Enabled Status for intr_in[61]" "0,1" newline bitfld.long 0x4 28. "ENA_STATUS_60,Enabled Status for intr_in[60]" "0,1" bitfld.long 0x4 27. "ENA_STATUS_59,Enabled Status for intr_in[59]" "0,1" bitfld.long 0x4 26. "ENA_STATUS_58,Enabled Status for intr_in[58]" "0,1" newline bitfld.long 0x4 25. "ENA_STATUS_57,Enabled Status for intr_in[57]" "0,1" bitfld.long 0x4 24. "ENA_STATUS_56,Enabled Status for intr_in[56]" "0,1" bitfld.long 0x4 23. "ENA_STATUS_55,Enabled Status for intr_in[55]" "0,1" newline bitfld.long 0x4 22. "ENA_STATUS_54,Enabled Status for intr_in[54]" "0,1" bitfld.long 0x4 21. "ENA_STATUS_53,Enabled Status for intr_in[53]" "0,1" bitfld.long 0x4 20. "ENA_STATUS_52,Enabled Status for intr_in[52]" "0,1" newline bitfld.long 0x4 19. "ENA_STATUS_51,Enabled Status for intr_in[51]" "0,1" bitfld.long 0x4 18. "ENA_STATUS_50,Enabled Status for intr_in[50]" "0,1" bitfld.long 0x4 17. "ENA_STATUS_49,Enabled Status for intr_in[49]" "0,1" newline bitfld.long 0x4 16. "ENA_STATUS_48,Enabled Status for intr_in[48]" "0,1" bitfld.long 0x4 15. "ENA_STATUS_47,Enabled Status for intr_in[47]" "0,1" bitfld.long 0x4 14. "ENA_STATUS_46,Enabled Status for intr_in[46]" "0,1" newline bitfld.long 0x4 13. "ENA_STATUS_45,Enabled Status for intr_in[45]" "0,1" bitfld.long 0x4 12. "ENA_STATUS_44,Enabled Status for intr_in[44]" "0,1" bitfld.long 0x4 11. "ENA_STATUS_43,Enabled Status for intr_in[43]" "0,1" newline bitfld.long 0x4 10. "ENA_STATUS_42,Enabled Status for intr_in[42]" "0,1" bitfld.long 0x4 9. "ENA_STATUS_41,Enabled Status for intr_in[41]" "0,1" bitfld.long 0x4 8. "ENA_STATUS_40,Enabled Status for intr_in[40]" "0,1" newline bitfld.long 0x4 7. "ENA_STATUS_39,Enabled Status for intr_in[39]" "0,1" bitfld.long 0x4 6. "ENA_STATUS_38,Enabled Status for intr_in[38]" "0,1" bitfld.long 0x4 5. "ENA_STATUS_37,Enabled Status for intr_in[37]" "0,1" newline bitfld.long 0x4 4. "ENA_STATUS_36,Enabled Status for intr_in[36]" "0,1" bitfld.long 0x4 3. "ENA_STATUS_35,Enabled Status for intr_in[35]" "0,1" bitfld.long 0x4 2. "ENA_STATUS_34,Enabled Status for intr_in[34]" "0,1" newline bitfld.long 0x4 1. "ENA_STATUS_33,Enabled Status for intr_in[33]" "0,1" bitfld.long 0x4 0. "ENA_STATUS_32,Enabled Status for intr_in[32]" "0,1" group.long 0x300++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_REG0" bitfld.long 0x0 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1" bitfld.long 0x0 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1" bitfld.long 0x0 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1" newline bitfld.long 0x0 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1" bitfld.long 0x0 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1" bitfld.long 0x0 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1" newline bitfld.long 0x0 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1" bitfld.long 0x0 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1" bitfld.long 0x0 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1" newline bitfld.long 0x0 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1" bitfld.long 0x0 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1" bitfld.long 0x0 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1" newline bitfld.long 0x0 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1" bitfld.long 0x0 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1" bitfld.long 0x0 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1" newline bitfld.long 0x0 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1" bitfld.long 0x0 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1" bitfld.long 0x0 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1" newline bitfld.long 0x0 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1" bitfld.long 0x0 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1" bitfld.long 0x0 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1" newline bitfld.long 0x0 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1" bitfld.long 0x0 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1" bitfld.long 0x0 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1" newline bitfld.long 0x0 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1" bitfld.long 0x0 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1" bitfld.long 0x0 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1" newline bitfld.long 0x0 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1" bitfld.long 0x0 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1" bitfld.long 0x0 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1" newline bitfld.long 0x0 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1" bitfld.long 0x0 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_REG1" bitfld.long 0x4 31. "ENABLE_63,Enable (set) for intr_in[63]" "0,1" bitfld.long 0x4 30. "ENABLE_62,Enable (set) for intr_in[62]" "0,1" bitfld.long 0x4 29. "ENABLE_61,Enable (set) for intr_in[61]" "0,1" newline bitfld.long 0x4 28. "ENABLE_60,Enable (set) for intr_in[60]" "0,1" bitfld.long 0x4 27. "ENABLE_59,Enable (set) for intr_in[59]" "0,1" bitfld.long 0x4 26. "ENABLE_58,Enable (set) for intr_in[58]" "0,1" newline bitfld.long 0x4 25. "ENABLE_57,Enable (set) for intr_in[57]" "0,1" bitfld.long 0x4 24. "ENABLE_56,Enable (set) for intr_in[56]" "0,1" bitfld.long 0x4 23. "ENABLE_55,Enable (set) for intr_in[55]" "0,1" newline bitfld.long 0x4 22. "ENABLE_54,Enable (set) for intr_in[54]" "0,1" bitfld.long 0x4 21. "ENABLE_53,Enable (set) for intr_in[53]" "0,1" bitfld.long 0x4 20. "ENABLE_52,Enable (set) for intr_in[52]" "0,1" newline bitfld.long 0x4 19. "ENABLE_51,Enable (set) for intr_in[51]" "0,1" bitfld.long 0x4 18. "ENABLE_50,Enable (set) for intr_in[50]" "0,1" bitfld.long 0x4 17. "ENABLE_49,Enable (set) for intr_in[49]" "0,1" newline bitfld.long 0x4 16. "ENABLE_48,Enable (set) for intr_in[48]" "0,1" bitfld.long 0x4 15. "ENABLE_47,Enable (set) for intr_in[47]" "0,1" bitfld.long 0x4 14. "ENABLE_46,Enable (set) for intr_in[46]" "0,1" newline bitfld.long 0x4 13. "ENABLE_45,Enable (set) for intr_in[45]" "0,1" bitfld.long 0x4 12. "ENABLE_44,Enable (set) for intr_in[44]" "0,1" bitfld.long 0x4 11. "ENABLE_43,Enable (set) for intr_in[43]" "0,1" newline bitfld.long 0x4 10. "ENABLE_42,Enable (set) for intr_in[42]" "0,1" bitfld.long 0x4 9. "ENABLE_41,Enable (set) for intr_in[41]" "0,1" bitfld.long 0x4 8. "ENABLE_40,Enable (set) for intr_in[40]" "0,1" newline bitfld.long 0x4 7. "ENABLE_39,Enable (set) for intr_in[39]" "0,1" bitfld.long 0x4 6. "ENABLE_38,Enable (set) for intr_in[38]" "0,1" bitfld.long 0x4 5. "ENABLE_37,Enable (set) for intr_in[37]" "0,1" newline bitfld.long 0x4 4. "ENABLE_36,Enable (set) for intr_in[36]" "0,1" bitfld.long 0x4 3. "ENABLE_35,Enable (set) for intr_in[35]" "0,1" bitfld.long 0x4 2. "ENABLE_34,Enable (set) for intr_in[34]" "0,1" newline bitfld.long 0x4 1. "ENABLE_33,Enable (set) for intr_in[33]" "0,1" bitfld.long 0x4 0. "ENABLE_32,Enable (set) for intr_in[32]" "0,1" group.long 0x380++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_CLR_REG0" bitfld.long 0x0 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1" bitfld.long 0x0 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1" bitfld.long 0x0 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1" newline bitfld.long 0x0 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1" bitfld.long 0x0 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1" bitfld.long 0x0 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1" newline bitfld.long 0x0 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1" bitfld.long 0x0 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1" bitfld.long 0x0 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1" newline bitfld.long 0x0 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1" bitfld.long 0x0 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1" bitfld.long 0x0 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1" newline bitfld.long 0x0 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1" bitfld.long 0x0 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1" bitfld.long 0x0 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1" newline bitfld.long 0x0 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1" bitfld.long 0x0 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1" bitfld.long 0x0 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1" newline bitfld.long 0x0 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1" bitfld.long 0x0 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1" bitfld.long 0x0 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1" newline bitfld.long 0x0 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1" bitfld.long 0x0 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1" bitfld.long 0x0 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1" newline bitfld.long 0x0 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1" bitfld.long 0x0 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1" bitfld.long 0x0 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1" newline bitfld.long 0x0 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1" bitfld.long 0x0 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1" bitfld.long 0x0 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1" newline bitfld.long 0x0 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1" bitfld.long 0x0 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_CLR_REG1" bitfld.long 0x4 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1" bitfld.long 0x4 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1" bitfld.long 0x4 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1" newline bitfld.long 0x4 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1" bitfld.long 0x4 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1" bitfld.long 0x4 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1" newline bitfld.long 0x4 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1" bitfld.long 0x4 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1" bitfld.long 0x4 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1" newline bitfld.long 0x4 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1" bitfld.long 0x4 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1" bitfld.long 0x4 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1" newline bitfld.long 0x4 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1" bitfld.long 0x4 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1" bitfld.long 0x4 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1" newline bitfld.long 0x4 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1" bitfld.long 0x4 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1" bitfld.long 0x4 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1" newline bitfld.long 0x4 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1" bitfld.long 0x4 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1" bitfld.long 0x4 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1" newline bitfld.long 0x4 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1" bitfld.long 0x4 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1" bitfld.long 0x4 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1" newline bitfld.long 0x4 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1" bitfld.long 0x4 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1" bitfld.long 0x4 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1" newline bitfld.long 0x4 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1" bitfld.long 0x4 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1" bitfld.long 0x4 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1" newline bitfld.long 0x4 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1" bitfld.long 0x4 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1" group.long 0x400++0x3F line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG0" hexmask.long.byte 0x0 24.--27. 1. "CH_MAP_3,Interrupt Channel Map for intr_in[3]" hexmask.long.byte 0x0 16.--19. 1. "CH_MAP_2,Interrupt Channel Map for intr_in[2]" hexmask.long.byte 0x0 8.--11. 1. "CH_MAP_1,Interrupt Channel Map for intr_in[1]" newline hexmask.long.byte 0x0 0.--3. 1. "CH_MAP_0,Interrupt Channel Map for intr_in[0]" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG1" hexmask.long.byte 0x4 24.--27. 1. "CH_MAP_7,Interrupt Channel Map for intr_in[7]" hexmask.long.byte 0x4 16.--19. 1. "CH_MAP_6,Interrupt Channel Map for intr_in[6]" hexmask.long.byte 0x4 8.--11. 1. "CH_MAP_5,Interrupt Channel Map for intr_in[5]" newline hexmask.long.byte 0x4 0.--3. 1. "CH_MAP_4,Interrupt Channel Map for intr_in[4]" line.long 0x8 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG2" hexmask.long.byte 0x8 24.--27. 1. "CH_MAP_11,Interrupt Channel Map for intr_in[11]" hexmask.long.byte 0x8 16.--19. 1. "CH_MAP_10,Interrupt Channel Map for intr_in[10]" hexmask.long.byte 0x8 8.--11. 1. "CH_MAP_9,Interrupt Channel Map for intr_in[9]" newline hexmask.long.byte 0x8 0.--3. 1. "CH_MAP_8,Interrupt Channel Map for intr_in[8]" line.long 0xC "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG3" hexmask.long.byte 0xC 24.--27. 1. "CH_MAP_15,Interrupt Channel Map for intr_in[15]" hexmask.long.byte 0xC 16.--19. 1. "CH_MAP_14,Interrupt Channel Map for intr_in[14]" hexmask.long.byte 0xC 8.--11. 1. "CH_MAP_13,Interrupt Channel Map for intr_in[13]" newline hexmask.long.byte 0xC 0.--3. 1. "CH_MAP_12,Interrupt Channel Map for intr_in[12]" line.long 0x10 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG4" hexmask.long.byte 0x10 24.--27. 1. "CH_MAP_19,Interrupt Channel Map for intr_in[19]" hexmask.long.byte 0x10 16.--19. 1. "CH_MAP_18,Interrupt Channel Map for intr_in[18]" hexmask.long.byte 0x10 8.--11. 1. "CH_MAP_17,Interrupt Channel Map for intr_in[17]" newline hexmask.long.byte 0x10 0.--3. 1. "CH_MAP_16,Interrupt Channel Map for intr_in[16]" line.long 0x14 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG5" hexmask.long.byte 0x14 24.--27. 1. "CH_MAP_23,Interrupt Channel Map for intr_in[23]" hexmask.long.byte 0x14 16.--19. 1. "CH_MAP_22,Interrupt Channel Map for intr_in[22]" hexmask.long.byte 0x14 8.--11. 1. "CH_MAP_21,Interrupt Channel Map for intr_in[21]" newline hexmask.long.byte 0x14 0.--3. 1. "CH_MAP_20,Interrupt Channel Map for intr_in[20]" line.long 0x18 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG6" hexmask.long.byte 0x18 24.--27. 1. "CH_MAP_27,Interrupt Channel Map for intr_in[27]" hexmask.long.byte 0x18 16.--19. 1. "CH_MAP_26,Interrupt Channel Map for intr_in[26]" hexmask.long.byte 0x18 8.--11. 1. "CH_MAP_25,Interrupt Channel Map for intr_in[25]" newline hexmask.long.byte 0x18 0.--3. 1. "CH_MAP_24,Interrupt Channel Map for intr_in[24]" line.long 0x1C "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG7" hexmask.long.byte 0x1C 24.--27. 1. "CH_MAP_31,Interrupt Channel Map for intr_in[31]" hexmask.long.byte 0x1C 16.--19. 1. "CH_MAP_30,Interrupt Channel Map for intr_in[30]" hexmask.long.byte 0x1C 8.--11. 1. "CH_MAP_29,Interrupt Channel Map for intr_in[29]" newline hexmask.long.byte 0x1C 0.--3. 1. "CH_MAP_28,Interrupt Channel Map for intr_in[28]" line.long 0x20 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG8" hexmask.long.byte 0x20 24.--27. 1. "CH_MAP_35,Interrupt Channel Map for intr_in[35]" hexmask.long.byte 0x20 16.--19. 1. "CH_MAP_34,Interrupt Channel Map for intr_in[34]" hexmask.long.byte 0x20 8.--11. 1. "CH_MAP_33,Interrupt Channel Map for intr_in[33]" newline hexmask.long.byte 0x20 0.--3. 1. "CH_MAP_32,Interrupt Channel Map for intr_in[32]" line.long 0x24 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG9" hexmask.long.byte 0x24 24.--27. 1. "CH_MAP_39,Interrupt Channel Map for intr_in[39]" hexmask.long.byte 0x24 16.--19. 1. "CH_MAP_38,Interrupt Channel Map for intr_in[38]" hexmask.long.byte 0x24 8.--11. 1. "CH_MAP_37,Interrupt Channel Map for intr_in[37]" newline hexmask.long.byte 0x24 0.--3. 1. "CH_MAP_36,Interrupt Channel Map for intr_in[36]" line.long 0x28 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG10" hexmask.long.byte 0x28 24.--27. 1. "CH_MAP_43,Interrupt Channel Map for intr_in[43]" hexmask.long.byte 0x28 16.--19. 1. "CH_MAP_42,Interrupt Channel Map for intr_in[42]" hexmask.long.byte 0x28 8.--11. 1. "CH_MAP_41,Interrupt Channel Map for intr_in[41]" newline hexmask.long.byte 0x28 0.--3. 1. "CH_MAP_40,Interrupt Channel Map for intr_in[40]" line.long 0x2C "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG11" hexmask.long.byte 0x2C 24.--27. 1. "CH_MAP_47,Interrupt Channel Map for intr_in[47]" hexmask.long.byte 0x2C 16.--19. 1. "CH_MAP_46,Interrupt Channel Map for intr_in[46]" hexmask.long.byte 0x2C 8.--11. 1. "CH_MAP_45,Interrupt Channel Map for intr_in[45]" newline hexmask.long.byte 0x2C 0.--3. 1. "CH_MAP_44,Interrupt Channel Map for intr_in[44]" line.long 0x30 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG12" hexmask.long.byte 0x30 24.--27. 1. "CH_MAP_51,Interrupt Channel Map for intr_in[51]" hexmask.long.byte 0x30 16.--19. 1. "CH_MAP_50,Interrupt Channel Map for intr_in[50]" hexmask.long.byte 0x30 8.--11. 1. "CH_MAP_49,Interrupt Channel Map for intr_in[49]" newline hexmask.long.byte 0x30 0.--3. 1. "CH_MAP_48,Interrupt Channel Map for intr_in[48]" line.long 0x34 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG13" hexmask.long.byte 0x34 24.--27. 1. "CH_MAP_55,Interrupt Channel Map for intr_in[55]" hexmask.long.byte 0x34 16.--19. 1. "CH_MAP_54,Interrupt Channel Map for intr_in[54]" hexmask.long.byte 0x34 8.--11. 1. "CH_MAP_53,Interrupt Channel Map for intr_in[53]" newline hexmask.long.byte 0x34 0.--3. 1. "CH_MAP_52,Interrupt Channel Map for intr_in[52]" line.long 0x38 "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG14" hexmask.long.byte 0x38 24.--27. 1. "CH_MAP_59,Interrupt Channel Map for intr_in[59]" hexmask.long.byte 0x38 16.--19. 1. "CH_MAP_58,Interrupt Channel Map for intr_in[58]" hexmask.long.byte 0x38 8.--11. 1. "CH_MAP_57,Interrupt Channel Map for intr_in[57]" newline hexmask.long.byte 0x38 0.--3. 1. "CH_MAP_56,Interrupt Channel Map for intr_in[56]" line.long 0x3C "ICSSM_PR1_ICSS_INTC_INTC_SLV_CH_MAP_REG15" hexmask.long.byte 0x3C 24.--27. 1. "CH_MAP_63,Interrupt Channel Map for intr_in[63]" hexmask.long.byte 0x3C 16.--19. 1. "CH_MAP_62,Interrupt Channel Map for intr_in[62]" hexmask.long.byte 0x3C 8.--11. 1. "CH_MAP_61,Interrupt Channel Map for intr_in[61]" newline hexmask.long.byte 0x3C 0.--3. 1. "CH_MAP_60,Interrupt Channel Map for intr_in[60]" group.long 0x800++0xB line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_HINT_MAP_REG0" hexmask.long.byte 0x0 24.--27. 1. "HINT_MAP_3,Host Interrupt Map for Channel 3" hexmask.long.byte 0x0 16.--19. 1. "HINT_MAP_2,Host Interrupt Map for Channel 2" hexmask.long.byte 0x0 8.--11. 1. "HINT_MAP_1,Host Interrupt Map for Channel 1" newline hexmask.long.byte 0x0 0.--3. 1. "HINT_MAP_0,Host Interrupt Map for Channel 0" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_HINT_MAP_REG1" hexmask.long.byte 0x4 24.--27. 1. "HINT_MAP_7,Host Interrupt Map for Channel 7" hexmask.long.byte 0x4 16.--19. 1. "HINT_MAP_6,Host Interrupt Map for Channel 6" hexmask.long.byte 0x4 8.--11. 1. "HINT_MAP_5,Host Interrupt Map for Channel 5" newline hexmask.long.byte 0x4 0.--3. 1. "HINT_MAP_4,Host Interrupt Map for Channel 4" line.long 0x8 "ICSSM_PR1_ICSS_INTC_INTC_SLV_HINT_MAP_REG2" hexmask.long.byte 0x8 8.--11. 1. "HINT_MAP_9,Host Interrupt Map for Channel 9" hexmask.long.byte 0x8 0.--3. 1. "HINT_MAP_8,Host Interrupt Map for Channel 8" rgroup.long 0x900++0x27 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG0" bitfld.long 0x0 31. "NONE_HINT_0,No interrupt pending flag" "0,1" hexmask.long.word 0x0 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG1" bitfld.long 0x4 31. "NONE_HINT_1,No interrupt pending flag" "0,1" hexmask.long.word 0x4 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt" line.long 0x8 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG2" bitfld.long 0x8 31. "NONE_HINT_2,No interrupt pending flag" "0,1" hexmask.long.word 0x8 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt" line.long 0xC "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG3" bitfld.long 0xC 31. "NONE_HINT_3,No interrupt pending flag" "0,1" hexmask.long.word 0xC 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt" line.long 0x10 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG4" bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1" hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt" line.long 0x14 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG5" bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1" hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt" line.long 0x18 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG6" bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1" hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt" line.long 0x1C "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG7" bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1" hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt" line.long 0x20 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG8" bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1" hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt" line.long 0x24 "ICSSM_PR1_ICSS_INTC_INTC_SLV_PRI_HINT_REG9" bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1" hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt" group.long 0xD00++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_POLARITY_REG0" bitfld.long 0x0 31. "POLARITY_31,Polarity for intr_in[31] 0=low" "0: low,?" bitfld.long 0x0 30. "POLARITY_30,Polarity for intr_in[30] 0=low" "0: low,?" bitfld.long 0x0 29. "POLARITY_29,Polarity for intr_in[29] 0=low" "0: low,?" newline bitfld.long 0x0 28. "POLARITY_28,Polarity for intr_in[28] 0=low" "0: low,?" bitfld.long 0x0 27. "POLARITY_27,Polarity for intr_in[27] 0=low" "0: low,?" bitfld.long 0x0 26. "POLARITY_26,Polarity for intr_in[26] 0=low" "0: low,?" newline bitfld.long 0x0 25. "POLARITY_25,Polarity for intr_in[25] 0=low" "0: low,?" bitfld.long 0x0 24. "POLARITY_24,Polarity for intr_in[24] 0=low" "0: low,?" bitfld.long 0x0 23. "POLARITY_23,Polarity for intr_in[23] 0=low" "0: low,?" newline bitfld.long 0x0 22. "POLARITY_22,Polarity for intr_in[22] 0=low" "0: low,?" bitfld.long 0x0 21. "POLARITY_21,Polarity for intr_in[21] 0=low" "0: low,?" bitfld.long 0x0 20. "POLARITY_20,Polarity for intr_in[20] 0=low" "0: low,?" newline bitfld.long 0x0 19. "POLARITY_19,Polarity for intr_in[19] 0=low" "0: low,?" bitfld.long 0x0 18. "POLARITY_18,Polarity for intr_in[18] 0=low" "0: low,?" bitfld.long 0x0 17. "POLARITY_17,Polarity for intr_in[17] 0=low" "0: low,?" newline bitfld.long 0x0 16. "POLARITY_16,Polarity for intr_in[16] 0=low" "0: low,?" bitfld.long 0x0 15. "POLARITY_15,Polarity for intr_in[15] 0=low" "0: low,?" bitfld.long 0x0 14. "POLARITY_14,Polarity for intr_in[14] 0=low" "0: low,?" newline bitfld.long 0x0 13. "POLARITY_13,Polarity for intr_in[13] 0=low" "0: low,?" bitfld.long 0x0 12. "POLARITY_12,Polarity for intr_in[12] 0=low" "0: low,?" bitfld.long 0x0 11. "POLARITY_11,Polarity for intr_in[11] 0=low" "0: low,?" newline bitfld.long 0x0 10. "POLARITY_10,Polarity for intr_in[10] 0=low" "0: low,?" bitfld.long 0x0 9. "POLARITY_9,Polarity for intr_in[9] 0=low" "0: low,?" bitfld.long 0x0 8. "POLARITY_8,Polarity for intr_in[8] 0=low" "0: low,?" newline bitfld.long 0x0 7. "POLARITY_7,Polarity for intr_in[7] 0=low" "0: low,?" bitfld.long 0x0 6. "POLARITY_6,Polarity for intr_in[6] 0=low" "0: low,?" bitfld.long 0x0 5. "POLARITY_5,Polarity for intr_in[5] 0=low" "0: low,?" newline bitfld.long 0x0 4. "POLARITY_4,Polarity for intr_in[4] 0=low" "0: low,?" bitfld.long 0x0 3. "POLARITY_3,Polarity for intr_in[3] 0=low" "0: low,?" bitfld.long 0x0 2. "POLARITY_2,Polarity for intr_in[2] 0=low" "0: low,?" newline bitfld.long 0x0 1. "POLARITY_1,Polarity for intr_in[1] 0=low" "0: low,?" bitfld.long 0x0 0. "POLARITY_0,Polarity for intr_in[0] 0=low" "0: low,?" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_POLARITY_REG1" bitfld.long 0x4 31. "POLARITY_63,Polarity for intr_in[63] 0=low" "0: low,?" bitfld.long 0x4 30. "POLARITY_62,Polarity for intr_in[62] 0=low" "0: low,?" bitfld.long 0x4 29. "POLARITY_61,Polarity for intr_in[61] 0=low" "0: low,?" newline bitfld.long 0x4 28. "POLARITY_60,Polarity for intr_in[60] 0=low" "0: low,?" bitfld.long 0x4 27. "POLARITY_59,Polarity for intr_in[59] 0=low" "0: low,?" bitfld.long 0x4 26. "POLARITY_58,Polarity for intr_in[58] 0=low" "0: low,?" newline bitfld.long 0x4 25. "POLARITY_57,Polarity for intr_in[57] 0=low" "0: low,?" bitfld.long 0x4 24. "POLARITY_56,Polarity for intr_in[56] 0=low" "0: low,?" bitfld.long 0x4 23. "POLARITY_55,Polarity for intr_in[55] 0=low" "0: low,?" newline bitfld.long 0x4 22. "POLARITY_54,Polarity for intr_in[54] 0=low" "0: low,?" bitfld.long 0x4 21. "POLARITY_53,Polarity for intr_in[53] 0=low" "0: low,?" bitfld.long 0x4 20. "POLARITY_52,Polarity for intr_in[52] 0=low" "0: low,?" newline bitfld.long 0x4 19. "POLARITY_51,Polarity for intr_in[51] 0=low" "0: low,?" bitfld.long 0x4 18. "POLARITY_50,Polarity for intr_in[50] 0=low" "0: low,?" bitfld.long 0x4 17. "POLARITY_49,Polarity for intr_in[49] 0=low" "0: low,?" newline bitfld.long 0x4 16. "POLARITY_48,Polarity for intr_in[48] 0=low" "0: low,?" bitfld.long 0x4 15. "POLARITY_47,Polarity for intr_in[47] 0=low" "0: low,?" bitfld.long 0x4 14. "POLARITY_46,Polarity for intr_in[46] 0=low" "0: low,?" newline bitfld.long 0x4 13. "POLARITY_45,Polarity for intr_in[45] 0=low" "0: low,?" bitfld.long 0x4 12. "POLARITY_44,Polarity for intr_in[44] 0=low" "0: low,?" bitfld.long 0x4 11. "POLARITY_43,Polarity for intr_in[43] 0=low" "0: low,?" newline bitfld.long 0x4 10. "POLARITY_42,Polarity for intr_in[42] 0=low" "0: low,?" bitfld.long 0x4 9. "POLARITY_41,Polarity for intr_in[41] 0=low" "0: low,?" bitfld.long 0x4 8. "POLARITY_40,Polarity for intr_in[40] 0=low" "0: low,?" newline bitfld.long 0x4 7. "POLARITY_39,Polarity for intr_in[39] 0=low" "0: low,?" bitfld.long 0x4 6. "POLARITY_38,Polarity for intr_in[38] 0=low" "0: low,?" bitfld.long 0x4 5. "POLARITY_37,Polarity for intr_in[37] 0=low" "0: low,?" newline bitfld.long 0x4 4. "POLARITY_36,Polarity for intr_in[36] 0=low" "0: low,?" bitfld.long 0x4 3. "POLARITY_35,Polarity for intr_in[35] 0=low" "0: low,?" bitfld.long 0x4 2. "POLARITY_34,Polarity for intr_in[34] 0=low" "0: low,?" newline bitfld.long 0x4 1. "POLARITY_33,Polarity for intr_in[33] 0=low" "0: low,?" bitfld.long 0x4 0. "POLARITY_32,Polarity for intr_in[32] 0=low" "0: low,?" group.long 0xD80++0x7 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_TYPE_REG0" bitfld.long 0x0 31. "TYPE_31,Type for intr_in[31] 0=level" "0: level,?" bitfld.long 0x0 30. "TYPE_30,Type for intr_in[30] 0=level" "0: level,?" bitfld.long 0x0 29. "TYPE_29,Type for intr_in[29] 0=level" "0: level,?" newline bitfld.long 0x0 28. "TYPE_28,Type for intr_in[28] 0=level" "0: level,?" bitfld.long 0x0 27. "TYPE_27,Type for intr_in[27] 0=level" "0: level,?" bitfld.long 0x0 26. "TYPE_26,Type for intr_in[26] 0=level" "0: level,?" newline bitfld.long 0x0 25. "TYPE_25,Type for intr_in[25] 0=level" "0: level,?" bitfld.long 0x0 24. "TYPE_24,Type for intr_in[24] 0=level" "0: level,?" bitfld.long 0x0 23. "TYPE_23,Type for intr_in[23] 0=level" "0: level,?" newline bitfld.long 0x0 22. "TYPE_22,Type for intr_in[22] 0=level" "0: level,?" bitfld.long 0x0 21. "TYPE_21,Type for intr_in[21] 0=level" "0: level,?" bitfld.long 0x0 20. "TYPE_20,Type for intr_in[20] 0=level" "0: level,?" newline bitfld.long 0x0 19. "TYPE_19,Type for intr_in[19] 0=level" "0: level,?" bitfld.long 0x0 18. "TYPE_18,Type for intr_in[18] 0=level" "0: level,?" bitfld.long 0x0 17. "TYPE_17,Type for intr_in[17] 0=level" "0: level,?" newline bitfld.long 0x0 16. "TYPE_16,Type for intr_in[16] 0=level" "0: level,?" bitfld.long 0x0 15. "TYPE_15,Type for intr_in[15] 0=level" "0: level,?" bitfld.long 0x0 14. "TYPE_14,Type for intr_in[14] 0=level" "0: level,?" newline bitfld.long 0x0 13. "TYPE_13,Type for intr_in[13] 0=level" "0: level,?" bitfld.long 0x0 12. "TYPE_12,Type for intr_in[12] 0=level" "0: level,?" bitfld.long 0x0 11. "TYPE_11,Type for intr_in[11] 0=level" "0: level,?" newline bitfld.long 0x0 10. "TYPE_10,Type for intr_in[10] 0=level" "0: level,?" bitfld.long 0x0 9. "TYPE_9,Type for intr_in[9] 0=level" "0: level,?" bitfld.long 0x0 8. "TYPE_8,Type for intr_in[8] 0=level" "0: level,?" newline bitfld.long 0x0 7. "TYPE_7,Type for intr_in[7] 0=level" "0: level,?" bitfld.long 0x0 6. "TYPE_6,Type for intr_in[6] 0=level" "0: level,?" bitfld.long 0x0 5. "TYPE_5,Type for intr_in[5] 0=level" "0: level,?" newline bitfld.long 0x0 4. "TYPE_4,Type for intr_in[4] 0=level" "0: level,?" bitfld.long 0x0 3. "TYPE_3,Type for intr_in[3] 0=level" "0: level,?" bitfld.long 0x0 2. "TYPE_2,Type for intr_in[2] 0=level" "0: level,?" newline bitfld.long 0x0 1. "TYPE_1,Type for intr_in[1] 0=level" "0: level,?" bitfld.long 0x0 0. "TYPE_0,Type for intr_in[0] 0=level" "0: level,?" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_TYPE_REG1" bitfld.long 0x4 31. "TYPE_63,Type for intr_in[63] 0=level" "0: level,?" bitfld.long 0x4 30. "TYPE_62,Type for intr_in[62] 0=level" "0: level,?" bitfld.long 0x4 29. "TYPE_61,Type for intr_in[61] 0=level" "0: level,?" newline bitfld.long 0x4 28. "TYPE_60,Type for intr_in[60] 0=level" "0: level,?" bitfld.long 0x4 27. "TYPE_59,Type for intr_in[59] 0=level" "0: level,?" bitfld.long 0x4 26. "TYPE_58,Type for intr_in[58] 0=level" "0: level,?" newline bitfld.long 0x4 25. "TYPE_57,Type for intr_in[57] 0=level" "0: level,?" bitfld.long 0x4 24. "TYPE_56,Type for intr_in[56] 0=level" "0: level,?" bitfld.long 0x4 23. "TYPE_55,Type for intr_in[55] 0=level" "0: level,?" newline bitfld.long 0x4 22. "TYPE_54,Type for intr_in[54] 0=level" "0: level,?" bitfld.long 0x4 21. "TYPE_53,Type for intr_in[53] 0=level" "0: level,?" bitfld.long 0x4 20. "TYPE_52,Type for intr_in[52] 0=level" "0: level,?" newline bitfld.long 0x4 19. "TYPE_51,Type for intr_in[51] 0=level" "0: level,?" bitfld.long 0x4 18. "TYPE_50,Type for intr_in[50] 0=level" "0: level,?" bitfld.long 0x4 17. "TYPE_49,Type for intr_in[49] 0=level" "0: level,?" newline bitfld.long 0x4 16. "TYPE_48,Type for intr_in[48] 0=level" "0: level,?" bitfld.long 0x4 15. "TYPE_47,Type for intr_in[47] 0=level" "0: level,?" bitfld.long 0x4 14. "TYPE_46,Type for intr_in[46] 0=level" "0: level,?" newline bitfld.long 0x4 13. "TYPE_45,Type for intr_in[45] 0=level" "0: level,?" bitfld.long 0x4 12. "TYPE_44,Type for intr_in[44] 0=level" "0: level,?" bitfld.long 0x4 11. "TYPE_43,Type for intr_in[43] 0=level" "0: level,?" newline bitfld.long 0x4 10. "TYPE_42,Type for intr_in[42] 0=level" "0: level,?" bitfld.long 0x4 9. "TYPE_41,Type for intr_in[41] 0=level" "0: level,?" bitfld.long 0x4 8. "TYPE_40,Type for intr_in[40] 0=level" "0: level,?" newline bitfld.long 0x4 7. "TYPE_39,Type for intr_in[39] 0=level" "0: level,?" bitfld.long 0x4 6. "TYPE_38,Type for intr_in[38] 0=level" "0: level,?" bitfld.long 0x4 5. "TYPE_37,Type for intr_in[37] 0=level" "0: level,?" newline bitfld.long 0x4 4. "TYPE_36,Type for intr_in[36] 0=level" "0: level,?" bitfld.long 0x4 3. "TYPE_35,Type for intr_in[35] 0=level" "0: level,?" bitfld.long 0x4 2. "TYPE_34,Type for intr_in[34] 0=level" "0: level,?" newline bitfld.long 0x4 1. "TYPE_33,Type for intr_in[33] 0=level" "0: level,?" bitfld.long 0x4 0. "TYPE_32,Type for intr_in[32] 0=level" "0: level,?" group.long 0x1100++0x27 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG0" bitfld.long 0x0 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x0 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level" line.long 0x4 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG1" bitfld.long 0x4 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x4 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level" line.long 0x8 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG2" bitfld.long 0x8 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x8 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level" line.long 0xC "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG3" bitfld.long 0xC 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0xC 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level" line.long 0x10 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG4" bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level" line.long 0x14 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG5" bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level" line.long 0x18 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG6" bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level" line.long 0x1C "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG7" bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level" line.long 0x20 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG8" bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level" line.long 0x24 "ICSSM_PR1_ICSS_INTC_INTC_SLV_NEST_LEVEL_REG9" bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1" hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level" group.long 0x1500++0x3 line.long 0x0 "ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_HINT_REG0" bitfld.long 0x0 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1" bitfld.long 0x0 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1" bitfld.long 0x0 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1" newline bitfld.long 0x0 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1" bitfld.long 0x0 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1" bitfld.long 0x0 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1" newline bitfld.long 0x0 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1" bitfld.long 0x0 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1" bitfld.long 0x0 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1" newline bitfld.long 0x0 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1" tree.end tree "ICSSM0_ICSSM_RAM_SLV_RAM" base ad:0x48010000 group.long 0x0++0x3 line.long 0x0 "ICSSM_RAM_SLV_RAM_RAM_REG_j,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree "ICSSM0_RAT" tree "ICSSM0_RAT_SLICE0" base ad:0x48008000 rgroup.long 0x0++0x7 line.long 0x0 "RAT_SLICE0_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "RAT_SLICE0_CONFIG,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits" hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses" hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions" group.long 0x804++0x3 line.long 0x0 "RAT_SLICE0_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x820++0x3 line.long 0x0 "RAT_SLICE0_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x824++0x17 line.long 0x0 "RAT_SLICE0_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "RAT_SLICE0_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error." line.long 0x8 "RAT_SLICE0_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "RAT_SLICE0_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits." line.long 0x10 "RAT_SLICE0_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "RAT_SLICE0_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x840++0x13 line.long 0x0 "RAT_SLICE0_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "RAT_SLICE0_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "RAT_SLICE0_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "RAT_SLICE0_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "RAT_SLICE0_EOI_REG,EOI Register." hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" group.long 0x20++0xF line.long 0x0 "RAT_SLICE0_REGION_CTRL_j,The Control for Region a" bitfld.long 0x0 31. "EN,Enable for the Region" "0,1" hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte 1 = 2B 2 = 4B 3 = 8B etc. up to 32 = 4GB." line.long 0x4 "RAT_SLICE0_REGION_BASE_j,The Base Address for Region a. This is the source address for matching to a region." hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size." line.long 0x8 "RAT_SLICE0_REGION_TRANS_L_j,The Translated Lower Address Bits for Region a" hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size." line.long 0xC "RAT_SLICE0_REGION_TRANS_U_j,The Translated Upper Address Bits for Region a" hexmask.long.byte 0xC 0.--3. 1. "UPPER,Translated Upper Address Bits for the Region" tree.end tree "ICSSM0_RAT_SLICE1" base ad:0x48009000 rgroup.long 0x0++0x7 line.long 0x0 "RAT_SLICE1_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "RAT_SLICE1_CONFIG,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 16.--23. 1. "ADDR_WIDTH,Number of address bits" hexmask.long.byte 0x4 8.--15. 1. "ADDRS,Number of addresses" hexmask.long.byte 0x4 0.--7. 1. "REGIONS,Number of regions" group.long 0x804++0x3 line.long 0x0 "RAT_SLICE1_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x820++0x3 line.long 0x0 "RAT_SLICE1_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x824++0x17 line.long 0x0 "RAT_SLICE1_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 4 = RAT." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "RAT_SLICE1_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 1 = Boundary crossing error." line.long 0x8 "RAT_SLICE1_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "RAT_SLICE1_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 12 bits." line.long 0x10 "RAT_SLICE1_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "RAT_SLICE1_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x840++0x13 line.long 0x0 "RAT_SLICE1_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "RAT_SLICE1_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "RAT_SLICE1_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "RAT_SLICE1_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "RAT_SLICE1_EOI_REG,EOI Register." hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" group.long 0x20++0xF line.long 0x0 "RAT_SLICE1_REGION_CTRL_j,The Control for Region a" bitfld.long 0x0 31. "EN,Enable for the Region" "0,1" hexmask.long.byte 0x0 0.--5. 1. "SIZE,Size of the Region in Address Bits. 0 = 1 byte 1 = 2B 2 = 4B 3 = 8B etc. up to 32 = 4GB." line.long 0x4 "RAT_SLICE1_REGION_BASE_j,The Base Address for Region a. This is the source address for matching to a region." hexmask.long 0x4 0.--31. 1. "BASE,Base Address for the Region. It must be aligned to the programmed size." line.long 0x8 "RAT_SLICE1_REGION_TRANS_L_j,The Translated Lower Address Bits for Region a" hexmask.long 0x8 0.--31. 1. "LOWER,Translated Lower Address Bits for the Region. It must be aligned to the programmed size." line.long 0xC "RAT_SLICE1_REGION_TRANS_U_j,The Translated Upper Address Bits for Region a" hexmask.long.byte 0xC 0.--3. 1. "UPPER,Translated Upper Address Bits for the Region" tree.end tree.end tree.end tree "ICSSM_XBAR_INTR" base ad:0x52E03000 rgroup.long 0x0++0x3 line.long 0x0 "ICSSM_XBAR_INTR_PID,Identification register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,Rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "ICSSM_XBAR_INTR_MUXCNTL_j,Interrupt mux control register." bitfld.long 0x0 16. "INT_ENABLE,Interrupt j Output Enable." "0,1" hexmask.long.byte 0x0 0.--6. 1. "MUX_CNTL,Mux Control for Interrupt j." tree.end tree "LIN" base ad:0x0 tree "LIN0" base ad:0x52400000 group.long 0x0++0x1F line.long 0x0 "LIN_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. 0 SCI/LIN module is in held in reset.1 SCI/LIN module is out of reset." "0,1" line.long 0x4 "LIN_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically. 0 No.." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 0 ID filtering using ID-Byte. RECEIVEDID and IDBYTE fields in the LINID register are used for detecting a.." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 0 Classic checksum is used. This checksum is compatible with LIN 1.3 slave nodes. The classic checksum.." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used. 0 The multi-buffer mode is.." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module. 0 LIN mode is disabled; SCI compatibility mode is enabled.1 LIN mode is enabled; SCI compatibility mode is disabled." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Target configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a target or master. 0 SCI-compatible mode: Reserved.LIN.." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function. 0 SCI-compatible mode: Parity disabled; no parity bit is generated during transmission or is expected during reception.LIN mode: ID-parity verification is disabled.1.." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 0 Reserved.1 Must be set to 1 when module is configured.." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 0 SCI-compatible mode: Idle-line mode is used.LIN mode: ID4 and.." "0,1" line.long 0x8 "LIN_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by Writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 0 No effect1 Transmit TDO for wakeup. This bit will be cleared.." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to.." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 0 Interrupt is.." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT. 0 Receiver DMA request is.." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT. 0 Transmit DMA request is.." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is.." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 0 Interrupt is disabled. Writing a 0 to this.." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 0.." "0,1" line.long 0x10 "LIN_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a.." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 0 Receiver DMA request is disabled. Writing a 0 to this bit has no effect.1 Receiver DMA request is.." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 0 Transmit DMA request is disabled. Writing a 0 to this bit has no effect.1 Transmit DMA request is.." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to this bit.." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to.." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a.." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0.." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" line.long 0x14 "LIN_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped.." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 0 Interrupt level mapped to INT0.." "0,1" line.long 0x18 "LIN_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level.." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 0 Interrupt level mapped to.." "0,1" line.long 0x1C "LIN_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the 'Header Reception and Adaptive Baudrate'.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no effect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin. 0 LINTX pin is disabled.1 LINTX pin is enabled." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin. 0 LINRX pin is disabled.1 LINRX pin is enabled." "0,1" line.long 0x8 "LIN_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD is equivalent.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN_LINID,The LINID register contains the identification fields for LIN communication.NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field must be.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Target Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a target task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the 'Header Reception and Adaptive Baudrate' section] of a target module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN_RESERVED_1_j,tbd." group.long 0x90++0x7 line.long 0x0 "LIN_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit] 0 No Delay1 Delay by 1 SCLK2 Delay by 2 SCLK3 Delay by 3 SCLK4.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing. 0 IODFT is disabled1 IODFT is disabled2 IODFT is disabled3 IODFT is disabled4 IODFT is disabled5 IODFT is disabled6.." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path. 0 Digital loopback is enabled.1 Analog loopback.." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. 0 Analog loopback through the transmit pin is.." "0,1" line.long 0x4 "LIN_RESERVED_2_j,tbd." group.long 0xE0++0x3 line.long 0x0 "LIN_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not 0 LIN INT1 line does not generate an interrupt to the PIE.1 LIN INT1 line generates an interrupt.." "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not. 0 LIN INT0 line does not generate an interrupt to the PIE.1 LIN INT0 line generates an interrupt.." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN1" base ad:0x52401000 group.long 0x0++0x1F line.long 0x0 "LIN_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. 0 SCI/LIN module is in held in reset.1 SCI/LIN module is out of reset." "0,1" line.long 0x4 "LIN_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically. 0 No.." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 0 ID filtering using ID-Byte. RECEIVEDID and IDBYTE fields in the LINID register are used for detecting a.." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 0 Classic checksum is used. This checksum is compatible with LIN 1.3 slave nodes. The classic checksum.." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used. 0 The multi-buffer mode is.." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module. 0 LIN mode is disabled; SCI compatibility mode is enabled.1 LIN mode is enabled; SCI compatibility mode is disabled." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Target configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a target or master. 0 SCI-compatible mode: Reserved.LIN.." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function. 0 SCI-compatible mode: Parity disabled; no parity bit is generated during transmission or is expected during reception.LIN mode: ID-parity verification is disabled.1.." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 0 Reserved.1 Must be set to 1 when module is configured.." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 0 SCI-compatible mode: Idle-line mode is used.LIN mode: ID4 and.." "0,1" line.long 0x8 "LIN_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by Writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 0 No effect1 Transmit TDO for wakeup. This bit will be cleared.." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to.." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 0 Interrupt is.." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT. 0 Receiver DMA request is.." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT. 0 Transmit DMA request is.." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is.." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 0 Interrupt is disabled. Writing a 0 to this.." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 0.." "0,1" line.long 0x10 "LIN_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a.." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 0 Receiver DMA request is disabled. Writing a 0 to this bit has no effect.1 Receiver DMA request is.." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 0 Transmit DMA request is disabled. Writing a 0 to this bit has no effect.1 Transmit DMA request is.." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to this bit.." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to.." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a.." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0.." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" line.long 0x14 "LIN_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped.." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 0 Interrupt level mapped to INT0.." "0,1" line.long 0x18 "LIN_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level.." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 0 Interrupt level mapped to.." "0,1" line.long 0x1C "LIN_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the 'Header Reception and Adaptive Baudrate'.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no effect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin. 0 LINTX pin is disabled.1 LINTX pin is enabled." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin. 0 LINRX pin is disabled.1 LINRX pin is enabled." "0,1" line.long 0x8 "LIN_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD is equivalent.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN_LINID,The LINID register contains the identification fields for LIN communication.NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field must be.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Target Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a target task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the 'Header Reception and Adaptive Baudrate' section] of a target module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN_RESERVED_1_j,tbd." group.long 0x90++0x7 line.long 0x0 "LIN_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit] 0 No Delay1 Delay by 1 SCLK2 Delay by 2 SCLK3 Delay by 3 SCLK4.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing. 0 IODFT is disabled1 IODFT is disabled2 IODFT is disabled3 IODFT is disabled4 IODFT is disabled5 IODFT is disabled6.." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path. 0 Digital loopback is enabled.1 Analog loopback.." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. 0 Analog loopback through the transmit pin is.." "0,1" line.long 0x4 "LIN_RESERVED_2_j,tbd." group.long 0xE0++0x3 line.long 0x0 "LIN_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not 0 LIN INT1 line does not generate an interrupt to the PIE.1 LIN INT1 line generates an interrupt.." "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not. 0 LIN INT0 line does not generate an interrupt to the PIE.1 LIN INT0 line generates an interrupt.." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN2" base ad:0x52402000 group.long 0x0++0x1F line.long 0x0 "LIN_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. 0 SCI/LIN module is in held in reset.1 SCI/LIN module is out of reset." "0,1" line.long 0x4 "LIN_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically. 0 No.." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 0 ID filtering using ID-Byte. RECEIVEDID and IDBYTE fields in the LINID register are used for detecting a.." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 0 Classic checksum is used. This checksum is compatible with LIN 1.3 slave nodes. The classic checksum.." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used. 0 The multi-buffer mode is.." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module. 0 LIN mode is disabled; SCI compatibility mode is enabled.1 LIN mode is enabled; SCI compatibility mode is disabled." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Target configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a target or master. 0 SCI-compatible mode: Reserved.LIN.." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function. 0 SCI-compatible mode: Parity disabled; no parity bit is generated during transmission or is expected during reception.LIN mode: ID-parity verification is disabled.1.." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 0 Reserved.1 Must be set to 1 when module is configured.." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 0 SCI-compatible mode: Idle-line mode is used.LIN mode: ID4 and.." "0,1" line.long 0x8 "LIN_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by Writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 0 No effect1 Transmit TDO for wakeup. This bit will be cleared.." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to.." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 0 Interrupt is.." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT. 0 Receiver DMA request is.." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT. 0 Transmit DMA request is.." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is.." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 0 Interrupt is disabled. Writing a 0 to this.." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 0.." "0,1" line.long 0x10 "LIN_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a.." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 0 Receiver DMA request is disabled. Writing a 0 to this bit has no effect.1 Receiver DMA request is.." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 0 Transmit DMA request is disabled. Writing a 0 to this bit has no effect.1 Transmit DMA request is.." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to this bit.." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to.." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a.." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0.." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" line.long 0x14 "LIN_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped.." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 0 Interrupt level mapped to INT0.." "0,1" line.long 0x18 "LIN_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level.." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 0 Interrupt level mapped to.." "0,1" line.long 0x1C "LIN_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the 'Header Reception and Adaptive Baudrate'.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no effect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin. 0 LINTX pin is disabled.1 LINTX pin is enabled." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin. 0 LINRX pin is disabled.1 LINRX pin is enabled." "0,1" line.long 0x8 "LIN_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD is equivalent.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN_LINID,The LINID register contains the identification fields for LIN communication.NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field must be.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Target Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a target task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the 'Header Reception and Adaptive Baudrate' section] of a target module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN_RESERVED_1_j,tbd." group.long 0x90++0x7 line.long 0x0 "LIN_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit] 0 No Delay1 Delay by 1 SCLK2 Delay by 2 SCLK3 Delay by 3 SCLK4.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing. 0 IODFT is disabled1 IODFT is disabled2 IODFT is disabled3 IODFT is disabled4 IODFT is disabled5 IODFT is disabled6.." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path. 0 Digital loopback is enabled.1 Analog loopback.." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. 0 Analog loopback through the transmit pin is.." "0,1" line.long 0x4 "LIN_RESERVED_2_j,tbd." group.long 0xE0++0x3 line.long 0x0 "LIN_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not 0 LIN INT1 line does not generate an interrupt to the PIE.1 LIN INT1 line generates an interrupt.." "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not. 0 LIN INT0 line does not generate an interrupt to the PIE.1 LIN INT0 line generates an interrupt.." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN3" base ad:0x52403000 group.long 0x0++0x1F line.long 0x0 "LIN_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. 0 SCI/LIN module is in held in reset.1 SCI/LIN module is out of reset." "0,1" line.long 0x4 "LIN_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically. 0 No.." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 0 ID filtering using ID-Byte. RECEIVEDID and IDBYTE fields in the LINID register are used for detecting a.." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 0 Classic checksum is used. This checksum is compatible with LIN 1.3 slave nodes. The classic checksum.." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used. 0 The multi-buffer mode is.." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module. 0 LIN mode is disabled; SCI compatibility mode is enabled.1 LIN mode is enabled; SCI compatibility mode is disabled." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Target configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a target or master. 0 SCI-compatible mode: Reserved.LIN.." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function. 0 SCI-compatible mode: Parity disabled; no parity bit is generated during transmission or is expected during reception.LIN mode: ID-parity verification is disabled.1.." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 0 Reserved.1 Must be set to 1 when module is configured.." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 0 SCI-compatible mode: Idle-line mode is used.LIN mode: ID4 and.." "0,1" line.long 0x8 "LIN_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by Writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 0 No effect1 Transmit TDO for wakeup. This bit will be cleared.." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to.." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 0 Interrupt is.." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT. 0 Receiver DMA request is.." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT. 0 Transmit DMA request is.." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is.." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 0 Interrupt is disabled. Writing a 0 to this.." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 0.." "0,1" line.long 0x10 "LIN_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a.." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 0 Receiver DMA request is disabled. Writing a 0 to this bit has no effect.1 Receiver DMA request is.." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 0 Transmit DMA request is disabled. Writing a 0 to this bit has no effect.1 Transmit DMA request is.." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to this bit.." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to.." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a.." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0.." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" line.long 0x14 "LIN_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped.." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 0 Interrupt level mapped to INT0.." "0,1" line.long 0x18 "LIN_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level.." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 0 Interrupt level mapped to.." "0,1" line.long 0x1C "LIN_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the 'Header Reception and Adaptive Baudrate'.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no effect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin. 0 LINTX pin is disabled.1 LINTX pin is enabled." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin. 0 LINRX pin is disabled.1 LINRX pin is enabled." "0,1" line.long 0x8 "LIN_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD is equivalent.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN_LINID,The LINID register contains the identification fields for LIN communication.NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field must be.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Target Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a target task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the 'Header Reception and Adaptive Baudrate' section] of a target module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN_RESERVED_1_j,tbd." group.long 0x90++0x7 line.long 0x0 "LIN_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit] 0 No Delay1 Delay by 1 SCLK2 Delay by 2 SCLK3 Delay by 3 SCLK4.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing. 0 IODFT is disabled1 IODFT is disabled2 IODFT is disabled3 IODFT is disabled4 IODFT is disabled5 IODFT is disabled6.." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path. 0 Digital loopback is enabled.1 Analog loopback.." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. 0 Analog loopback through the transmit pin is.." "0,1" line.long 0x4 "LIN_RESERVED_2_j,tbd." group.long 0xE0++0x3 line.long 0x0 "LIN_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not 0 LIN INT1 line does not generate an interrupt to the PIE.1 LIN INT1 line generates an interrupt.." "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not. 0 LIN INT0 line does not generate an interrupt to the PIE.1 LIN INT0 line generates an interrupt.." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN4" base ad:0x52404000 group.long 0x0++0x1F line.long 0x0 "LIN_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. 0 SCI/LIN module is in held in reset.1 SCI/LIN module is out of reset." "0,1" line.long 0x4 "LIN_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically. 0 No.." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 0 ID filtering using ID-Byte. RECEIVEDID and IDBYTE fields in the LINID register are used for detecting a.." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 0 Classic checksum is used. This checksum is compatible with LIN 1.3 slave nodes. The classic checksum.." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used. 0 The multi-buffer mode is.." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module. 0 LIN mode is disabled; SCI compatibility mode is enabled.1 LIN mode is enabled; SCI compatibility mode is disabled." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Target configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a target or master. 0 SCI-compatible mode: Reserved.LIN.." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function. 0 SCI-compatible mode: Parity disabled; no parity bit is generated during transmission or is expected during reception.LIN mode: ID-parity verification is disabled.1.." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 0 Reserved.1 Must be set to 1 when module is configured.." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 0 SCI-compatible mode: Idle-line mode is used.LIN mode: ID4 and.." "0,1" line.long 0x8 "LIN_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by Writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 0 No effect1 Transmit TDO for wakeup. This bit will be cleared.." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to.." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 0 Interrupt is.." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 0 Interrupt is disabled." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT. 0 Receiver DMA request is.." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT. 0 Transmit DMA request is.." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is.." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 0 Interrupt is disabled. Writing a 0 to this.." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 0 Interrupt is disabled. Writing a 0 to this bit has.." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 0.." "0,1" line.long 0x10 "LIN_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1.." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a.." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 0 Receiver DMA request is disabled. Writing a 0 to this bit has no effect.1 Receiver DMA request is.." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 0 Transmit DMA request is disabled. Writing a 0 to this bit has no effect.1 Transmit DMA request is.." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to this bit.." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1 to.." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing.." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a.." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0.." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 0 Interrupt is disabled. Writing a 0 to this bit has no effect.1 Interrupt is enabled. Writing a 1.." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 0 Interrupt is disabled. Writing a 0 to this bit has no.." "0,1" line.long 0x14 "LIN_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped.." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 0 Interrupt level mapped to INT0.." "0,1" line.long 0x18 "LIN_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0.." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to.." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1 Interrupt level.." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line.1 Interrupt level mapped to INT1.." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 0.." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt.." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 0 Interrupt level mapped to INT0 line.1.." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 0 Interrupt level mapped to INT0 line. Writing a 0 to this bit has no.." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 0 Interrupt level mapped to.." "0,1" line.long 0x1C "LIN_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the 'Header Reception and Adaptive Baudrate'.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the 'Message Filtering and Validation' section for more details. When this flag is.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no effect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin. 0 LINTX pin is disabled.1 LINTX pin is enabled." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin. 0 LINRX pin is disabled.1 LINRX pin is enabled." "0,1" line.long 0x8 "LIN_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0].0:general purpose input pin.1:general-purpose output pin" "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD is equivalent.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN_LINID,The LINID register contains the identification fields for LIN communication.NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field must be.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Target Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a target task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.NOTE: TD is equivalent to Data byte of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the 'Header Reception and Adaptive Baudrate' section] of a target module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN_RESERVED_1_j,tbd." group.long 0x90++0x7 line.long 0x0 "LIN_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit] 0 No Delay1 Delay by 1 SCLK2 Delay by 2 SCLK3 Delay by 3 SCLK4.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing. 0 IODFT is disabled1 IODFT is disabled2 IODFT is disabled3 IODFT is disabled4 IODFT is disabled5 IODFT is disabled6.." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path. 0 Digital loopback is enabled.1 Analog loopback.." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. 0 Analog loopback through the transmit pin is.." "0,1" line.long 0x4 "LIN_RESERVED_2_j,tbd." group.long 0xE0++0x3 line.long 0x0 "LIN_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not 0 LIN INT1 line does not generate an interrupt to the PIE.1 LIN INT1 line generates an interrupt.." "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not. 0 LIN INT0 line does not generate an interrupt to the PIE.1 LIN INT0 line generates an interrupt.." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree.end tree "MCAN" base ad:0x0 tree "MCAN0" tree "MCAN0_CFG" base ad:0x52608000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN0_ECC" base ad:0x52700000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN0_MSG_RAM" base ad:0x52600000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN1" tree "MCAN1_CFG" base ad:0x52618000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN1_ECC" base ad:0x52701000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN1_MSG_RAM" base ad:0x52610000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN2" tree "MCAN2_CFG" base ad:0x52628000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN2_ECC" base ad:0x52702000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN2_MSG_RAM" base ad:0x52620000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN3" tree "MCAN3_CFG" base ad:0x52638000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN3_ECC" base ad:0x52703000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN3_MSG_RAM" base ad:0x52630000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN4" tree "MCAN4_CFG" base ad:0x52648000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN4_ECC" base ad:0x52704000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN4_MSG_RAM" base ad:0x52640000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN5" tree "MCAN5_CFG" base ad:0x52658000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN5_ECC" base ad:0x52705000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN5_MSG_RAM" base ad:0x52650000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN6" tree "MCAN6_CFG" base ad:0x52668000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN6_ECC" base ad:0x52706000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN6_MSG_RAM" base ad:0x52660000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree "MCAN7" tree "MCAN7_CFG" base ad:0x52678000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_SS_PID,Revision Register. The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "CFG_SS_CTRL,Control Register. The Control Register contains general control bits for the MCANSS." bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" newline bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CFG_SS_STAT,Status Register. The Status Register provides general status bits for the MCANSS." bitfld.long 0x0 2. "EN_FDOE,Enable FD configuration. Reflects the value of mcanss_enable_fdoe configuration port" "0,1" newline bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SS_ICS,Interrupt Clear Shadow Register. Write 1 to clear interrupt bits." bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. [ICS - Interrupt Clear Shadow Register]" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CFG_SS_IRS,Interrupt Raw Status Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. [IRS - Interrupt Raw Status Register]" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "CFG_SS_IECS,Interrupt Enable Clear Shadow Register. Write 1 to clear interrupt enable bits." bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. [IECS - Interrupt Enable Clear Shadow Register]" "0,1" group.long 0x18++0x3 line.long 0x0 "CFG_SS_IE,Interrupt Enable Register. Write 1 to set interrupt bits." bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. [IE - Interrupt Enable Register]" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CFG_SS_IES,Interrupt Enable Status Register. Read enabled interrupts." bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. [IES - Interrupt Enable Status]" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_SS_EOI,End Of Interrupt (EOI) Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. For level interrupt signals the EOI register is not functional and must not be used." hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. [E.g. Ext TS is bit 0].Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: 8'h00: EOI value for External TS interrupt 8'h01:.." group.long 0x24++0x3 line.long 0x0 "CFG_SS_EXT_TS_PS,External Timestamp Prescaler Register." hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "CFG_SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register." hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt [EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter]" rgroup.long 0x200++0xB line.long 0x0 "CFG_CREL,Core Release Register. Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" newline hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CFG_ENDN,Endian Register. Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "CFG_CUST,Custom Register." hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x23 line.long 0x0 "CFG_DBTP,Data Bit Timing & Prescaler Register. Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in.." bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 1'b0 = Transmitter Delay Compensation disabled 1'b1 = Transmitter Delay Compensation enabled" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled" newline hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. The actual interpretation by the hardware of this value is such that one.." newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CFG_TEST,Test Register. Test mode selection. Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit." rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 1'b0 = The CAN bus is dominant 1'b1 = The CAN bus is recessive" "0: The CAN bus is dominant,1: The CAN bus is recessive" newline bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 2'b00 = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 2'b01 = Sample Point can be monitored at the MCAN TX pin 2'b10 = Dominant ('0') level at the MCAN TX pin 2'b11 = Recessive.." "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back Mode 1'b0 = Reset value Loopback Mode is disabled 1'b1 = Loopback Mode is enabled(see Test Modes)" "0: Reset value,1: Loopback Mode is enabled" line.long 0x8 "CFG_RWD,RAM Watchdog. Monitors the READY output of the Message RAM." hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." newline hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value Start value of the Message RAM Watchdog Counter. With the reset value of 8'h0 the counter is disabled." line.long 0xC "CFG_CCCR,CC Control Register. Operation mode configuration." bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame(see Tx Handling) . 1'b0 = Transmit pause disabled 1'b1 = Transmit pause enabled" "0: Transmit pause disabled,1: Transmit pause enabled" newline bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration 1'b0 = Edge filtering disabled 1'b1 = Two consecutive dominant tq required to detect an edge for hard synchronization" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.." newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 1'b0 = Protocol exception handling enabled 1'b1 = Protocol exception handling disabled Note: When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0: Protocol exception handling enabled,1: Protocol exception handling disabled Note: When.." newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 1'b0 = Bit rate switching for transmissions disabled 1'b1 = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 1'b0 the MCAN_CCCR[9] BRSE bit is not evaluated." "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled.." newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 1'b0 = FD operation disabled 1'b1 = FD operation enabled" "0: FD operation disabled,1: FD operation enabled" newline bitfld.long 0xC 7. "TEST,Test Mode enable 1'b0 = Normal operation. The MCAN_TEST register holds reset values. 1'b1 = Test Mode. Write access to the MCAN_TEST register enabled" "0: Normal operation,1: Test Mode" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission 1'b0 = Automatic retransmission of messages not transmitted successfully enabled 1'b1 = Automatic retransmission disabled" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0xC 5. "MON,Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 1'b0 = Bus Monitoring Mode is disabled 1'b1 = Bus.." "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled" newline bitfld.long 0xC 4. "CSR,Clock Stop Request 1'b0 = No clock stop is requested 1'b1 = Clock stop requested. When clock stop is requested first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and.." "0: No clock stop is requested,1: Clock stop requested" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 1'b0 = No clock stop acknowledged 1'b1 = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0: No clock stop acknowledged,1: The MCAN module may be set in power down by.." newline bitfld.long 0xC 2. "ASM,Restriced Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation.." "0: Normal CAN operation,1: Restricted Operation Mode active" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 1'b0 = The Host CPU has no write access to the protected configuration registers 1'b1 = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1)" "0: The Host CPU has no write access to the..,1: The Host CPU has write access to the protected.." newline bitfld.long 0xC 0. "INIT,Initialization 1'b0 = Normal Operation 1'b1 = Initialization is started Note: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore.." "0: Normal Operation,1: Initialization is started Note: Due to the.." line.long 0x10 "CFG_NBTP,Nominal Bit Timing & Prescaler Register. Configuration of arbitration phase bit timing. This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "CFG_TSCC,Timestamp Counter Configuration. Timestamp counter prescaler setting. selection of internal/external timestamp vector." hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With.." newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select 2'b00 = Timestamp counter value always 0 2'b01 = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2'b10 = External timestamp counter value used 2'b11 = Same as 2'b00" "0,1,2,3" line.long 0x18 "CFG_TSCV,Timestamp Counter Value." hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01 the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the.." line.long 0x1C "CFG_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the.." "0,1,2,3" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 1'b0 = Timeout Counter disabled 1'b1 = Timeout Counter enabled" "0: Timeout Counter disabled,1: Timeout Counter enabled" line.long 0x20 "CFG_TOCV,Timeout Counter Value. Read/reset timeout counter." hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is.." rgroup.long 0x240++0x7 line.long 0x0 "CFG_ECR,Error Counter Register. State of Rx/Tx Error counter. CAN error logging." hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh;.." newline bitfld.long 0x0 15. "RP,Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "CFG_PSR,Protocol Status Register. CAN protocol controller status. transmitter delay compensation value." hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is in the data phase the number of mtq.." newline bitfld.long 0x4 14. "PXE,Protocol Exception Event 1'b0 = No protocol exception event occurred since last read access 1'b1 = Protocol exception event occurred" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred" newline bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message This bit is set independent of acceptance filtering. 1'b0 = Since this bit was reset by the Host CPU no CAN FD message has been received 1'b1 = Message in CAN FD format with FDF flag set has been received" "0: Since this bit was reset by the Host CPU,1: Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its BRS flag set 1'b1 = Last received CAN FD message had its BRS.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set" newline bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit independent of acceptance filtering. 1'b0 = Last received CAN FD message did not have its ESI flag set 1'b1 = Last received CAN FD message had its ESI.." "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status 1'b0 = The MCAN module is not Bus_Off 1'b1 = The MCAN module is in Bus_Off state" "0: The MCAN module is not Bus_Off,1: The MCAN module is in Bus_Off state" newline bitfld.long 0x4 6. "EW,Warning Status 1'b0 = Both error counters are below the Error_Warning limit of 96 1'b1 = At least one of error counter has reached the Error_Warning limit of 96" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.." newline bitfld.long 0x4 5. "EP,Error Passive 1'b0 = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1'b1 = The MCAN module is in the Error_Passive state" "0: The MCAN module is in the Error_Active state,1: The MCAN module is in the Error_Passive state" newline bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 2'b00 = Synchronizing - node is synchronizing on CAN communication 2'b01 = Idle - node is neither receiver nor transmitter 2'b10 = Receiver - node is operating as receiver 2'b11 = Transmitter -.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to0hwhen a message has been transferred (reception or transmission) without error. 3'b000 = No Error: No error.." "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "CFG_TDCR,Transmitter Delay Comensation Register. Configuration of transmitter delay compensation offset and filter window length." hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq 0h7Fh)." newline hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x250++0xF line.long 0x0 "CFG_IR,Interrupt Register. The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" newline bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" newline bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: i. has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0: No Message RAM access failure occurred,1: Message RAM access failure occurred" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" newline bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" newline bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CFG_IE,Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line." bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" newline bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" newline bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" newline bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x8 "CFG_ILS,Interrupt line select. The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For assigning interrupt to INT0. write 0 to corresponding.." bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" newline bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" newline bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1" newline bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" newline bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" newline bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" newline bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1" newline bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" newline bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" newline bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" newline bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0xC "CFG_ILE,Interrupt line enable Register. Enable/Disable interrupt lines INT0/INT1." bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" newline bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x280++0xB line.long 0x0 "CFG_GFC,Global Filter Configuration. Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages." bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 2'b00 = Accept in Rx FIFO 0 2'b01 = Accept in Rx FIFO 1 2'b10 = Reject 2'b11 = Reject" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 1'b0 = Filter remote frames with 11-bit standard IDs 1'b1 = Reject all remote frames with 11-bit standard IDs" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 1'b0 = Filter remote frames with 29-bit extended IDs 1'b1 = Reject all remote frames with 29-bit extended IDs" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs" line.long 0x4 "CFG_SIDFC,Standard ID Filter Configuration. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard 8'h00 = No standard Message ID filter 8'h01-8'h80 (1-128) = Number of standard Message ID filter elements > 8'h80 (128) = Values greater than 128 are interpreted as 128" newline hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Message RAM Configuration)." line.long 0x8 "CFG_XIDFC,Extended ID Filter Configuration. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages." hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Extended 8'h00 = No extended Message ID filter 8'h01-8'h40 (1-64) = Number of extended Message ID filter elements > 8'h40 (64) = Values greater than 64 are interpreted as 64" newline hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Message RAM Configuration)." group.long 0x290++0x3 line.long 0x0 "CFG_XIDAM,Extended ID and Mask." hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x294++0x3 line.long 0x0 "CFG_HPMS,High Priority Message Status. Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 1'b0 = Standard Filter List 1'b1 = Extended Filter List" "0: Standard Filter List,1: Extended Filter List" newline hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1." newline bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator 2'b00 = No FIFO selected 2'b01 = FIFO message lost 2'b10 = Message stored in FIFO 0 2'b11 = Message stored in FIFO 1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1." group.long 0x298++0xB line.long 0x0 "CFG_NDAT1,New Data 1 register. NewData flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the.." hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 31-0" line.long 0x4 "CFG_NDAT2,New Data 2 register. NewData flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until.." hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 63-32" line.long 0x8 "CFG_RXF0C,Rx FIFO 0 Configuration register. FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 0 blocking mode 1'b1 = FIFO 0 overwrite mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 7'h00 = No Rx FIFO 0 7'h01-7'h40 (1-64) = Number of Rx FIFO 0 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2A4++0x3 line.long 0x0 "CFG_RXF0S,Rx FIFO 0 Status register. FIFO 0 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of.." "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost" newline bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "CFG_RXF0A,Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get.." line.long 0x4 "CFG_RXBC,Rx Buffer Configuration register. Start address of Rx buffer section." hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "CFG_RXF1C,Rx FIFO 1 Configuration register. FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs). 1'b0 = FIFO 1 blocking mode 1'b1 = FIFO 1 overwrite mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" newline hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 7'h00 = Watermark interrupt disabled 7'h01-7'h40 (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 7'h40 (64) = Watermark interrupt disabled" newline hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 7'h00 = No Rx FIFO 1 7'h01-7'h40 (1-64) = Number of Rx FIFO 1 elements > 7'h40 (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1." newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2B4++0x3 line.long 0x0 "CFG_RXF1S,Rx FIFO 1 Status register. FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of.." "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost" newline bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "CFG_RXF1A,Rx FIFO 1 Acknowledge register. FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get.." line.long 0x4 "CFG_RXESC,Rx Buffer/FIFO Element Size Configuration register. Configure data field size for storage of accepted frames." bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "CFG_TXBC,Tx Buffer Configuration register. Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode 1'b0 = Tx FIFO operation 1'b1 = Tx Queue operation" "0: Tx FIFO operation,1: Tx Queue operation" newline hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 6'h00 = No Tx FIFO/Queue 6'b01-6'h20 (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 6'h00 = No Dedicated Tx Buffers 6'h01-6'h20 (1-32) = Number of Dedicated Tx Buffers > 6'h20 (32) = Values greater than 32 are interpreted as 32" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32." line.long 0x4 "CFG_TXFQS,Tx FIFO/Queue Status register. Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of.." bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1'b1). Note: In case of mixed configurations where.." group.long 0x2C8++0x3 line.long 0x0 "CFG_TXESC,Tx Buffer Element Size Configuration register. ConfigurationConfigure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 3'b000 = 8 byte data field 3'b001 = 12 byte data field 3'b010 = 16 byte data field 3'b011 = 20 byte data field 3'b100 = 24 byte data field 3'b101 = 32 byte data field 3'b110 = 48 byte data field 3'b111 = 64 byte data field.." "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "CFG_TXBRP,Tx Buffer Request Pending register. PendingTx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested.." hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "CFG_TXBAR,Tx Buffer Add Request register. Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for.." hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "CFG_TXBCR,Tx Buffer Cancellation Request register. Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This.." hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "CFG_TXBTO,Tx Buffer Transmission Occurred register. Signals successful transmissions. set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is.." hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "CFG_TXBCF,Tx Buffer Cancellation Finished register. Signals successful transmit cancellation. set when corresponding MCAN_TXBRP flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the.." hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x7 line.long 0x0 "CFG_TXBTIE,Tx Buffer Transmission Interrupt Enable register. Enable transmit interrupts for selected Tx buffers." hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "CFG_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable register. Enable cancellation finished interrupts for selected Tx buffers." hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0x2F0++0x3 line.long 0x0 "CFG_TXEFC,Tx Event FIFO Configuration register. Tx event FIFO watermark. size and start address." hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 6'h00 = Watermark interrupt disabled 6'h01-6'h20 (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 6'h20 (32) = Watermark interrupt disabled" newline hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 6'h00 = Tx Event FIFO disabled 6'h01-6'h20 (1-32) = Number of Tx Event FIFO elements > 6'h20 (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1." newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Message RAM Configuration)." rgroup.long 0x2F4++0x7 line.long 0x0 "CFG_TXEFS,Tx Event FIFO Status register. Tx event FIFO element lost/full indication. put index. get index. and fill level." bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset this bit is also reset. 1'b0 = No Tx Event FIFO element lost 1'b1 = Tx Event FIFO element lost also set after write attempt.." "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost" newline bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "CFG_TXEFA,Tx Event FIFO Acknowledge register. Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event.." tree.end tree "MCAN7_ECC" base ad:0x52707000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_REV,Aggregator Revision Register. The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_VECTOR,ECC RAM ID to select which ECC RAM to control or read status from." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_STAT,Contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "ECC_CTRL,ECC Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK,TI Internal : Check ParityTI Internal : Check timeout" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "ECC_ERR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_ERR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_ERR_STAT1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_ERR_STAT2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_ERR_STAT3,ECC Error Status3 Register." hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "ECC_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing Reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "ECC_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have.." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,2-bit saturating counter of the number of parity errors that have occurred since last cleared. 2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have.." "0,1,2,3" line.long 0xC "ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout.." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields." "0,1,2,3" tree.end tree "MCAN7_MSG_RAM" base ad:0x52670000 group.long 0x0++0x3 line.long 0x0 "MSG_RAM_START,START." hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" group.long 0x10FFC++0x3 line.long 0x0 "MSG_RAM_END,END." hexmask.long 0x0 0.--31. 1. "END,MCAN message mem End address" tree.end tree.end tree.end tree "MCRC0" base ad:0x35000000 group.long 0x0++0x3 line.long 0x0 "MSS_MCRC_CRC_CTRL0,Contains sw reset control bit to reset PSA." bitfld.long 0x0 31. "CH4_CRC_SEL2,Refer 'CH4_DW_SEL' field description" "0,1" newline bitfld.long 0x0 30. "CH4_BYTE_SWAP,BYTE SWAP Enable across Data Size0 Byte Swap Disabled1 Byte Swap enabled." "0,1" newline bitfld.long 0x0 29. "CH4_BIT_SWAP,msb/lsb SWAPPING 0 msb [most significant bit First]1 lsb [least significant bit First]" "0,1" newline bitfld.long 0x0 27.--28. "CH4_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]}000 CRC-64001 - CRC-16010 CRC-32100 - VDA CAN SAE-J1850 CRC-8101 - H2F Autosar 4.0110 - CASTAGNOLI iSCSI111 / 011 - E2E Profile 4" "0,1,2,3" newline bitfld.long 0x0 25.--26. "CH4_DW_SEL,CRC Data Size select.000 64 bit Data Size001 - 16 bit Data Size010 32 Bit Data Size" "0,1,2,3" newline bitfld.long 0x0 24. "CH4_PSA_SWREST,Channel 4 PSA Software Reset. When set the PSA SignatureRegister is reset to all zero. Software reset does not reset softwarereset bit itself. Therefore CPU is required to clear this bit by Writinga 0.0 = PSA Signature Register not.." "0: PSA Signature Register not reset1 = PSA..,?" newline bitfld.long 0x0 23. "CH3_CRC_SEL2,Refer 'CH3_DW_SEL' field description" "0,1" newline bitfld.long 0x0 22. "CH3_BYTE_SWAP,BYTE SWAP Enable across Data Size0 Byte Swap Disabled1 Byte Swap enabled." "0,1" newline bitfld.long 0x0 21. "CH3_BIT_SWAP,msb/lsb SWAPPING 0 msb [most significant bit First]1 lsb [least significant bit First]" "0,1" newline bitfld.long 0x0 19.--20. "CH3_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]}000 CRC-64001 - CRC-16010 CRC-32100 - VDA CAN SAE-J1850 CRC-8101 - H2F Autosar 4.0110 - CASTAGNOLI iSCSI111 / 011 - E2E Profile 4" "0,1,2,3" newline bitfld.long 0x0 17.--18. "CH3_DW_SEL,CRC Data Size select.000 64 bit Data Size001 - 16 bit Data Size010 32 Bit Data Size" "0,1,2,3" newline bitfld.long 0x0 16. "CH3_PSA_SWREST,Channel 3 PSA Software Reset. When set the PSA SignatureRegister is reset to all zero. Software reset does not reset softwarereset bit itself. Therefore CPU is required to clear this bit by Writinga 0.0 = PSA Signature Register not.." "0: PSA Signature Register not reset1 = PSA..,?" newline bitfld.long 0x0 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1" newline bitfld.long 0x0 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size0 Byte Swap Disabled1 Byte Swap enabled." "0,1" newline bitfld.long 0x0 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 msb [most significant bit First]1 lsb [least significant bit First]" "0,1" newline bitfld.long 0x0 11.--12. "CH2_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]}000 CRC-64001 - CRC-16010 CRC-32100 - VDA CAN SAE-J1850 CRC-8101 - H2F Autosar 4.0110 - CASTAGNOLI iSCSI111 / 011 - E2E Profile 4" "0,1,2,3" newline bitfld.long 0x0 9.--10. "CH2_DW_SEL,CRC Data Size select.000 64 bit Data Size001 - 16 bit Data Size010 32 Bit Data Size" "0,1,2,3" newline bitfld.long 0x0 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset. When set the PSA SignatureRegister is reset to all zero. Software reset does not reset softwarereset bit itself. Therefore CPU is required to clear this bit by Writinga 0.0 = PSA Signature Register not.." "0: PSA Signature Register not reset1 = PSA..,?" newline bitfld.long 0x0 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1" newline bitfld.long 0x0 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size0 Byte Swap Disabled1 Byte Swap enabled." "0,1" newline bitfld.long 0x0 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 msb [most significant bit First]1 lsb [least significant bit First]" "0,1" newline bitfld.long 0x0 3.--4. "CH1_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]}000 CRC-64001 - CRC-16010 CRC-32100 - VDA CAN SAE-J1850 CRC-8101 - H2F Autosar 4.0110 - CASTAGNOLI iSCSI111 / 011 - E2E Profile 4" "0,1,2,3" newline bitfld.long 0x0 1.--2. "CH1_DW_SEL,CRC Data Size select.000 64 bit Data Size001 - 16 bit Data Size010 32 Bit Data Size" "0,1,2,3" newline bitfld.long 0x0 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset. When set the PSA SignatureRegister is reset to all zero. Software reset does not reset softwarereset bit itself. Therefore CPU is required to clear this bit by Writinga 0.0 = PSA Signature Register not.." "0: PSA Signature Register not reset1 = PSA..,?" group.long 0x8++0x3 line.long 0x0 "MSS_MCRC_CRC_CTRL1,Contains power down control bit." hexmask.long 0x0 1.--31. 1. "RESERVED1" newline bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put inpower down mode.0 = MCRC is not in power down mode1 = MCRC is in power down mode" "0: MCRC is not in power down mode1 = MCRC is in..,?" group.long 0x10++0x3 line.long 0x0 "MSS_MCRC_CRC_CTRL2,Contains channel mode. data trace enable control bits." hexmask.long.byte 0x0 26.--31. 1. "RESERVED5" newline bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode:0 0 = Data Capture mode. In this mode the PSA Signature Registerdoes not compress data when it is written. Any datawritten to PSA Signature Register is simply captured byPSA Signature Register without any compression. Thismode.." "0: reserved1,1: Full-CPU mode,?,?" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED4" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode:0 0 = Data Capture mode. In this mode the PSA Signature Registerdoes not compress data when it is written. Any datawritten to PSA Signature Register is simply captured byPSA Signature Register without any compression. Thismode.." "0: reserved1,1: Full-CPU mode,?,?" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED3" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode:0 0 = Data Capture mode. In this mode the PSA Signature Registerdoes not compress data when it is written. Any datawritten to PSA Signature Register is simply captured byPSA Signature Register without any compression. Thismode.." "0: reserved1,1: Full-CPU mode,?,?" newline rbitfld.long 0x0 5.--7. "RESERVED2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable. When set the channel is put intodata trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data onthese buses is compressed by the PSA Signature Register. Whensuspend.." "0: Data Trace disable1 = Data Trace enable,?" newline rbitfld.long 0x0 2.--3. "RESERVED1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode:0 0 = Data Capture mode. In this mode the PSA Signature Registerdoes not compress data when it is written. Any datawritten to PSA Signature Register is simply captured byPSA Signature Register without any compression. Thismode.." "0: reserved1,1: Full-CPU mode,?,?" group.long 0x18++0x3 line.long 0x0 "MSS_MCRC_CRC_INTS,CRC interrupt enable register. Write one to a bit to enable a interrupt." rbitfld.long 0x0 29.--31. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIMEOUTENS,Channel 4 Timeout Interrupt Enable Bit. Writing a one to thisbit enable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt enable,?" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit. Writing a one tothis bit enable the underrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt enable,?" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit. Writing a one to thisbit enable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun Interrupt.." "0: Has no effect1 = Overrun Interrupt enable,?" newline bitfld.long 0x0 25. "CH4_CRCFAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to thisbit enable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt enable,?" newline hexmask.long.byte 0x0 21.--24. 1. "RESERVED4" newline bitfld.long 0x0 20. "CH3_TIMEOUTENS,Channel 3 Timeout Interrupt Enable Bit. Writing a one to thisbit enable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt enable,?" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit. Writing a one tothis bit enable the underrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt enable,?" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit. Writing a one to thisbit enable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun Interrupt.." "0: Has no effect1 = Overrun Interrupt enable,?" newline bitfld.long 0x0 17. "CH3_CRCFAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to thisbit enable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt enable,?" newline hexmask.long.byte 0x0 13.--16. 1. "RESERVED3" newline bitfld.long 0x0 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit. Writing a one to thisbit enable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt enable,?" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit. Writing a one tothis bit enable the underrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt enable,?" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit. Writing a one to thisbit enable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun Interrupt.." "0: Has no effect1 = Overrun Interrupt enable,?" newline bitfld.long 0x0 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to thisbit enable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt enable,?" newline hexmask.long.byte 0x0 5.--8. 1. "RESERVED2" newline bitfld.long 0x0 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit. Writing a one to thisbit enable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt enable,?" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit. Writing a one tothis bit enable the underrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt enable,?" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit. Writing a one to thisbit enable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun Interrupt.." "0: Has no effect1 = Overrun Interrupt enable,?" newline bitfld.long 0x0 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to thisbit enable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt enable,?" newline rbitfld.long 0x0 0. "RESERVED1" "0,1" group.long 0x20++0x3 line.long 0x0 "MSS_MCRC_CRC_INTR,CRC interrupt disable register. Write one to a bit to disable a interrupt." rbitfld.long 0x0 29.--31. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIMEOUTENR,Channel 4 Timeout Interrupt Disable Bit. Writing a one to thisbit disable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt disable,?" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit. Writing a one tothis bit disable the underrun interrupt. Writing a zero has noeffect. Reading from this bit gives the status [interrupt enable/dis-able].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt disable,?" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit. Writing a one to thisbit disable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun.." "0: Has no effect1 = Overrun Interrupt disable,?" newline bitfld.long 0x0 25. "CH4_CRCFAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to thisbit disable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt disable,?" newline hexmask.long.byte 0x0 21.--24. 1. "RESERVED4" newline bitfld.long 0x0 20. "CH3_TIMEOUTENR,Channel 3 Timeout Interrupt Disable Bit. Writing a one to thisbit disable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt disable,?" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit. Writing a one tothis bit disable the underrun interrupt. Writing a zero has noeffect. Reading from this bit gives the status [interrupt enable/dis-able].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt disable,?" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit. Writing a one to thisbit disable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun.." "0: Has no effect1 = Overrun Interrupt disable,?" newline bitfld.long 0x0 17. "CH3_CRCFAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to thisbit disable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt disable,?" newline hexmask.long.byte 0x0 13.--16. 1. "RESERVED3" newline bitfld.long 0x0 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit. Writing a one to thisbit disable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt disable,?" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit. Writing a one tothis bit disable the underrun interrupt. Writing a zero has noeffect. Reading from this bit gives the status [interrupt enable/dis-able].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt disable,?" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit. Writing a one to thisbit disable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun.." "0: Has no effect1 = Overrun Interrupt disable,?" newline bitfld.long 0x0 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to thisbit disable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt disable,?" newline hexmask.long.byte 0x0 5.--8. 1. "RESERVED2" newline bitfld.long 0x0 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit. Writing a one to thisbit disable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt disable,?" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit. Writing a one tothis bit disable the underrun interrupt. Writing a zero has noeffect. Reading from this bit gives the status [interrupt enable/dis-able].User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt disable,?" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit. Writing a one to thisbit disable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = Overrun.." "0: Has no effect1 = Overrun Interrupt disable,?" newline bitfld.long 0x0 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to thisbit disable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status [interrupt enable/disable].User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt disable,?" newline rbitfld.long 0x0 0. "RESERVED1" "0,1" group.long 0x28++0x3 line.long 0x0 "MSS_MCRC_CRC_STATUS_REG,CRC interrupt status register. Contains interrupt flags for different types of interrupt." rbitfld.long 0x0 29.--31. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIMEOUT,Channel 4 CRC Timeout Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode.0 = No timeout interrupt is active1 = Timeout interrupt is active" "0: No timeout interrupt is active1 = Timeout..,?" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode only0 = No underrun interrupt is active1 = Underrun interrupt is active" "0,1" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode0 = No overrun interrupt is active1 = Overrun interrupt is active" "0,1" newline bitfld.long 0x0 25. "CH4_CRCFAIL,Channel 4 CRC Compare Fail Status Flag. This bit is clearedby Writing a 1 to it only. Writing 0 has no effect. This bit is setin AUTO mode only.0 = No CRC compare fail interrupt is active1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active1 = CRC..,?" newline hexmask.long.byte 0x0 21.--24. 1. "RESERVED4" newline bitfld.long 0x0 20. "CH3_TIMEOUT,Channel 3 CRC Timeout Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode.0 = No timeout interrupt is active1 = Timeout interrupt is active" "0: No timeout interrupt is active1 = Timeout..,?" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode only0 = No underrun interrupt is active1 = Underrun interrupt is active" "0,1" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode0 = No overrun interrupt is active1 = Overrun interrupt is active" "0,1" newline bitfld.long 0x0 17. "CH3_CRCFAIL,Channel 3 CRC Compare Fail Status Flag. This bit is clearedby Writing a 1 to it only. Writing 0 has no effect. This bit is setin AUTO mode only.0 = No CRC compare fail interrupt is active1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active1 = CRC..,?" newline hexmask.long.byte 0x0 13.--16. 1. "RESERVED3" newline bitfld.long 0x0 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode.0 = No timeout interrupt is active1 = Timeout interrupt is active" "0: No timeout interrupt is active1 = Timeout..,?" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode only0 = No underrun interrupt is active1 = Underrun interrupt is active" "0,1" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode0 = No overrun interrupt is active1 = Overrun interrupt is active" "0,1" newline bitfld.long 0x0 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag. This bit is clearedby Writing a 1 to it only. Writing 0 has no effect. This bit is setin AUTO mode only.0 = No CRC compare fail interrupt is active1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active1 = CRC..,?" newline hexmask.long.byte 0x0 5.--8. 1. "RESERVED2" newline bitfld.long 0x0 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode.0 = No timeout interrupt is active1 = Timeout interrupt is active" "0: No timeout interrupt is active1 = Timeout..,?" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode only0 = No underrun interrupt is active1 = Underrun interrupt is active" "0,1" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag. This bit is cleared byWriting a 1 to it only. Writing 0 has no effect. This bit is set inAUTO mode0 = No overrun interrupt is active1 = Overrun interrupt is active" "0,1" newline bitfld.long 0x0 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag. This bit is clearedby Writing a 1 to it only. Writing 0 has no effect. This bit is setin AUTO mode only.0 = No CRC compare fail interrupt is active1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active1 = CRC..,?" newline rbitfld.long 0x0 0. "RESERVED1" "0,1" group.long 0x30++0x3 line.long 0x0 "MSS_MCRC_CRC_INT_OFFSET_REG,Register indicates highest priority pending interrupt vector address." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 0.--7. 1. "OFSTREG,CRC Interrupt Offset. This register indicates the highest prioritypending interrupt vector address. Reading the offset register auto-matically clear the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "MSS_MCRC_CRC_BUSY,Register indicates CRC busy flag for each channel." hexmask.long.byte 0x0 25.--31. 1. "RESERVED4" newline bitfld.long 0x0 24. "CH4_BUSY,Ch4_BUSY. During AUTO mode the busy flag is set when thefirst data pattern of the block is compressed and remains set untilthe the last data pattern of the block is compressed. The flag iscleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED3" newline bitfld.long 0x0 16. "CH3_BUSY,Ch3_BUSY. During AUTO mode the busy flag is set when thefirst data pattern of the block is compressed and remains set untilthe the last data pattern of the block is compressed. The flag iscleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED2" newline bitfld.long 0x0 8. "CH2_BUSY,Ch2_BUSY. During AUTO mode the busy flag is set when thefirst data pattern of the block is compressed and remains set untilthe the last data pattern of the block is compressed. The flag iscleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED1" newline bitfld.long 0x0 0. "CH1_BUSY,CH1_BUSY. During AUTO mode the busy flag is set when thefirst data pattern of the block is compressed and remains set untilthe the last data pattern of the block is compressed. The flag iscleared when the last data pattern of the block is.." "0,1" group.long 0x40++0x13 line.long 0x0 "MSS_MCRC_CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count." hexmask.long.word 0x0 20.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register con-tains the number of data patterns in one sector to be compressedbefore a CRC is performed." line.long 0x4 "MSS_MCRC_CRC_SCOUNT_REG1,Channel 1 preload register for the sector count." hexmask.long.word 0x4 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register con-tains the number of sectors in one block of memory." line.long 0x8 "MSS_MCRC_CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure." hexmask.long.word 0x8 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode thisregister contains the current sector number of which the signatureverification fails. The sector counter is a free running up counter.When a sector fails the erroneous sector number is.." line.long 0xC "MSS_MCRC_CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer." hexmask.long.byte 0xC 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. Thisregister contains the number of clock cycles within which theDMA must transfer the next block of data patterns." line.long 0x10 "MSS_MCRC_CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time." hexmask.long.byte 0x10 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis-ter. This register contains the number of clock cycles withinwhich the CRC for an entire block needs to complete before atimeout interrupt is generated." group.long 0x60++0xF line.long 0x0 "MSS_MCRC_PSA_SIGREGL1,Channel 1 PSA signature low register." hexmask.long 0x0 0.--31. 1. "PSASIG1_31_0,Channel 1 PSA Signature Low Register. This register containsthe value stored at PSASIG1[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SIGREGH1,Channel 1 PSA signature high register." hexmask.long 0x4 0.--31. 1. "PSA_SIG1_63_32,Channel 1 PSA Signature High Register. This register containsthe value stored at PSASIG1[63:32] register." line.long 0x8 "MSS_MCRC_CRC_REGL1,Channel 1 CRC value low register." hexmask.long 0x8 0.--31. 1. "CRC1_31_0,Channel 1 CRC Value Low Register. This register contains thecurrent known good signature value stored at CRC1[31:0] regis-ter." line.long 0xC "MSS_MCRC_CRC_REGH1,Channel 1 CRC value high register." hexmask.long 0xC 0.--31. 1. "CRC1_63_32,Channel 1 CRC Value High Register. This register contains thecurrent known good signature value stored at CRC1[63:32] regis-ter." rgroup.long 0x70++0xF line.long 0x0 "MSS_MCRC_PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter." hexmask.long 0x0 0.--31. 1. "PSASECSIG1_31_0,Channel 1 PSA Sector Signature Low Register. This registercontains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter." hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This registercontains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "MSS_MCRC_RAW_DATAREGL1,Channel 1 un-compressed raw data low register." hexmask.long 0x8 0.--31. 1. "RAW_DATA1_31_0,Channel 1 Raw Data Low Register. This register contains bit31:0 of the un-compressed raw data." line.long 0xC "MSS_MCRC_RAW_DATAREGH1,Channel 1 un-compressed raw data high register." hexmask.long 0xC 0.--31. 1. "RAW_DATA1_63_32,Channel 1 Raw Data High Register. This register contains bit63:32 of the un-compressed raw data." group.long 0x80++0x13 line.long 0x0 "MSS_MCRC_CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count." hexmask.long.word 0x0 20.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register. This register con-tains the number of data patterns in one sector to be compressedbefore a CRC is performed." line.long 0x4 "MSS_MCRC_CRC_SCOUNT_REG2,Channel 2 preload register for the sector count." hexmask.long.word 0x4 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register con-tains the number of sectors in one block of memory." line.long 0x8 "MSS_MCRC_CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure." hexmask.long.word 0x8 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode thisregister contains the current sector number of which the signatureverification fails. The sector counter is a free running up counter.When a sector fails the erroneous sector number is.." line.long 0xC "MSS_MCRC_CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer." hexmask.long.byte 0xC 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. Thisregister contains the number of clock cycles within which theDMA must transfer the next block of data patterns." line.long 0x10 "MSS_MCRC_CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time." hexmask.long.byte 0x10 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis-ter. This register contains the number of clock cycles withinwhich the CRC for an entire block needs to complete before atimeout interrupt is generated." group.long 0xA0++0xF line.long 0x0 "MSS_MCRC_PSA_SIGREGL2,Channel 2 PSA signature low register." hexmask.long 0x0 0.--31. 1. "PSASIG2_31_0,Channel 2 PSA Signature Low Register. This register containsthe value stored at PSASIG2[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SIGREGH2,Channel 2 PSA signature high register." hexmask.long 0x4 0.--31. 1. "PSA_SIG2_63_32,Channel 2 PSA Signature High Register. This register containsthe value stored at PSASIG2[63:32] register." line.long 0x8 "MSS_MCRC_CRC_REGL2,Channel 2 CRC value low register." hexmask.long 0x8 0.--31. 1. "CRC2_31_0,Channel 2 CRC Value Low Register. This register contains thecurrent known good signature value stored at CRC2[31:0] regis-ter." line.long 0xC "MSS_MCRC_CRC_REGH2,Channel 2 CRC value high register." hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains thecurrent known good signature value stored at CRC2[63:32] regis-ter." rgroup.long 0xB0++0xF line.long 0x0 "MSS_MCRC_PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter." hexmask.long 0x0 0.--31. 1. "PSASECSIG2_31_0,Channel 2 PSA Sector Signature Low Register. This registercontains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter." hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This registercontains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MSS_MCRC_RAW_DATAREGL2,Channel 2 un-compressed raw data low register." hexmask.long 0x8 0.--31. 1. "RAW_DATA2_31_0,Channel 2 Raw Data Low Register. This register contains bit31:0 of the un-compressed raw data." line.long 0xC "MSS_MCRC_RAW_DATAREGH2,Channel 2 un-compressed raw data high Register." hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit63:32 of the un-compressed raw data." group.long 0xC0++0x13 line.long 0x0 "MSS_MCRC_CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count." hexmask.long.word 0x0 20.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register con-tains the number of data patterns in one sector to be compressedbefore a CRC is performed." line.long 0x4 "MSS_MCRC_CRC_SCOUNT_REG3,Channel 3 preload register for the sector count." hexmask.long.word 0x4 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register con-tains the number of sectors in one block of memory." line.long 0x8 "MSS_MCRC_CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure." hexmask.long.word 0x8 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode thisregister contains the current sector number of which the signatureverification fails. The sector counter is a free running up counter.When a sector fails the erroneous sector number is.." line.long 0xC "MSS_MCRC_CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer." hexmask.long.byte 0xC 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. Thisregister contains the number of clock cycles within which theDMA must transfer the next block of data patterns." line.long 0x10 "MSS_MCRC_CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time." hexmask.long.byte 0x10 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Regis-ter. This register contains the number of clock cycles withinwhich the CRC for an entire block needs to complete before atimeout interrupt is generated." group.long 0xE0++0xF line.long 0x0 "MSS_MCRC_PSA_SIGREGL3,Channel 3 PSA signature low register." hexmask.long 0x0 0.--31. 1. "PSASIG3_31_0,Channel 3 PSA Signature Low Register. This register containsthe value stored at PSASIG2[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SIGREGH3,Channel 3 PSA signature high register." hexmask.long 0x4 0.--31. 1. "PSA_SIG3_63_32,Channel 3 PSA Signature High Register. This register containsthe value stored at PSASIG2[63:32] register." line.long 0x8 "MSS_MCRC_CRC_REGL3,Channel 3 CRC value low register." hexmask.long 0x8 0.--31. 1. "CRC3_31_0,Channel 3 CRC Value Low Register. This register contains thecurrent known good signature value stored at CRC2[31:0] regis-ter." line.long 0xC "MSS_MCRC_CRC_REGH3,Channel 3 CRC value high register." hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains thecurrent known good signature value stored at CRC2[63:32] regis-ter." rgroup.long 0xF0++0xF line.long 0x0 "MSS_MCRC_PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter." hexmask.long 0x0 0.--31. 1. "PSASECSIG3_31_0,Channel 3 PSA Sector Signature Low Register. This registercontains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter." hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This registercontains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MSS_MCRC_RAW_DATAREGL3,Channel 3 un-compressed raw data low register." hexmask.long 0x8 0.--31. 1. "RAW_DATA3_31_0,Channel 3 Raw Data Low Register. This register contains bit31:0 of the un-compressed raw data." line.long 0xC "MSS_MCRC_RAW_DATAREGH3,Channel 3 un-compressed raw data high Register." hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit63:32 of the un-compressed raw data." group.long 0x100++0x13 line.long 0x0 "MSS_MCRC_CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count." hexmask.long.word 0x0 20.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register con-tains the number of data patterns in one sector to be compressedbefore a CRC is performed." line.long 0x4 "MSS_MCRC_CRC_SCOUNT_REG4,Channel 4 preload register for the sector count." hexmask.long.word 0x4 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register con-tains the number of sectors in one block of memory." line.long 0x8 "MSS_MCRC_CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure." hexmask.long.word 0x8 16.--31. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC4,Channel 4 Current Sector ID Register. In AUTO mode thisregister contains the current sector number of which the signatureverification fails. The sector counter is a free running up counter.When a sector fails the erroneous sector number is.." line.long 0xC "MSS_MCRC_CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer." hexmask.long.byte 0xC 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD4,Channel 4 Watchdog Timeout Counter Preload Register. Thisregister contains the number of clock cycles within which theDMA must transfer the next block of data patterns." line.long 0x10 "MSS_MCRC_CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time." hexmask.long.byte 0x10 24.--31. 1. "RESERVED1" newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD4,Channel 4 Block Complete Timeout Counter Preload Regis-ter. This register contains the number of clock cycles withinwhich the CRC for an entire block needs to complete before atimeout interrupt is generated." group.long 0x120++0xF line.long 0x0 "MSS_MCRC_PSA_SIGREGL4,Channel 4 PSA signature low register." hexmask.long 0x0 0.--31. 1. "PSASIG4_31_0,Channel 4 PSA Signature Low Register. This register containsthe value stored at PSASIG2[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SIGREGH4,Channel 4 PSA signature high register." hexmask.long 0x4 0.--31. 1. "PSA_SIG4_63_32,Channel 4 PSA Signature High Register. This register containsthe value stored at PSASIG2[63:32] register." line.long 0x8 "MSS_MCRC_CRC_REGL4,Channel 4 CRC value low register." hexmask.long 0x8 0.--31. 1. "CRC4_31_0,Channel 4 CRC Value Low Register. This register contains thecurrent known good signature value stored at CRC2[31:0] regis-ter." line.long 0xC "MSS_MCRC_CRC_REGH4,Channel 4 CRC value high register." hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register. This register contains thecurrent known good signature value stored at CRC2[63:32] regis-ter." rgroup.long 0x130++0xF line.long 0x0 "MSS_MCRC_PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter." hexmask.long 0x0 0.--31. 1. "PSASECSIG4_31_0,Channel 4 PSA Sector Signature Low Register. This registercontains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MSS_MCRC_PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter." hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This registercontains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MSS_MCRC_RAW_DATAREGL4,Channel 4 un-compressed raw data low register." hexmask.long 0x8 0.--31. 1. "RAW_DATA4_31_0,Channel 4 Raw Data Low Register. This register contains bit31:0 of the un-compressed raw data." line.long 0xC "MSS_MCRC_RAW_DATAREGH4,Channel 4 un-compressed raw data high Register." hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit63:32 of the un-compressed raw data." group.long 0x140++0x3 line.long 0x0 "MSS_MCRC_MCRC_BUS_SEL,Disables either or all tracing of data buses." bitfld.long 0x0 2. "MEN,MEn. Enable/disables the tracing of VBUSM0:Tracing of VBUSM master bus has been disabled1:Tracing of VBUSM master bus has been enabled" "0,1" newline bitfld.long 0x0 1. "DTCMEN,DTCMEn. Enable/disables the tracing of data TCM0:Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled1:Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0,1" newline bitfld.long 0x0 0. "ITCMEN,ITCMEn. Enable/disables the tracing of instruction TCM0:Tracing of ITCM bus has been disabled1:Tracing of ITCM bus has been enabled" "0,1" tree.end tree "MCSPI" base ad:0x0 tree "MCSPI0" base ad:0x52200000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI1" base ad:0x52201000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI2" base ad:0x52202000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI3" base ad:0x52203000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI4" base ad:0x52204000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI5" base ad:0x52205000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI6" base ad:0x52206000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI7" base ad:0x52207000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account 1 FIFO 16 bytes depth2 FIFO 32 bytes depth4 FIFO 64 bytes depth8 FIFO.." bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 0 FIFO not implemented in design1 FIFO and its management implemented in design with depth defined by FFNBYTE.." "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration." bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation suspend.1 IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional] 0 Read 0 - Reset done no pending action0 Write 0 - No Action1 Read 1 - Reset(software or other) ongoing1 Write 1 - Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period 0 Interface and functional clocks may be switched off.1 Interface clock is maintained. Functional clock may be switched off.2 Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0 If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control 0 Wake-up capability is disabled.1 Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0 0 (write) Normal mode1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy 0 Interface clock is free-running.1 Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information ." hexmask.long 0x0 1.--31. 1. "RESERVED_16,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal module reset is ongoing1 Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt ." hexmask.long.word 0x0 18.--31. 1. "RESERVED_8,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is.." "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1.." "0,1" rbitfld.long 0x0 15. "RESERVED_7,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is.." "0,1" rbitfld.long 0x0 11. "RESERVED_9,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" rbitfld.long 0x0 7. "RESERVED_10,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [target mode only] Channel 0 0 Event status bit unchanged1 Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0 0 Read 0 - Event false0 Write 0 - Event status bit Unchanged1 Read 1 - Event is Pending1 Write 1 - Event status bit is reset" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0x4 18.--31. 1. "RESERVED_5,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED_4,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch3 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED_6,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 2 0 Interrupt disabled1 Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED_3,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 1 0 Interrupt disabled1 Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register full or almost full Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register empty or almost empty Interrupt Enable Ch 0 0 Interrupt disabled1 Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x8 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 0 The event is not allowed to wake-up the system even if the global control bit.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_17,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit 0 No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the MCSPI_IRQSTATUS register.1 Force to 1 all status bits of.." "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line 0 Output (as in controller mode)1 Input (as in peripheral mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1] 0 Output1 Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0] 0 Output1 Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit 0 The pin is driven low.1 The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED_11,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access.." "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0 Functional mode1 System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Target 0 Controller - The module generates the SPICLK and SPIEN[3:0].1 Peripheral - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or target mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.1 SPIEN is not used." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only] 0 More than one channel will be used in controller mode.1 Only one channel will be used in controller mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" rbitfld.long 0x14 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 0 Detection enabled only on SPIEN[0]1 Detection enabled only on SPIEN[1]2 Detection enabled only on SPIEN[2]3 Detection.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0[6] EPOL=0 and drives it high when MCSPI_CHCONF_0[6].." "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0x0: Reserved 0x1: Reserved 0x2: Reserved 0x3: The SPI word is 4-bits long 0x4: The SPI word is 5-bits long 0x5: The SPI word is 6-bits long 0x6: The SPI word is 7-bits long 0x7: The SPI word is 8-bits long 0x8: The SPI word.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 0 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 0 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 0 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 0 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 0 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 0 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 0 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio. 0x0: Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_1[6] EPOL=0 and drives it high when MCSPI_CHCONF_1[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 1 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 1 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 1 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 1 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 1 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 1 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 1 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_2[6] EPOL=0 and drives it high when MCSPI_CHCONF_2[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 2 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 2 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 2 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 2 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 2 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 2 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 2 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" rbitfld.long 0x0 30.--31. "RESERVED_0,Read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of4096clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data.1 The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data.1 The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle1 1.5 clock cycles2 2.5 clock cycles3 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL" "0,1" rbitfld.long 0x0 21.--22. "RESERVED_1,Read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_3[6] EPOL=0 and drives it high when MCSPI_CHCONF_3[6].." "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer).1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0 Data line 0 (SPIDAT[0]) selected for reception1 Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission1 No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission1 No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0.." "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0.." "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes 0 Transmit-and-receive mode1 Receive-only mode2 Transmit-only mode3 Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0 Reserved1 Reserved2 Reserved3 The MCSPI word is 4 bits long4 The MCSPI word is 5 bits long5 The MCSPI word is 6 bits long6 The MCSPI word is 7 bits long7 The MCSPI word is 8 bits long8 The.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity 0 SPICLK is held low during the INACTIVE state1 SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK.1 Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x0 7.--31. 1. "RESERVED_2,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 3 FIFO Receive Buffer Full Status 0 FIFO receive buffer is not full1 FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 3 FIFO Receive Buffer Empty Status 0 FIFO receive buffer is not empty1 FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 3 FIFO Transmit Buffer Full Status 0 FIFO transmit buffer is not full1 FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 3 FIFO Transmit Buffer Empty Status 0 FIFO transmit buffer is not empty1 FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 3 End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details 0 This flag is automatically cleared.." "0,1" bitfld.long 0x0 1. "TXS,Channel 3 Transmitter Register Status 0 Register is full.1 Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel 3 Receiver Register Status 0 Register is empty.1 Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED_2,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is4096clock divider ratio 0 Clock.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable 0 Channel i is not active.1 Channel i is active." "0,1" line.long 0x4 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index." hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree.end tree "MMCSD0" base ad:0x48300000 rgroup.long 0x4++0x3 line.long 0x0 "MMC_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any).Actual field format and encoding is up to the module's designer to decide." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "RETMODE,Retention Mode generic parameterThis bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0 Retention mode disabled1 Retention mode enabled" "0,1" hexmask.long.byte 0x0 2.--5. 1. "MEM_SIZE,Memory size for FIFO buffer: 1 Memory of 512 bytes max block length is 512 bytes2 Memory of 1024 bytes max block length is 1024 bytes4 Memory of 2048 bytes max block length is 2048 bytes8 Memory of 4096.." bitfld.long 0x0 1. "MERGE_MEM,Memory merged for FIFO buffer:This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. 0 2 memories instantiated one per data transfer.." "0,1" bitfld.long 0x0 0. "MADMA_EN,Master DMA enabled generic parameter:This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. 0 No Master DMA (ADMA) management supported1 Controller supports ADMA" "0,1" group.long 0x10++0x3 line.long 0x0 "MMC_HL_SYSCONFIG,Clock Management Configuration Register." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode.By definition initiator may generate read/write transaction as long as it is out of STANDBY state. 0 Force-standby mode: local initiator is unconditionally placed in.." "0,1,2,3" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode.By definition target can handle read/write transaction as long as it is out of IDLE state. 0 Force-idle mode: local target's idle state follows (acknowledges) the system's idle.." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal.Functionality NOT implemented in MMCSD. 0 IP module is sensitive to emulation suspend1 IP module is not sensitive to emulation suspend" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. [Optional] 0 No action0 Reset done no pending action1 Reset (software or other) ongoing1 Initiate software reset" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MMC_SYSSTATUS,System Status RegisterThis register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "RESETDONE,Internal Reset MonitoringNote: the debounce clock the system clock [OCP] and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. 0 Internal module reset is on-going1.." "0,1" group.long 0x124++0x13 line.long 0x0 "MMC_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1. R1b for all cards and of R5. R5b and R6 response for cards types SD or SDIO. When a bit MMCHS_CSRE[i] is set to 1. if the.." hexmask.long 0x0 0.--31. 1. "CSRE,Card status response error" line.long 0x4 "MMC_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode. a write into MMCHS_CMD.." hexmask.long.word 0x4 17.--31. 1. "RESERVED" rbitfld.long 0x4 16. "OBI,Out-Of-Band Interrupt [OBI] data value 0 The Out-of-Band Interrupt pin is driven low.1 The Out-of-Band Interrupt pin is driven high." "0,1" rbitfld.long 0x4 15. "SDCD,Card detect input signal [SDCD] data value 0 The card detect pin is driven low.1 The card detect pin is driven high." "0,1" rbitfld.long 0x4 14. "SDWP,Write protect input signal [SDWP] data value 0 The write protect pin SDWP is driven low.1 The write protect pin SDWP is driven high." "0,1" bitfld.long 0x4 13. "WAKD,Wake request output signal data value 0 The pin SWAKEUP is driven low.0 No action. Returns 0.1 The pin SWAKEUP is driven high.1 No action. Returns 1." "0,1" newline bitfld.long 0x4 12. "SSB,Set status bitThis bit must be cleared prior attempting to clear a status bit of the interrupt status register [MMCSD_STAT]. 0 Clear this SSB bitfield. Writing 0 does not clear already set status bits;0 No action. Returns 0.1 No.." "0,1" bitfld.long 0x4 11. "D7D,DAT7 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT7 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 10. "D6D,DAT6 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT6 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 9. "D5D,DAT5 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT5 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 8. "D4D,DAT4 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT4 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" newline bitfld.long 0x4 7. "D3D,DAT3 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT3 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 6. "D2D,DAT2 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT2 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 5. "D1D,DAT1 input/output signal data value 0 If SYSTEST[DDIR] = 0 (output mode direction) the DAT1 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction) no effect.0 If SYSTEST[DDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 4. "D0D,DAT0 input/output signal data value 0 If SYSTEST[DDIR] = 1 (input mode direction) returns the value on the DAT0 line (low). If SYSTEST[DDIR] = 0 (output mode direction) returns 00 If SYSTEST[DDIR] = 0 (output mode.." "0,1" bitfld.long 0x4 3. "DDIR,Control of the DAT[7:0] pins direction. 0 The DAT lines are outputs (host to card)0 No action. Returns 0.1 The DAT lines are inputs (card to host)1 No action. Returns 1." "0,1" newline bitfld.long 0x4 2. "CDAT,CMD input/output signal data value 0 If SYSTEST[CDIR] = 0 (output mode direction) the CMD line is driven low. If SYSTEST[CDIR] = 1 (input mode direction) no effect.0 If SYSTEST[CDIR] = 1 (input mode direction) .." "0,1" bitfld.long 0x4 1. "CDIR,Control of the CMD pin direction. 0 The CMD line is an output (host to card)0 No action. Returns 0.1 The CMD line is an input (card to host)1 No action. Returns 1." "0,1" bitfld.long 0x4 0. "MCKD,MMC clock output signal data value 0 The output clock is driven low.0 No action. Returns 0.1 The output clock is driven high.1 No action. Returns 1." "0,1" line.long 0x8 "MMC_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and.." hexmask.long.word 0x8 22.--31. 1. "RESERVED" bitfld.long 0x8 21. "SDMA_LNE,Target DMA Level/Edge Request:The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCSD_DATA register or late de-assertion request remains active until last allowed data written.." "0,1" bitfld.long 0x8 20. "DMA_MNS,DMA Master or Target selection:When this bit is set and the controller is configured to use the DMA Ocp master interface is used to get datas from system using ADMA2 procedure [direct access to the memory].This option is only available if.." "0,1" bitfld.long 0x8 19. "DDR,Dual Data Rate mode:When this register is set the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC Start end.." "0,1" bitfld.long 0x8 18. "BOOT_CF0,Boot status supported:This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after Writing in MMCSD_CMD. The line is released when this bit field is de-asserted and abort data transfer in.." "0,1" newline bitfld.long 0x8 17. "BOOT_ACK,Book acknowledge received:When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. 0 No acknowledge to be received1 A boot.." "0,1" bitfld.long 0x8 16. "CLKEXTFREE,External clock free running:This register is used to maintain card clock out of transfer transaction to enable target module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCSD_SYSCTL[CEN] is.." "0,1" bitfld.long 0x8 15. "PADEN,Control Power for MMC Lines:This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1] the signal is also combine.." "0,1" bitfld.long 0x8 14. "OBIE,Out-of-Band Interrupt EnableMMC cards only:This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin.The usage of the Out-of-Band signal [OBI] is optional and depends on the system integration. 0 Out-of-Band interrupt.." "0,1" bitfld.long 0x8 13. "OBIP,Out-of-Band Interrupt PolarityMMC cards only:This bit selects the active level of the out-of-band interrupt coming from MMC cards.The usage of the Out-of-Band signal [OBI] is optional and depends on the system integration. 0 Active high level1.." "0,1" newline bitfld.long 0x8 12. "CEATA,CE-ATA control modeMMC cards compliant with CE-ATA:By default this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. 0 Standard MMC/SD/SDIO.." "0,1" bitfld.long 0x8 11. "CTPL,Control Power for DAT[1] lineMMC and SD cards:By default this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards:When this bit is set to 1 the.." "0,1" bitfld.long 0x8 9.--10. "DVAL,Debounce filter valueAll cardsThis register is used to define a debounce period to filter the card detect input signal [SDCD].The usage of the card detect input signal [SDCD] is optional and depends on the system integration and the type of the.." "0,1,2,3" bitfld.long 0x8 8. "WPP,Write protect polarityFor SD and SDIO cards onlyThis bit selects the active level of the write protect input signal [SDWP].The usage of the write protect input signal [SDWP] is optional and depends on the system integration and the type of the.." "0,1" bitfld.long 0x8 7. "CDP,Card detect polarityAll cardsThis bit selects the active level of the card detect input signal [SDCD]. The usage of the card detect input signal [SDCD] is optional and depends on the system integration and the type of the connector housing that.." "0,1" newline bitfld.long 0x8 6. "MIT,MMC interrupt commandOnly for MMC cards.This bit must be set to 1 when the next write access to the command register [MMCSD_CMD] is for Writing a MMC interrupt command [CMD40] requiring the command timeout detection to be disabled for the command.." "0,1" bitfld.long 0x8 5. "DW8,8-bit mode MMC selectFor SD/SDIO cards this bit must be set to 0. For MMC card this bit must be set following a valid SWITCH command [CMD6] with the correct value and extend CSD index written in the argument. Prior to this command the MMC card.." "0,1" bitfld.long 0x8 4. "MODE,Mode selectAll cardsThese bits select between Functional mode and SYSTEST mode. 0 Functional mode. Transfers to the MMC/SD/SDIO cards follow the card protocol. MMC clock is enabled. MMC/SD transfers are operated under the.." "0,1" bitfld.long 0x8 3. "STR,Stream commandOnly for MMC cards.This bit must be set to 1 only for the stream data transfers [read or write] of the adtc commands.Stream read is a class 1 command [CMD11: READ_DAT_UNTIL_STOP].Stream write is a class 3 command [CMD20:.." "0,1" bitfld.long 0x8 2. "HR,Broadcast host responseOnly for MMC cards.This register is used to force the host to generate a 48-bit response for bc command type.It can be used to terminate the interrupt mode by generating a CMD40 response by the core [see section 4.3 'Interrupt.." "0,1" newline bitfld.long 0x8 1. "INIT,Send initialization streamAll cards.When this bit is set to 1 and the card is idle an initialization sequence is sent to the card.An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialization sequence.." "0,1" bitfld.long 0x8 0. "OD,Card open drain mode.Only for MMC cards.This bit must be set to 1 for MMC card commands 1 2 3 and 40 and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically during card identification mode.." "0,1" line.long 0xC "MMC_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power. this value depends on PAD characteristics and voltage." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "PWRCNT,Power counter register.This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. 0 No additional delay added1 TCF delay (card clock period)2 TCF x 2 delay (card clock period)65534 TCF x.." line.long 0x10 "MMC_DLL,DLL control and status register This register is used for tuning procedure required for SDR104 speed mode. It gives visibility and control on the DLL." bitfld.long 0x10 31. "DLL_SOFT_RESET,Soft reset for DLL active HIGH. 0 Reset completed.0 No action.1 Reset is in progress1 Issue soft reset" "0,1" bitfld.long 0x10 30. "LOCK_TIMER,Timer for the dll_lock signal to be asserted after reset. 0 1024 cycles (equivalent to DLL fast mode lock)1 66560 cycles" "0,1" hexmask.long.byte 0x10 22.--29. 1. "MAX_LOCK_DIFF,Maximum number of taps that the master DLLs clock period measurement can deviate without resulting in the master DLL losing lock." bitfld.long 0x10 20.--21. "FORCE_SR_F,Forced fine delay value." "0,1,2,3" hexmask.long.byte 0x10 13.--19. 1. "FORCE_SR_C,Forced coarse delay value" newline bitfld.long 0x10 12. "FORCE_VALUE,Put forced values to target DLL ignoring master DLL output and ratio value. 0 Do not put force value1 Put force value." "0,1" hexmask.long.byte 0x10 6.--11. 1. "SLAVE_RATIO,Fraction of a clock cycle for the shift to be implemented in units of 256ths of a clock cycle. 0 0 degree delay2 45 degrees delay4 90 degrees delay6 135 degrees delay8 180 degrees delay10 225 degrees delay12.." rbitfld.long 0x10 4.--5. "RESERVED" "0,1,2,3" bitfld.long 0x10 3. "DLL_UNLOCK_CLEAR,Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL. 0 No effect.1 Clears the flag." "0,1" rbitfld.long 0x10 2. "DLL_UNLOCK_STICKY,Asserted when any single period measurement exceeds MAX_LOCK_DIFF." "0,1" newline bitfld.long 0x10 1. "DLL_CALIB,Enables Target DLL to update new delay values. 0 Disabled1 Enabled" "0,1" rbitfld.long 0x10 0. "DLL_LOCK,Master DLL lock status. 0 DLL is not locked1 DLL is locked" "0,1" group.long 0x200++0xF line.long 0x0 "MMC_SDMASA,SDMA System Address / Argument 2 Register." hexmask.long 0x0 0.--31. 1. "SDMA_ARG2,SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. [1] SDMA System Address This register contains the system memory address for a SDMA.." line.long 0x4 "MMC_BLK,Transfer Length Configuration Register MMCHS_BLK[BLEN] is the block size register. MMCHS_BLK[NBLK] is the block count register. This register shall be used for any card." hexmask.long.word 0x4 16.--31. 1. "NBLK,Blocks count for current transferThis register is enabled when Block count Enable [MMCSD_CMD[BCE]] is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred.Note: The host.." hexmask.long.byte 0x4 12.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "BLEN,Transfer Block Size.This register specifies the block size for block data transfers.Read operations during transfers may return an invalid value and write operations are ignored.When a CMD12 command is issued to stop the transfer a read of the.." line.long 0x8 "MMC_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register MMCHS_CMD register)." hexmask.long 0x8 0.--31. 1. "ARG,Command argument bits [31:0]" line.long 0xC "MMC_CMD,Command and Transfer Mode Register MMCHS_CMD[31:16] = the command register MMCHS_CMD[15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into.." rbitfld.long 0xC 30.--31. "RESERVED2" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "INDX,Command indexBinary encoded value from 0 to 63 specifying the command number send to card 0 CMD0 or ACMD01 CMD1 or ACMD12 CMD2 or ACMD23 CMD3 or ACMD34 CMD4 or ACMD45 CMD5 or ACMD56 CMD6 or ACMD67 CMD7 or.." bitfld.long 0xC 22.--23. "CMD_TYPE,Command type This register specifies three types of special command: Suspend Resume and Abort. These bits shall be set to00bfor all other commands. 0 Others Commands1 CMD52 for writing 'Bus Suspend' in CCCR2 CMD52 for writing.." "0,1,2,3" bitfld.long 0xC 21. "DP,Data present selectThis register indicates that data is present and DAT line shall be used.It must be set to 0 in the following conditions:- command using only CMD line- command with no data transfer but using busy signal on DAT[0]- Resume command 0.." "0,1" bitfld.long 0xC 20. "CICE,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command.If the index is not the same in the response as in the command it is reported.." "0,1" newline bitfld.long 0xC 19. "CCCE,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus.If an error is detected it is reported as a command CRC error [MMCSD_STAT[CCRC] set to.." "0,1" rbitfld.long 0xC 18. "RESERVED1" "0,1" bitfld.long 0xC 16.--17. "RSP_TYPE,Response typeThis bits defines the response type of the command 0 No response1 Response Length 136 bits2 Response Length 48 bits3 Response Length 48 bits with busy after response" "0,1,2,3" hexmask.long.word 0xC 6.--15. 1. "RESERVED" bitfld.long 0xC 5. "MSBS,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command.For any others command this bit shall be set to 0. 0 Single block. If this bit is 0 it is not necessary to set the register.." "0,1" newline bitfld.long 0xC 4. "DDIR,Data transfer Direction SelectThis bit defines either data transfer will be a read or a write. 0 Data Write (host to card)1 Data Read (card to host)" "0,1" bitfld.long 0xC 2.--3. "ACEN,Auto CMD Enable - SD card only. This field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation [1] Auto CMD12 Enable When this field is set to01b the Host Controller issues CMD12.." "0,1,2,3" bitfld.long 0xC 1. "BCE,Block Count EnableMultiple block transfers only.This bit is used to enable the block count register [MMCSD_BLK[NBLK]].When Block Count is disabled [MMCSD_CMD[BCE] is set to 0] in Multiple block transfers [MMCSD_CMD[MSBS] is set to 1] the module can.." "0,1" bitfld.long 0xC 0. "DE,DMA EnableThis bit is used to enable DMA mode for host data access. 0 DMA mode disable1 DMA mode enable" "0,1" rgroup.long 0x210++0xF line.long 0x0 "MMC_RSP10,Command Response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6." hexmask.long.word 0x0 16.--31. 1. "RSP1,Command Response [31:16]" hexmask.long.word 0x0 0.--15. 1. "RSP0,Command Response [15:0]" line.long 0x4 "MMC_RSP32,Command Response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2." hexmask.long.word 0x4 16.--31. 1. "RSP3,Command Response [63:48]" hexmask.long.word 0x4 0.--15. 1. "RSP2,Command Response [47:32]" line.long 0x8 "MMC_RSP54,Command Response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2." hexmask.long.word 0x8 16.--31. 1. "RSP5,Command Response [95:80]" hexmask.long.word 0x8 0.--15. 1. "RSP4,Command Response [79:64]" line.long 0xC "MMC_RSP76,Command Response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2." hexmask.long.word 0xC 16.--31. 1. "RSP7,Command Response [127:112]" hexmask.long.word 0xC 0.--15. 1. "RSP6,Command Response [111:96]" group.long 0x220++0x3 line.long 0x0 "MMC_DATA,Data RegisterThis register is the 32-bit entry point of the buffer for read or write data transfers.The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512.." hexmask.long 0x0 0.--31. 1. "DATA,Data Register [31:0]In functional mode [MMCSD_CON[MODE] set to the default value 0] A read access to this register is allowed only when the buffer read enable status is set to 1 [MMCSD_PSTATE[BRE]] otherwise a bad access [MMCSD_STAT[BADA]] is.." rgroup.long 0x224++0x3 line.long 0x0 "MMC_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED2" bitfld.long 0x0 24. "CLEV,CMD line signal levelThis status is used to check the CMD line level to recover from errors and for debugging.The value of this register after reset depends on the CMD line level at that time. 0 The CMD line level is 0.1 The CMD line.." "0,1" hexmask.long.byte 0x0 20.--23. 1. "DLEV,DAT[3:0] line signal levelDAT[3] => bit 23DAT[2] => bit 22DAT[1] => bit 21DAT[0] => bit 20This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from.." bitfld.long 0x0 19. "WP,Write protect switch pin levelFor SDIO cards only.This bit reflects the write protect input pin [SDWP] level.The value of this register after reset depends on the protect input pin [SDWP] level at that time. 0 If MMCHS_CON[WPP] is set to 0.." "0,1" bitfld.long 0x0 18. "CDPL,Card detect pin levelThis bit reflects the inverse value of the card detect input pin [SDCD] debouncing is not performed on this bit and bit is valid only when Card State Stable [MMCSD_PSTAE[CSS]] is set to 1.Use of this bit is limited to testing.." "0,1" newline bitfld.long 0x0 17. "CSS,Card State StableThis bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable [MMCSD_PSTATE[CDPL]]. Debouncing is performed on the card detect input pin [SDCD] to detect card stability.This bit is not affected by a software.." "0,1" bitfld.long 0x0 16. "CINS,Card insertedThis bit is the debounced value of the card detect input pin [SDCD].An inactive to active transition of the card detect input pin [SDCD] will generate a card insertion interrupt [MMCSD_STAT[CINS]].A active to inactive transition of the.." "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED1" bitfld.long 0x0 11. "BRE,Buffer read enableThis bit is used for non-DMA read transfers.It indicates that a complete block specified by MMCSD_BLK[BLEN] has been written in the buffer and is ready to be read.It is set to 0 when the entire block is read from the buffer. It is.." "0,1" bitfld.long 0x0 10. "BWE,Buffer Write enableThis status is used for non-DMA write transfers.It indicates if space is available for write data. 0 There is no room left in the buffer to write BLEN bytes of data.1 There is enough space in the buffer to.." "0,1" newline bitfld.long 0x0 9. "RTA,Read transfer activeThis status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request [MMCSD_HCTL[CR]] following a stop at block gap request. This bit is set to 0.." "0,1" bitfld.long 0x0 8. "WTA,Write transfer activeThis status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request [MMCSD_HCTL[CR]] following a stop at block gap request. This bit is set to 0 when CRC status has.." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" bitfld.long 0x0 3. "RTR,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit.." "0,1" bitfld.long 0x0 2. "DLA,DAT line activeThis status bit indicates whether one of the DAT line is in use.In the case of read transactions [card to host]:This bit is set to 1 after the end bit of read command or by activating continue request MMCSD_HCTL[CR].This bit is set to.." "0,1" newline bitfld.long 0x0 1. "DATI,Command inhibit[DAT]This status bit is generated if either DAT line is active [MMCSD_PSTATE[DLA]] or Read transfer is active [MMCSD_PSTATE[RTA]] or when a command with busy is issued. This bit prevents the local host to issue a command.A change of.." "0,1" bitfld.long 0x0 0. "CMDI,Command inhibit[CMD]This status bit indicates that the CMD line is in use.This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted.This bit is set to 0 in either.." "0,1" group.long 0x228++0x1B line.long 0x0 "MMC_HCTL,Host Control Register This register defines the host controls to set power. wakeup and transfer parameters. MMCHS_HCTL[31:24] = Wakeup control MMCHS_HCTL[23:16] = Block gap control MMCHS_HCTL[15:8] = Power control MMCHS_HCTL[7:0] = Host control." hexmask.long.byte 0x0 28.--31. 1. "RESERVED3" bitfld.long 0x0 27. "OBWE,Wakeup event enable for 'Out-of-Band' Interrupt.This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]].The write to this register is ignored when MMCSD_CON[OBIE].." "0,1" bitfld.long 0x0 26. "REM,Wakeup event enable on SD card removalThis bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. 0 Disable wakeup on card removal1 Enable wakeup on card.." "0,1" bitfld.long 0x0 25. "INS,Wakeup event enable on SD card insertionThis bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. 0 Disable wakeup on card insertion1 Enable wakeup on.." "0,1" bitfld.long 0x0 24. "IWE,Wakeup event enable on SD card interruptThis bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. 0 Disable wakeup on card interrupt1 Enable wakeup on.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED2" bitfld.long 0x0 19. "IBG,Interrupt block at gapThis bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0. 0 Disable.." "0,1" bitfld.long 0x0 18. "RWC,Read wait controlThe read wait function is optional only for SDIO cards. If the card supports read wait this bit must be enabled then requesting a stop at block gap [MMCSD_HCTL[SBGR]] generates a read wait period after the current end of block. Be.." "0,1" bitfld.long 0x0 17. "CR,Continue requestThis bit is used to restart a transaction that was stopped by requesting a stop at block gap [MMCSD_HCTL[SBGR]]. Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has.." "0,1" bitfld.long 0x0 16. "SBGR,Stop at block gap requestThis bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request [MMHS_HCTL[CR]] or during a suspend/resume sequence.In case of read transfer the card must support.." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED1" bitfld.long 0x0 9.--11. "SDVS,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system [MMCSD_CAPA[VS18 VS30 VS33]] before starting a transfer. 5 1.8V (Typical)6.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "SDBP,SD bus powerBefore setting this bit the host driver shall select the SD bus voltage [MMCSD_HCTL[SDVS]]. If the host controller detects the No card state this bit is automatically set to 0. If the module is power off a write in the command.." "0,1" bitfld.long 0x0 7. "CDSS,Card Detect Signal SelectionThis bit selects source for the card detection.When the source for the card detection is switched the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in.." "0,1" bitfld.long 0x0 6. "CDTL,Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. 0 No Card1 Card Inserted" "0,1" newline rbitfld.long 0x0 5. "RESERVED" "0,1" bitfld.long 0x0 3.--4. "DMAS,DMA Select Mode:One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only.." "0,1,2,3" bitfld.long 0x0 2. "HSPE,High Speed Enable:Before setting this bit the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 [default] the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock. If.." "0,1" bitfld.long 0x0 1. "DTW,Data transfer widthFor MMC card this bit must be set following a valid SWITCH command [CMD6] with the correct value and extend CSD index written in the argument. Prior to this command the MMC card configuration register [CSD and EXT_CSD] must be.." "0,1" rbitfld.long 0x0 0. "LED,Reserved bit.LED control feature is not supported This bit is initialized to zero and writes to it are ignored." "0,1" line.long 0x4 "MMC_SYSCTL,SD System Control Register This register defines the system controls to set software resets. clock frequency management and data timeout. MMCHS_SYSCTL[31:24] = Software resets MMCHS_SYSCTL[23:16] = Timeout control MMCHS_SYSCTL[15:0] = Clock.." hexmask.long.byte 0x4 27.--31. 1. "RESERVED2" bitfld.long 0x4 26. "SRD,Software reset for DAT lineThis bit is set to 1 for reset and released to 0 when completed.DAT finite state machine in both clock domain are also reset.Here below are the registers cleared by MMCSD_SYSCTL[SRD]:- MMCSD_DATA- MMCSD_PSTATE: BRE BWE .." "0,1" bitfld.long 0x4 25. "SRC,Software reset for CMD lineThis bit is set to 1 for reset and released to 0 when completed.CMD finite state machine in both clock domain are also reset.Here below the registers cleared by MMCSD_SYSCTL[SRC]:- MMCSD_PSTATE: CMDI- MMCSD_STAT: CCOCP and.." "0,1" bitfld.long 0x4 24. "SRA,Software reset for allThis bit is set to 1 for reset and released to 0 when completed.This reset affects the entire host controller except for the card detection circuit and capabilities registers. 0 Reset completed1 Software reset for.." "0,1" hexmask.long.byte 0x4 20.--23. 1. "RESERVED1" newline hexmask.long.byte 0x4 16.--19. 1. "DTO,Data timeout counter value and busy timeout.This value determines the interval by which DAT lines timeouts are detected.The host driver needs to set this bitfield based on - the maximum read access time [NAC] [Refer to the SD Specification Part1.." hexmask.long.word 0x4 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between a reference clock frequency [system dependant] and the output clock frequency on the CLK pin of either the memory card [MMC SD or SDIO]. 0 Clock Ref bypass1 Clock Ref bypass2.." rbitfld.long 0x4 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock.." "0,1" rbitfld.long 0x4 3.--4. "RESERVED" "0,1,2,3" bitfld.long 0x4 2. "CEN,Clock enableThis bit controls if the clock is provided to the card or not. 0 The clock is not provided to the card . Clock frequency can be changed .1 The clock is provided to the card and can be automatically gated when.." "0,1" newline rbitfld.long 0x4 1. "ICS,Internal clock stable [status]This bit indicates either the internal clock is stable or not. 0 The internal clock is not stable.1 The internal clock is stable after enabling the clock (MMCHS_SYSCTL[ICE]) or after changing the.." "0,1" bitfld.long 0x4 0. "ICE,Internal clock enableThis register controls the internal clock activity.In very low power state the internal clock is stopped.Note: The activity of the debounce clock [used for wakeup events] and the OCP clock [used for reads and writes to the.." "0,1" line.long 0x8 "MMC_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt. MMCHS_STAT[31:16] = Error Interrupt Status MMCHS_STAT[15:0] = Normal Interrupt Status." rbitfld.long 0x8 30.--31. "RESERVED3" "0,1,2,3" bitfld.long 0x8 29. "BADA,Bad access to data spaceThis bit is set automatically to indicate a bad access to buffer when not allowed:-This bit is set during a read access to the data register [MMCSD_DATA] while buffer reads are not allowed [MMCSD_PSTATE[BRE] =0]-This bit is.." "0,1" bitfld.long 0x8 28. "CERR,Card errorThis bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b. Only bits referenced as type E[error] in status field in the response can set a card status error. An error bit in the response is.." "0,1" rbitfld.long 0x8 27. "RESERVED2" "0,1" bitfld.long 0x8 26. "TE,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error Host Driver needs to.." "0,1" newline bitfld.long 0x8 25. "ADMAE,ADMA Error:This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition the Host Controller generates this interrupt.." "0,1" bitfld.long 0x8 24. "ACE,Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1. In case of Auto CMD12 this bit is set to 1 not only when the.." "0,1" rbitfld.long 0x8 23. "CLE,Reserved.Current limit error is not supported.These bits are initialized to zero and writes to them are ignored." "0,1" bitfld.long 0x8 22. "DEB,Data End Bit errorThis bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. 0 No Error0 Status bit unchanged1 Data end bit error1.." "0,1" bitfld.long 0x8 21. "DCRC,Data CRC ErrorThis bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command. 0 No Error.0.." "0,1" newline bitfld.long 0x8 20. "DTO,Data timeout errorThis bit is set automatically according to the following conditions: - busy timeout for R1b R5b response type - busy timeout after write CRC status- write CRC status timeout- read data timeout 0 No error.0 Status bit.." "0,1" bitfld.long 0x8 19. "CIE,Command index errorThis bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCSD_CMD[CICE] register. 0 No error.0 Status bit unchanged1 Command index.." "0,1" bitfld.long 0x8 18. "CEB,Command end bit errorThis bit is set automatically when detecting a 0 at the end bit position of a command response. 0 No error.0 Status bit unchanged1 Command end bit error1 Status is cleared" "0,1" bitfld.long 0x8 17. "CCRC,Command CRC ErrorThis bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCSD_CMD[CCCE] register. 0 No Error.0 Status bit unchanged1 Command CRC error1 Status is cleared" "0,1" bitfld.long 0x8 16. "CTO,Command Timeout ErrorThis bit is set automatically when no response is received within 64 clock cycles from the end bit of the command.For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. 0 No error0.." "0,1" newline rbitfld.long 0x8 15. "ERRI,Error InterruptIf any of the bits in the Error Interrupt Status register [MMCSD_STAT[24:15]] are set then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first.Writes to this bit are ignored. 0.." "0,1" hexmask.long.byte 0x8 11.--14. 1. "RESERVED" bitfld.long 0x8 10. "BSR,Boot status received interruptThis bit is set automatically when MMCSD_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. 0 No Interrupt.0 Status bit unchanged1 Boot.." "0,1" bitfld.long 0x8 9. "OBI,Out-Of-Band interruptThis bit is set automatically when MMCSD_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCSD_CON[OBIP].This interrupt is only useful for MMC card.The.." "0,1" rbitfld.long 0x8 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode interrupt source is asynchronous [can be a source of asynchronous wakeup]. In 4-bit mode interrupt source is sampled during the interrupt cycle. In CE-ATA.." "0,1" newline bitfld.long 0x8 7. "CREM,Card removalThis bit is set automatically when MMCSD_PSTATE[CINS] changes from 1 to 0.A clear of this bit doesn't effect Card inserted present state [MMCSD_PSTATE[CINS]]. 0 Card state stable or Debouncing0 Status bit unchanged1 Card.." "0,1" bitfld.long 0x8 6. "CINS,Card insertionThis bit is set automatically when MMCSD_PSTATE[CINS] changes from 0 to 1.A clear of this bit doesn't effect Card inserted present state [MMCSD_PSTATE[CINS]]. 0 Card state stable or debouncing0 Status bit unchanged1 Card.." "0,1" bitfld.long 0x8 5. "BRR,Buffer read readyThis bit is set automatically during a read operation to the card [see class 2 - block oriented read commands] when one block specified by MMCSD_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has.." "0,1" bitfld.long 0x8 4. "BWR,Buffer write readyThis bit is set automatically during a write operation to the card [see class 4 - block oriented write command] when the host can write a complete block as specified by MMCSD_BLK[BLEN]. It indicates that the memory card has emptied.." "0,1" bitfld.long 0x8 3. "DMA,DMA interrupt :This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. 0 Dma interrupt detected0 Status bit unchanged1 No dma interrupt1 Status is cleared" "0,1" newline bitfld.long 0x8 2. "BGE,Block gap eventWhen a stop at block gap is requested [MMCSD_HCTL[SBGR]] this bit is automatically set when transaction is stopped at the block gap during a read or write operation.This event does not occur when the stop at block gap is requested on.." "0,1" bitfld.long 0x8 1. "TC,Transfer completedThis bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request [MMCSD_HCTL[SBGR]].In Read mode:This bit is automatically set on completion of a.." "0,1" bitfld.long 0x8 0. "CC,Command completeThis bit is set when a 1-to-0 transition occurs in the register command inhibit [MMCSD_PSTATE[CMDI]]If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the.." "0,1" line.long 0xC "MMC_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits. on an event-by-event basis. MMCHS_IE[31:16] = Error Interrupt Status Enable MMCHS_IE[15:0] = Normal Interrupt Status Enable." rbitfld.long 0xC 30.--31. "RESERVED3" "0,1,2,3" bitfld.long 0xC 29. "BADA_ENABLE,Bad access to data space Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 28. "CERR_ENABLE,Card Error Status Enable 0 Masked1 Enabled" "0,1" rbitfld.long 0xC 27. "RESERVED2" "0,1" bitfld.long 0xC 26. "TE_ENABLE,Tuning Error Status Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0xC 25. "ADMAE_ENABLE,ADMA Error Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 24. "ACE_ENABLE,Auto CMD Error Status Enable 0 Masked1 Enabled" "0,1" rbitfld.long 0xC 23. "CLE,Reserved bit. Current limit error is not supported. These bits are initialized to zero and writes to them are ignored." "0,1" bitfld.long 0xC 22. "DEB_ENABLE,Data End Bit Error Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 21. "DCRC_ENABLE,Data CRC Error Status Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0xC 20. "DTO_ENABLE,Data Timeout Error Status Enable 0 The data timeout detection is deactivated. The host controller provides the clock to the card until the card sends the data or the transfer is aborted.1 The data timeout detection.." "0,1" bitfld.long 0xC 19. "CIE_ENABLE,Command Index Error Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 18. "CEB_ENABLE,Command End Bit Error Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 17. "CCRC_ENABLE,Command CRC Error Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 16. "CTO_ENABLE,Command Timeout Error Status Enable 0 Masked1 Enabled" "0,1" newline rbitfld.long 0xC 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" hexmask.long.byte 0xC 11.--14. 1. "RESERVED" bitfld.long 0xC 10. "BSR_ENABLE,Boot Status Enable A write to this register when MMCSD_CON[BOOT_ACK] is set to 0x0 is ignored. 0 Masked1 Enabled" "0,1" bitfld.long 0xC 9. "OBI_ENABLE,Out-of-Band Status Enable A write to this register when MMCSD_CON[OBIE] is set to '0' is ignored. 0 Masked1 Enabled" "0,1" bitfld.long 0xC 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card the status bit is reasserted when this bit is set to.." "0,1" newline bitfld.long 0xC 7. "CREM_ENABLE,Card Removal Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 6. "CINS_ENABLE,Card Insertion Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 5. "BRR_ENABLE,Buffer Read Ready Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 4. "BWR_ENABLE,Buffer Write Ready Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 3. "DMA_ENABLE,DMA Status Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0xC 2. "BGE_ENABLE,Block Gap Event Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 1. "TC_ENABLE,Transfer Complete Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0xC 0. "CC_ENABLE,Command Complete Status Enable 0 Masked1 Enabled" "0,1" line.long 0x10 "MMC_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status. on an event-by-event basis. MMCHS_ISE[31:16] = Error Interrupt Signal Enable MMCHS_ISE[15:0] = Normal Interrupt Signal Enable." rbitfld.long 0x10 30.--31. "RESERVED3" "0,1,2,3" bitfld.long 0x10 29. "BADA_SIGEN,Bad access to data space Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 28. "CERR_SIGEN,Card Error Interrupt Signal Enable 0 Masked1 Enabled" "0,1" rbitfld.long 0x10 27. "RESERVED2" "0,1" bitfld.long 0x10 26. "TE_SIGEN,Tuning Error Signal Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0x10 25. "ADMAE_SIGEN,ADMA Error Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 24. "ACE_SIGEN,Auto CMD Error Signal Enable 0 Masked1 Enabled" "0,1" rbitfld.long 0x10 23. "CLE,Reserved bit.Current limit error is not supported.These bits are initialized to zero and writes to them are ignored." "0,1" bitfld.long 0x10 22. "DEB_SIGEN,Data End Bit Error Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 21. "DCRC_SIGEN,Data CRC Error Signal Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0x10 20. "DTO_SIGEN,Data Timeout Error Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 19. "CIE_SIGEN,Command Index Error Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 18. "CEB_SIGEN,Command End Bit Error Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 17. "CCRC_SIGEN,Command CRC Error Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 16. "CTO_SIGEN,Command timeout Error Signal Enable 0 Masked1 Enabled" "0,1" newline rbitfld.long 0x10 15. "NULL,Fixed to 0The host driver shall control error interrupts using the Error Interrupt Signal Enable register.Writes to this bit are ignored" "0,1" hexmask.long.byte 0x10 11.--14. 1. "RESERVED" bitfld.long 0x10 10. "BSR_SIGEN,Boot Status Signal Enable A write to this register when MMCSD_CON[BOOT_ACK] is set to 0x0 is ignored. 0 Masked1 Enabled" "0,1" bitfld.long 0x10 9. "OBI_SIGEN,Out-Of-Band Interrupt Signal Enable A write to this register when MMCSD_CON[OBIE] is set to '0' is ignored. 0 Masked1 Enabled" "0,1" bitfld.long 0x10 8. "CIRQ_SIGEN,Card Interrupt Signal Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0x10 7. "CREM_SIGEN,Card Removal Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 6. "CINS_SIGEN,Card Insertion Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 5. "BRR_SIGEN,Buffer Read Ready Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 4. "BWR_SIGEN,Buffer Write Ready Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 3. "DMA_SIGEN,DMA Interrupt Signal Enable 0 Masked1 Enabled" "0,1" newline bitfld.long 0x10 2. "BGE_SIGEN,Black Gap Event Signal Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 1. "TC_SIGEN,Transfer Completed Status Enable 0 Masked1 Enabled" "0,1" bitfld.long 0x10 0. "CC_SIGEN,Command Complete Status Enable 0 Masked1 Enabled" "0,1" line.long 0x14 "MMC_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur.." bitfld.long 0x14 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver." "0,1" bitfld.long 0x14 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in.." "0,1" hexmask.long.byte 0x14 24.--29. 1. "RESERVED2" bitfld.long 0x14 23. "SCLK_SEL,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning [when Execute Tuning is cleared]. Setting 1 means that tuning is.." "0,1" bitfld.long 0x14 22. "ET,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by Writing 0. This is Read-Write with.." "0,1" newline bitfld.long 0x14 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register." "0,1,2,3" bitfld.long 0x14 19. "V1V8_SIGEN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall.." "0,1" bitfld.long 0x14 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1. If Preset Value Enable in the Host Control 2 register is set to 1 Host Controller sets SDCLK Frequency Select Clock Generator.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--15. 1. "RESERVED1" rbitfld.long 0x14 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error [D04-D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 0 Not error1 Command.." "0,1" newline rbitfld.long 0x14 5.--6. "RESERVED" "0,1,2,3" rbitfld.long 0x14 4. "ACIE,Auto CMD Index Error This bit is set if the Command Index error occurs in response to a command. 0 No error1 Error" "0,1" rbitfld.long 0x14 3. "ACEB,Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0. 0 No error1 End bit Error Generated" "0,1" rbitfld.long 0x14 2. "ACCE,Auto CMD CRC Error This bit is set when detecting a CRC error in the command response. 0 No error1 CRC Error Generated" "0,1" rbitfld.long 0x14 1. "ACTO,Auto CMD Timeout Error This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1 the other error status bits [D04-D02] are meaningless. 0 No error1 Auto CMD Time Out" "0,1" newline rbitfld.long 0x14 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop.." "0,1" line.long 0x18 "MMC_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller." rbitfld.long 0x18 30.--31. "RESERVED4" "0,1,2,3" rbitfld.long 0x18 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt. 0 Asynchronous Interrupt Not Supported1 Asynchronous Interrupt Supported" "0,1" rbitfld.long 0x18 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. 0 32 bit System bus address1 64 bit System bus address" "0,1" rbitfld.long 0x18 27. "RESERVED3" "0,1" bitfld.long 0x18 26. "VS18,Voltage support 1.8V Initialization of this register [via a write access to this register] depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard.." "0,1" newline bitfld.long 0x18 25. "VS30,Voltage support 3.0V Initialization of this register [via a write access to this register] depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard.." "0,1" bitfld.long 0x18 24. "VS33,Voltage support 3.3V Initialization of this register [via a write access to this register] depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard.." "0,1" rbitfld.long 0x18 23. "SRS,Suspend/Resume support [SDIO cards only] This bit indicates whether the host controller supports Suspend/Resume functionality. 0 The Host controller does not Suspend/Resume functionality.1 The Host controller supports Suspend/Resume.." "0,1" rbitfld.long 0x18 22. "DS,DMA supportThis bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. 0 DMA Not Supported1 DMA Supported" "0,1" rbitfld.long 0x18 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency. 0 High Speed Not Supported1 High Speed Supported" "0,1" newline rbitfld.long 0x18 20. "RESERVED2" "0,1" rbitfld.long 0x18 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN 0 ADMA2 not Supported1 ADMA2 Supported" "0,1" rbitfld.long 0x18 18. "RESERVED1" "0,1" rbitfld.long 0x18 16.--17. "MBL,Maximum block lengthThis value indicates the maximum block size that the host driver can read and write to the buffer in the host controller.This value depends on definition of generic parameter with a max value of2048bytes.The host controller.." "0,1,2,3" hexmask.long.byte 0x18 8.--15. 1. "BCF,Base Clock Frequency For SD Clock This value indicates the base [maximum] clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is.." newline rbitfld.long 0x18 7. "TCU,Timeout clock unitThis bit shows the unit of base clock frequency used to detect Data Timeout Error [MMCSD_STAT[DTO]]. 0 KHz1 MHz" "0,1" rbitfld.long 0x18 6. "RESERVED" "0,1" hexmask.long.byte 0x18 0.--5. 1. "TCF,Timeout clock frequencyThe timeout clock frequency is used to detect Data Timeout Error [MMCSD_STAT[DTO]]. 0 The timeout clock frequency depends on the frequency of the clock provided to the card. The value of the timeout clock.." rgroup.long 0x244++0x3 line.long 0x0 "MMC_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization." hexmask.long.byte 0x0 24.--31. 1. "RESERVED3" hexmask.long.byte 0x0 16.--23. 1. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting00hmeans that Host Controller does not support programmable clock generator. 00h: Clock Multiplier is Not Supported.." bitfld.long 0x0 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length. Bit47-46 Re-Tuning Mode Re-Tuning Method Data Length There are two re-tuning timings: Re-Tuning Request controlled by the Host Controller and expiration of a.." "0,1,2,3" bitfld.long 0x0 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104.] 0 SDR50 does not require tuning.1 SDR50 requires tuning." "0,1" bitfld.long 0x0 12. "RESERVED2" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer. 0 Re-Tuning Timer disabled1 1 second2 2 seconds3 4 seconds4 8 seconds5.." bitfld.long 0x0 7. "RESERVED1" "0,1" bitfld.long 0x0 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling. 0 Driver Type D is Not Supported.1 Driver Type D is Supported" "0,1" bitfld.long 0x0 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling. 0 Driver Type C is Not Supported.1 Driver Type C is Supported." "0,1" bitfld.long 0x0 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling. 0 Driver Type A is Not Supported.1 Driver Type A is Supported." "0,1" newline bitfld.long 0x0 3. "RESERVED" "0,1" bitfld.long 0x0 2. "DDR50,DDR50 Support 0 DDR50 is Not Supported.1 DDR50 is Supported." "0,1" bitfld.long 0x0 1. "SDR104,SDR104 Support SDR104 requires tuning. 0 SDR104 is Not Supported.1 SDR104 is Supported." "0,1" bitfld.long 0x0 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1. Bit 13 indicates whether SDR50 requires tuning or not. 0 SDR50 is Not Supported.1 SDR50 is Supported." "0,1" group.long 0x248++0x3 line.long 0x0 "MMC_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (MMCHS_CAPA). Initialization of this.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--23. 1. "CUR_1V8,Maximum current for 1.8V 0 The maximum current capability for this voltage is not available. Feature not implemented." hexmask.long.byte 0x0 8.--15. 1. "CUR_3V0,Maximum current for 3.0V 0 The maximum current capability for this voltage is not available. Feature not implemented." hexmask.long.byte 0x0 0.--7. 1. "CUR_3V3,Maximum current for 3.3V 0 The maximum current capability for this voltage is not available. Feature not implemented." group.long 0x250++0xB line.long 0x0 "MMC_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register. Rather. it is an address at which the Auto CMD Error Status Register can be written. Writing 1 : set each.." bitfld.long 0x0 30.--31. "RESERVED3" "0,1,2,3" bitfld.long 0x0 29. "FE_BADA,Force Event Bad access to data space. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 28. "FE_CERR,Force Event Card error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 26.--27. "RESERVED2" "0,1,2,3" bitfld.long 0x0 25. "FE_ADMAE,Force Event ADMA Error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" newline bitfld.long 0x0 24. "FE_ACE,Force Event for Auto CMD Error 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 23. "FE_CLE,Reserved. Current limit error is not supported. These bits are initialized to zero and writes to them are ignored." "0,1" bitfld.long 0x0 22. "FE_DEB,Force Event Data End Bit error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 21. "FE_DCRC,Force Event Data CRC Error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 20. "FE_DTO,Force Event Data Timeout Error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" newline bitfld.long 0x0 19. "FE_CIE,Force Event Command Index Error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 18. "FE_CEB,Force Event Command End Bit Error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 17. "FE_CCRC,Force Event Command CRC Error. 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 16. "FE_CTO,Command Timeout ErrorThis bit is set automatically when no response is received within 64 clock cycles from the end bit of the command.For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. 0 Status.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RESERVED1" newline bitfld.long 0x0 7. "FE_CNI,Force Event Command not issue by Auto CMD12 error 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 5.--6. "RESERVED" "0,1,2,3" bitfld.long 0x0 4. "FE_ACIE,Force Event for Auto CMD Index Error 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 3. "FE_ACEB,Force Event Auto CMD End Bit Error 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 2. "FE_ACCE,Force Event Auto CMD CRC Error 0 No effect No Interrupt.1 Interrupt Forced" "0,1" newline bitfld.long 0x0 1. "FE_ACTO,Force Event Auto CMD Timeout Error 0 No effect No Interrupt.1 Interrupt Forced" "0,1" bitfld.long 0x0 0. "FE_ACNE,Force Event Auto CMD12 Not Executed 0 No effect No Interrupt.1 Interrupt Forced" "0,1" line.long 0x4 "MMC_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred. the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error..." hexmask.long 0x4 3.--31. 1. "RESERVED" bitfld.long 0x4 2. "LME,ADMA Length Mismatch Error:[1] While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length.[2] Total data length can not be divided by the block.." "0,1" bitfld.long 0x4 0.--1. "AES,ADMA Error State his field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '10' because ADMA never stops in this state. 0 ST_STOP (Stop DMA)Contents of SYS_SDR register1 ST_STOP.." "0,1,2,3" line.long 0x8 "MMC_ADMASAL,ADMA System address Low bits." hexmask.long 0x8 0.--31. 1. "ADMA_A32B,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA the Host Driver shall set start address of the.." rgroup.long 0x260++0xF line.long 0x0 "MMC_PVINITSD,Preset Value for Initialization and Default Speed modes." bitfld.long 0x0 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type.." "0,1,2,3" bitfld.long 0x0 27.--29. "RESERVED1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator.1 Programmable Clock Generator." "0,1" hexmask.long.word 0x0 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." bitfld.long 0x0 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected1 Driver Type A is Selected2 Driver.." "0,1,2,3" newline bitfld.long 0x0 11.--13. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator.1 Programmable Clock Generator." "0,1" hexmask.long.word 0x0 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.long 0x4 "MMC_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes." bitfld.long 0x4 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type C is.." "0,1,2,3" bitfld.long 0x4 27.--29. "RESERVED1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generato.1 Programmable Clock Generator." "0,1" hexmask.long.word 0x4 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." bitfld.long 0x4 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type C.." "0,1,2,3" newline bitfld.long 0x4 11.--13. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator.1 Programmable Clock Generator." "0,1" hexmask.long.word 0x4 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.long 0x8 "MMC_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes." bitfld.long 0x8 30.--31. "SDR50DS_SEL,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type C is.." "0,1,2,3" bitfld.long 0x8 27.--29. "RESERVED1" "0,1,2,3,4,5,6,7" bitfld.long 0x8 26. "SDR50CLKGEN_SEL,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator.1 Programmable Clock Generator." "0,1" hexmask.long.word 0x8 16.--25. 1. "SDR50SDCLK_SEL,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." bitfld.long 0x8 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type C is.." "0,1,2,3" newline bitfld.long 0x8 11.--13. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x8 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator.1 Programmable Clock Generato." "0,1" hexmask.long.word 0x8 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.long 0xC "MMC_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes." bitfld.long 0xC 30.--31. "DDR50DS_SEL,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type C is.." "0,1,2,3" bitfld.long 0xC 27.--29. "RESERVED1" "0,1,2,3,4,5,6,7" bitfld.long 0xC 26. "DDR50CLKGEN_SEL,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator1 Programmable Clock Generator" "0,1" hexmask.long.word 0xC 16.--25. 1. "DDR50SDCLK_SEL,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." bitfld.long 0xC 14.--15. "SDR104DS_SEL,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 0 Driver Type B is Selected.1 Driver Type A is Selected.2 Driver Type C.." "0,1,2,3" newline bitfld.long 0xC 11.--13. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0xC 10. "SDR104CLKGEN_SEL,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator. 0 Host Controller Ver2.00 Compatible Clock Generator.1 Programmable Clock Generator." "0,1" hexmask.long.word 0xC 0.--9. 1. "SDR104SDCLK_SEL,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.long 0x2FC++0x3 line.long 0x0 "MMC_REV,Versions RegisterThis register contains the hard coded RTL vendor revision number. the version number of SD specification compliancy and a slot status bit.MMCHS_REV[31:16] = Host controller versionMMCHS_REV[15:0] = Slot Interrupt Status." hexmask.long.byte 0x0 24.--31. 1. "VREV,Vendor Version Number: IP revision[7:4] Major revision[3:0] Minor revisionExamples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x0 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 0 SD Host Specification Version 1.00.1 SD Host Specification Version 2.00 - Including the feature.." hexmask.long.word 0x0 1.--15. 1. "RESERVED" bitfld.long 0x0 0. "SIS,Slot Interrupt StatusThis status bit indicates the inverted state of interrupt signal for the module.By a power on reset or by setting a software reset for all [MMCSD_HCTL[SRA]] the interrupt signal shall be de-asserted and this status shall read 0." "0,1" tree.end tree "MPU" base ad:0x0 tree "MPU_DTHE" base ad:0x40120000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_FSS" tree "MPU_FSS_CONFIG" base ad:0x40260000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_4_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_4_INTERRUPT_RAW_STATUS_SET,Interrupt Raw Status/Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_4_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_4_INTERRUPT_ENABLE,Interrupt Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_4_INTERRUPT_ENABLE_CLEAR,Interrupt Enable Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_4_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_4_FAULT_STATUS,Fault Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Initiator ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_4_FAULT_CLEAR,Fault Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_FSS_DATA" base ad:0x40160000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_HSM" base ad:0x40240000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_L2OCRAM" tree "MPU_L2OCRAM_BANK0" base ad:0x40020000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK1" base ad:0x40040000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK2" base ad:0x40060000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK3" base ad:0x40080000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK4" base ad:0x402C0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK5" base ad:0x402E0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_MBOX_SRAM" base ad:0x40140000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_R5SS0" tree "MPU_R5SS0_CONFIG" base ad:0x40280000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_4_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_4_INTERRUPT_RAW_STATUS_SET,Interrupt Raw Status/Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_4_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_4_INTERRUPT_ENABLE,Interrupt Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_4_INTERRUPT_ENABLE_CLEAR,Interrupt Enable Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_4_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_4_FAULT_STATUS,Fault Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Initiator ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_4_FAULT_CLEAR,Fault Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_R5SS0_CORE0" tree "MPU_R5SS0_CORE0_AHB" base ad:0x401C0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_16_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_16_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_16_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_16_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_16_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x280++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_9_START_ADDRESS,Programmable_9_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_9_END_ADDRESS,Programmable_9_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_9_MPPA,Programmable_9_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x290++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_10_START_ADDRESS,Programmable_10_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_10_END_ADDRESS,Programmable_10_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_10_MPPA,Programmable_10_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2A0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_11_START_ADDRESS,Programmable_11_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_11_END_ADDRESS,Programmable_11_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_11_MPPA,Programmable_11_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2B0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_12_START_ADDRESS,Programmable_12_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_12_END_ADDRESS,Programmable_12_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_12_MPPA,Programmable_12_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2C0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_13_START_ADDRESS,Programmable_13_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_13_END_ADDRESS,Programmable_13_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_13_MPPA,Programmable_13_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2D0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_14_START_ADDRESS,Programmable_14_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_14_END_ADDRESS,Programmable_14_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_14_MPPA,Programmable_14_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2E0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_15_START_ADDRESS,Programmable_15_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_15_END_ADDRESS,Programmable_15_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_15_MPPA,Programmable_15_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2F0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_16_START_ADDRESS,Programmable_16_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_16_END_ADDRESS,Programmable_16_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_16_MPPA,Programmable_16_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_16_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_16_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_16_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS0_CORE0_AXIS" base ad:0x400A0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_R5SS0_CORE1" tree "MPU_R5SS0_CORE1_AHB" base ad:0x401E0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_16_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_16_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_16_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_16_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_16_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x280++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_9_START_ADDRESS,Programmable_9_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_9_END_ADDRESS,Programmable_9_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_9_MPPA,Programmable_9_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x290++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_10_START_ADDRESS,Programmable_10_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_10_END_ADDRESS,Programmable_10_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_10_MPPA,Programmable_10_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2A0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_11_START_ADDRESS,Programmable_11_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_11_END_ADDRESS,Programmable_11_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_11_MPPA,Programmable_11_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2B0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_12_START_ADDRESS,Programmable_12_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_12_END_ADDRESS,Programmable_12_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_12_MPPA,Programmable_12_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2C0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_13_START_ADDRESS,Programmable_13_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_13_END_ADDRESS,Programmable_13_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_13_MPPA,Programmable_13_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2D0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_14_START_ADDRESS,Programmable_14_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_14_END_ADDRESS,Programmable_14_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_14_MPPA,Programmable_14_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2E0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_15_START_ADDRESS,Programmable_15_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_15_END_ADDRESS,Programmable_15_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_15_MPPA,Programmable_15_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2F0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_16_START_ADDRESS,Programmable_16_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_16_END_ADDRESS,Programmable_16_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_16_MPPA,Programmable_16_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_16_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_16_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_16_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS0_CORE1_AXIS" base ad:0x400C0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree.end tree "MPU_R5SS1" tree "MPU_R5SS1_CONFIG" base ad:0x402A0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_4_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_4_INTERRUPT_RAW_STATUS_SET,Interrupt Raw Status/Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_4_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_4_INTERRUPT_ENABLE,Interrupt Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_4_INTERRUPT_ENABLE_CLEAR,Interrupt Enable Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_4_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_4_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_4_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_4_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_4_FAULT_STATUS,Fault Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Initiator ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_4_FAULT_CLEAR,Fault Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_R5SS1_CORE0" tree "MPU_R5SS1_CORE0_AHB" base ad:0x40200000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_16_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_16_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_16_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_16_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_16_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x280++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_9_START_ADDRESS,Programmable_9_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_9_END_ADDRESS,Programmable_9_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_9_MPPA,Programmable_9_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x290++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_10_START_ADDRESS,Programmable_10_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_10_END_ADDRESS,Programmable_10_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_10_MPPA,Programmable_10_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2A0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_11_START_ADDRESS,Programmable_11_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_11_END_ADDRESS,Programmable_11_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_11_MPPA,Programmable_11_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2B0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_12_START_ADDRESS,Programmable_12_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_12_END_ADDRESS,Programmable_12_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_12_MPPA,Programmable_12_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2C0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_13_START_ADDRESS,Programmable_13_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_13_END_ADDRESS,Programmable_13_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_13_MPPA,Programmable_13_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2D0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_14_START_ADDRESS,Programmable_14_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_14_END_ADDRESS,Programmable_14_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_14_MPPA,Programmable_14_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2E0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_15_START_ADDRESS,Programmable_15_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_15_END_ADDRESS,Programmable_15_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_15_MPPA,Programmable_15_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2F0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_16_START_ADDRESS,Programmable_16_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_16_END_ADDRESS,Programmable_16_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_16_MPPA,Programmable_16_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_16_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_16_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_16_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS1_CORE0_AXIS" base ad:0x400E0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_R5SS1_CORE1" tree "MPU_R5SS1_CORE1_AHB" base ad:0x40220000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_16_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_16_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_16_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_16_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_16_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x280++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_9_START_ADDRESS,Programmable_9_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_9_END_ADDRESS,Programmable_9_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_9_MPPA,Programmable_9_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x290++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_10_START_ADDRESS,Programmable_10_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_10_END_ADDRESS,Programmable_10_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_10_MPPA,Programmable_10_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2A0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_11_START_ADDRESS,Programmable_11_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_11_END_ADDRESS,Programmable_11_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_11_MPPA,Programmable_11_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2B0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_12_START_ADDRESS,Programmable_12_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_12_END_ADDRESS,Programmable_12_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_12_MPPA,Programmable_12_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2C0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_13_START_ADDRESS,Programmable_13_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_13_END_ADDRESS,Programmable_13_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_13_MPPA,Programmable_13_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2D0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_14_START_ADDRESS,Programmable_14_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_14_END_ADDRESS,Programmable_14_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_14_MPPA,Programmable_14_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2E0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_15_START_ADDRESS,Programmable_15_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_15_END_ADDRESS,Programmable_15_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_15_MPPA,Programmable_15_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2F0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_16_START_ADDRESS,Programmable_16_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_16_END_ADDRESS,Programmable_16_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_16_MPPA,Programmable_16_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_16_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_16_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_16_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS1_CORE1_AXIS" base ad:0x40100000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_8_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_8_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_8_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_8_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_8_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will reset clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_8_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_8_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_8_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_8_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_8_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_8_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree.end tree "MPU_SCRM2SCRP0" base ad:0x40180000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_16_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_16_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_16_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_16_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_16_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x280++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_9_START_ADDRESS,Programmable_9_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_9_END_ADDRESS,Programmable_9_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_9_MPPA,Programmable_9_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x290++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_10_START_ADDRESS,Programmable_10_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_10_END_ADDRESS,Programmable_10_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_10_MPPA,Programmable_10_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2A0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_11_START_ADDRESS,Programmable_11_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_11_END_ADDRESS,Programmable_11_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_11_MPPA,Programmable_11_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2B0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_12_START_ADDRESS,Programmable_12_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_12_END_ADDRESS,Programmable_12_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_12_MPPA,Programmable_12_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2C0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_13_START_ADDRESS,Programmable_13_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_13_END_ADDRESS,Programmable_13_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_13_MPPA,Programmable_13_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2D0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_14_START_ADDRESS,Programmable_14_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_14_END_ADDRESS,Programmable_14_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_14_MPPA,Programmable_14_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2E0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_15_START_ADDRESS,Programmable_15_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_15_END_ADDRESS,Programmable_15_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_15_MPPA,Programmable_15_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2F0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_16_START_ADDRESS,Programmable_16_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_16_END_ADDRESS,Programmable_16_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_16_MPPA,Programmable_16_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_16_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_16_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_16_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_SCRM2SCRP1" base ad:0x401A0000 rgroup.long 0x0++0x3 line.long 0x0 "MPU_16_REVISION,Revision." bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." newline bitfld.long 0x0 8.--10. "REVMAJ,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." group.long 0x10++0xF line.long 0x0 "MPU_16_INTERRUPT_RAW_STATUS_SET,Interrupt_Raw_Status_Set." hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_16_INTERRUPT_ENABLED_STATUS_CLEAR,Interrupt_Enabled_Status_Clear." hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_16_INTERRUPT_ENABLE,Interrupt_Enable." hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_16_INTERRUPT_ENABLE_CLEAR,Interrupt_Enable_Clear." hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.long 0x200++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_1_START_ADDRESS,Programmable_1_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_1_END_ADDRESS,Programmable_1_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_1_MPPA,Programmable_1_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_2_START_ADDRESS,Programmable_2_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_2_END_ADDRESS,Programmable_2_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_2_MPPA,Programmable_2_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_3_START_ADDRESS,Programmable_3_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_3_END_ADDRESS,Programmable_3_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_3_MPPA,Programmable_3_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_4_START_ADDRESS,Programmable_4_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_4_END_ADDRESS,Programmable_4_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_4_MPPA,Programmable_4_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_5_START_ADDRESS,Programmable_5_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_5_END_ADDRESS,Programmable_5_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_5_MPPA,Programmable_5_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_6_START_ADDRESS,Programmable_6_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_6_END_ADDRESS,Programmable_6_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_6_MPPA,Programmable_6_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_7_START_ADDRESS,Programmable_7_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_7_END_ADDRESS,Programmable_7_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_7_MPPA,Programmable_7_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_8_START_ADDRESS,Programmable_8_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_8_END_ADDRESS,Programmable_8_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_8_MPPA,Programmable_8_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x280++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_9_START_ADDRESS,Programmable_9_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_9_END_ADDRESS,Programmable_9_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_9_MPPA,Programmable_9_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x290++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_10_START_ADDRESS,Programmable_10_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_10_END_ADDRESS,Programmable_10_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_10_MPPA,Programmable_10_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2A0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_11_START_ADDRESS,Programmable_11_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_11_END_ADDRESS,Programmable_11_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_11_MPPA,Programmable_11_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2B0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_12_START_ADDRESS,Programmable_12_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_12_END_ADDRESS,Programmable_12_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_12_MPPA,Programmable_12_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2C0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_13_START_ADDRESS,Programmable_13_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_13_END_ADDRESS,Programmable_13_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_13_MPPA,Programmable_13_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2D0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_14_START_ADDRESS,Programmable_14_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_14_END_ADDRESS,Programmable_14_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_14_MPPA,Programmable_14_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2E0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_15_START_ADDRESS,Programmable_15_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_15_END_ADDRESS,Programmable_15_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_15_MPPA,Programmable_15_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x2F0++0xB line.long 0x0 "MPU_16_PROGRAMMABLE_16_START_ADDRESS,Programmable_16_Start_Address." hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_16_PROGRAMMABLE_16_END_ADDRESS,Programmable_16_End_Address." hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_16_PROGRAMMABLE_16_MPPA,Programmable_16_MPPA." rbitfld.long 0x8 29.--31. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "LOCK,this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit.Writing 1 is alllowed once per boot. Lock bit will clear on reset only.Once locked SW can not modify the MPU.." "0,1" rbitfld.long 0x8 26.--27. "RESERVED2,Always read as 0." "0,1,2,3" hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." newline bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" newline bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_16_FAULT_ADDRESS,Fault_Address." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault_address." line.long 0x4 "MPU_16_FAULT_STATUS,Fault_Status." hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." newline bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault_type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_16_FAULT_CLEAR,Fault_Clear." hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault_clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MSRAM" base ad:0x0 tree "MSRAM_BANK0" base ad:0x70000000 group.long 0x0++0x3 line.long 0x0 "MSRAM_START,L2 Memory start address." hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x7FFFC++0x3 line.long 0x0 "MSRAM_END,L2 Memory end address." hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MSRAM_BANK1" base ad:0x70080000 group.long 0x0++0x3 line.long 0x0 "MSRAM_START,L2 Memory start address." hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x7FFFC++0x3 line.long 0x0 "MSRAM_END,L2 Memory end address." hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MSRAM_BANK2" base ad:0x70100000 group.long 0x0++0x3 line.long 0x0 "MSRAM_START,L2 Memory start address." hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x7FFFC++0x3 line.long 0x0 "MSRAM_END,L2 Memory end address." hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MSRAM_BANK3" base ad:0x70180000 group.long 0x0++0x3 line.long 0x0 "MSRAM_START,L2 Memory start address." hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x7FFFC++0x3 line.long 0x0 "MSRAM_END,L2 Memory end address." hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MSRAM_BANK4" base ad:0x70200000 group.long 0x0++0x3 line.long 0x0 "MSRAM_START,L2 Memory start address." hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x7FFFC++0x3 line.long 0x0 "MSRAM_END,L2 Memory end address." hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MSRAM_BANK5" base ad:0x70280000 group.long 0x0++0x3 line.long 0x0 "MSRAM_START,L2 Memory start address." hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x7FFFC++0x3 line.long 0x0 "MSRAM_END,L2 Memory end address." hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree.end tree "MSS" base ad:0x0 tree "MSS_CTRL" base ad:0x50D00000 group.long 0x20++0xB line.long 0x0 "MSS_CTRL_R5SS0_CONTROL" bitfld.long 0x0 24.--26. "R5SS0_CONTROL_ROM_WAIT_STATE,Writing 3'b111 enables a single cycle wait state with respect to CR5A_clk for rom access.This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. [because it is a timing issue in this scenario]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "R5SS0_CONTROL_RESET_FSM_TRIGGER,Write pulse bit field:Writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "R5SS0_CONTROL_LOCK_STEP_SWITCH_WAIT,Writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS0_CONTROL_LOCK_STEP,Writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if corresponding R5SS_CONTROL_LOCK_STEP_SWITCH_WAIT is set. Or else the switiching to Dual-core happens on the fly." "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_HALT" bitfld.long 0x4 0.--2. "R5SS0_CORE0_HALT_HALT,Writing 3'b000 will unhalt CR5A. This register should be written only once." "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_HALT" bitfld.long 0x8 0.--2. "R5SS0_CORE1_HALT_HALT,Writing 3'b000 will unhalt for CR5B. This register should be written only once." "0,1,2,3,4,5,6,7" rgroup.long 0x2C++0xB line.long 0x0 "MSS_CTRL_R5SS0_STATUS_REG" bitfld.long 0x0 8. "R5SS0_STATUS_REG_LOCK_STEP,Reading1:confirms R5SS is in lockstep mode. Reading0:confirms R5SS is in Dual-core mode." "0,1" newline bitfld.long 0x0 0. "R5SS0_STATUS_REG_MEMSWAP,Reading1:confirms ROM is Eclipsed from with RAM for R5." "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_STAT" bitfld.long 0x4 4. "R5SS0_CORE0_STAT_WFE_STAT,WFE Status" "0,1" newline bitfld.long 0x4 0. "R5SS0_CORE0_STAT_WFI_STAT,WFI Status" "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_STAT" bitfld.long 0x8 4. "R5SS0_CORE1_STAT_WFE_STAT,WFE Status" "0,1" newline bitfld.long 0x8 0. "R5SS0_CORE1_STAT_WFI_STAT,WFI Status" "0,1" group.long 0x38++0x3 line.long 0x0 "MSS_CTRL_R5SS0_FORCE_WFI" bitfld.long 0x0 0.--2. "R5SS0_FORCE_WFI_CR5_WFI_OVERIDE,Writing 3'b111 will force the wfi signals of R5SS to 1" "0,1,2,3,4,5,6,7" group.long 0x40++0xB line.long 0x0 "MSS_CTRL_R5SS1_CONTROL" bitfld.long 0x0 16.--18. "R5SS1_CONTROL_RESET_FSM_TRIGGER,Write pulse bit field:Writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "R5SS1_CONTROL_LOCK_STEP_SWITCH_WAIT,Writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS1_CONTROL_LOCK_STEP,Writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if corresponding R5SS_CONTROL_LOCK_STEP_SWITCH_WAIT is set. Or else the switiching to Dual-core happens on the fly." "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_HALT" bitfld.long 0x4 0.--2. "R5SS1_CORE0_HALT_HALT,Writing 3'b000 will unhalt CR5A. This register should be written only once." "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_HALT" bitfld.long 0x8 0.--2. "R5SS1_CORE1_HALT_HALT,Writing 3'b000 will unhalt for CR5B. This register should be written only once." "0,1,2,3,4,5,6,7" rgroup.long 0x4C++0xB line.long 0x0 "MSS_CTRL_R5SS1_STATUS_REG" bitfld.long 0x0 8. "R5SS1_STATUS_REG_LOCK_STEP,Reading1:confirms R5SS is in lockstep mode. Reading0:confirms R5SS is in Dual-core mode." "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_STAT" bitfld.long 0x4 4. "R5SS1_CORE0_STAT_WFE_STAT,WFE Status" "0,1" newline bitfld.long 0x4 0. "R5SS1_CORE0_STAT_WFI_STAT,WFI Status" "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_STAT" bitfld.long 0x8 4. "R5SS1_CORE1_STAT_WFE_STAT,WFE Status" "0,1" newline bitfld.long 0x8 0. "R5SS1_CORE1_STAT_WFI_STAT,WFI Status" "0,1" group.long 0x58++0x3 line.long 0x0 "MSS_CTRL_R5SS1_FORCE_WFI" bitfld.long 0x0 0.--2. "R5SS1_FORCE_WFI_CR5_WFI_OVERIDE,Writing 3'b111 will force the wfi signals of R5SS to 1" "0,1,2,3,4,5,6,7" group.long 0x80++0x3 line.long 0x0 "MSS_CTRL_R5SS0_ROM_ECLIPSE" bitfld.long 0x0 8.--10. "R5SS0_ROM_ECLIPSE_MEMSWAP_WAIT,Writing 3'b111 ensures ROM-Eclipsing happens only after R5SS reset. Or else it will be a immediate change." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS0_ROM_ECLIPSE_MEMSWAP,Writing 3'b111 ensures eclipsing of CR5A_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after R5SS reset assertion." "0,1,2,3,4,5,6,7" group.long 0x200++0x7 line.long 0x0 "MSS_CTRL_R5SS0_ATCM_MEM_INIT" bitfld.long 0x0 0. "R5SS0_ATCM_MEM_INIT_MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the ATCM banks of CR5A/B. Value in each row is initialized to 0x0C_0000_0000" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_ATCM_MEM_INIT_DONE" bitfld.long 0x4 0. "R5SS0_ATCM_MEM_INIT_DONE_MEM_INIT_DONE,This field will be high once initialization of ATCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x208++0x3 line.long 0x0 "MSS_CTRL_R5SS0_ATCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "R5SS0_ATCM_MEM_INIT_STATUS_MEM_STATUS,1'b0: No initialization is happening for ATCM banks of CR5A/B1'b1: Initialization is in progress for ATCM banks of CR5A/B" "0: No initialization is happening for ATCM banks of..,?" group.long 0x210++0x7 line.long 0x0 "MSS_CTRL_R5SS0_BTCM_MEM_INIT" bitfld.long 0x0 0. "R5SS0_BTCM_MEM_INIT_MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_BTCM_MEM_INIT_DONE" bitfld.long 0x4 0. "R5SS0_BTCM_MEM_INIT_DONE_MEM_INIT_DONE,This field will be high once initialization of B0/1TCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x218++0x3 line.long 0x0 "MSS_CTRL_R5SS0_BTCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "R5SS0_BTCM_MEM_INIT_STATUS_MEM_STATUS,1'b0: No initialization is happening for B0/1TCM banks of CR5A/B1'b1: Initialization is in progress for B0/1TCM banks of CR5A/B" "0: No initialization is happening for B0/1TCM banks..,?" group.long 0x220++0x7 line.long 0x0 "MSS_CTRL_R5SS1_ATCM_MEM_INIT" bitfld.long 0x0 0. "R5SS1_ATCM_MEM_INIT_MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the ATCM banks of CR5A/B. Value in each row is initialized to 0x0C_0000_0000" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_ATCM_MEM_INIT_DONE" bitfld.long 0x4 0. "R5SS1_ATCM_MEM_INIT_DONE_MEM_INIT_DONE,This field will be high once initialization of ATCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x228++0x3 line.long 0x0 "MSS_CTRL_R5SS1_ATCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "R5SS1_ATCM_MEM_INIT_STATUS_MEM_STATUS,1'b0: No initialization is happening for ATCM banks of CR5A/B1'b1: Initialization is in progress for ATCM banks of CR5A/B" "0: No initialization is happening for ATCM banks of..,?" group.long 0x230++0x7 line.long 0x0 "MSS_CTRL_R5SS1_BTCM_MEM_INIT" bitfld.long 0x0 0. "R5SS1_BTCM_MEM_INIT_MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_BTCM_MEM_INIT_DONE" bitfld.long 0x4 0. "R5SS1_BTCM_MEM_INIT_DONE_MEM_INIT_DONE,This field will be high once initialization of B0/1TCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x238++0x3 line.long 0x0 "MSS_CTRL_R5SS1_BTCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "R5SS1_BTCM_MEM_INIT_STATUS_MEM_STATUS,1'b0: No initialization is happening for B0/1TCM banks of CR5A/B1'b1: Initialization is in progress for B0/1TCM banks of CR5A/B" "0: No initialization is happening for B0/1TCM banks..,?" group.long 0x240++0x7 line.long 0x0 "MSS_CTRL_L2IOCRAM_MEM_INIT" bitfld.long 0x0 5. "L2IOCRAM_MEM_INIT_PARTITION5,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank5. Value in each row is initialized to 0x0" "0,1" newline bitfld.long 0x0 4. "L2IOCRAM_MEM_INIT_PARTITION4,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank4. Value in each row is initialized to 0x0" "0,1" newline bitfld.long 0x0 3. "L2IOCRAM_MEM_INIT_PARTITION3,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank3. Value in each row is initialized to 0x0" "0,1" newline bitfld.long 0x0 2. "L2IOCRAM_MEM_INIT_PARTITION2,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank2. Value in each row is initialized to 0x0" "0,1" newline bitfld.long 0x0 1. "L2IOCRAM_MEM_INIT_PARTITION1,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank1. Value in each row is initialized to 0x0" "0,1" newline bitfld.long 0x0 0. "L2IOCRAM_MEM_INIT_PARTITION0,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank0. Value in each row is initialized to 0x0" "0,1" line.long 0x4 "MSS_CTRL_L2IOCRAM_MEM_INIT_DONE" bitfld.long 0x4 5. "L2IOCRAM_MEM_INIT_DONE_PARTITION5,This field will be high once intialization of L2 bank5 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.long 0x4 4. "L2IOCRAM_MEM_INIT_DONE_PARTITION4,This field will be high once intialization of L2 bank4 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.long 0x4 3. "L2IOCRAM_MEM_INIT_DONE_PARTITION3,This field will be high once intialization of L2 bank3 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.long 0x4 2. "L2IOCRAM_MEM_INIT_DONE_PARTITION2,This field will be high once intialization of L2 bank2 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.long 0x4 1. "L2IOCRAM_MEM_INIT_DONE_PARTITION1,This field will be high once intialization of L2 bank1 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.long 0x4 0. "L2IOCRAM_MEM_INIT_DONE_PARTITION0,This field will be high once intialization of L2 bank0 is finished. Writing '1' would clear the bit" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "MSS_CTRL_L2IOCRAM_MEM_INIT_STATUS" bitfld.long 0x0 5. "L2IOCRAM_MEM_INIT_STATUS_PARTITION5,1'b0: No initialization is happening for L2 bank51'b1: Initialization is in progress for L2 bank5" "0: No initialization is happening for L2 bank51'b1:..,?" newline bitfld.long 0x0 4. "L2IOCRAM_MEM_INIT_STATUS_PARTITION4,1'b0: No initialization is happening for L2 bank41'b1: Initialization is in progress for L2 bank4" "0: No initialization is happening for L2 bank41'b1:..,?" newline bitfld.long 0x0 3. "L2IOCRAM_MEM_INIT_STATUS_PARTITION3,1'b0: No initialization is happening for L2 bank31'b1: Initialization is in progress for L2 bank3" "0: No initialization is happening for L2 bank31'b1:..,?" newline bitfld.long 0x0 2. "L2IOCRAM_MEM_INIT_STATUS_PARTITION2,1'b0: No initialization is happening for L2 bank2 1'b1: Initialization is in progress for L2 bank2" "0: No initialization is happening for L2 bank2,1: Initialization is in progress for L2 bank2" newline bitfld.long 0x0 1. "L2IOCRAM_MEM_INIT_STATUS_PARTITION1,1'b0: No initialization is happening for L2 bank11'b1: Initialization is in progress for L2 bank1" "0: No initialization is happening for L2 bank11'b1:..,?" newline bitfld.long 0x0 0. "L2IOCRAM_MEM_INIT_STATUS_PARTITION0,1'b0: No initialization is happening for L2 bank0 1'b1: Initialization is in progress for L2 bank0" "0: No initialization is happening for L2 bank0,1: Initialization is in progress for L2 bank0" group.long 0x250++0x7 line.long 0x0 "MSS_CTRL_MAILBOXRAM_MEM_INIT" bitfld.long 0x0 0. "MAILBOXRAM_MEM_INIT_MEM0_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the MSS_MBOX. Value in each row is initialized to 0x0" "0,1" line.long 0x4 "MSS_CTRL_MAILBOXRAM_MEM_INIT_DONE" bitfld.long 0x4 0. "MAILBOXRAM_MEM_INIT_DONE_MEM0_DONE,This field will be high once intialization of MSS_MBOX is finished. Writing '1' would clear the bit" "0,1" rgroup.long 0x258++0x3 line.long 0x0 "MSS_CTRL_MAILBOXRAM_MEM_INIT_STATUS" bitfld.long 0x0 0. "MAILBOXRAM_MEM_INIT_STATUS_MEM0_STATUS,1'b0: No initialization is happening for MSS_MBOX 1'b1: Initialization is in progress for MSS_MBOX" "0: No initialization is happening for MSS_MBOX,1: Initialization is in progress for MSS_MBOX" group.long 0x260++0x7 line.long 0x0 "MSS_CTRL_TPCC_MEM_INIT" bitfld.long 0x0 0. "TPCC_MEM_INIT_TPCC_A_MEMINIT_START,Write_pulse bit field:Writing 1'b1 will start initializing the MSS_TPCCA" "0,1" line.long 0x4 "MSS_CTRL_TPCC_MEM_INIT_DONE" bitfld.long 0x4 0. "TPCC_MEM_INIT_DONE_TPCC_A_MEMINIT_DONE,This field will be high once intialization of MSS_TPCCA is finished. Writing '1' would clear the bit" "0,1" rgroup.long 0x268++0x3 line.long 0x0 "MSS_CTRL_TPCC_MEMINIT_STATUS" bitfld.long 0x0 0. "TPCC_MEMINIT_STATUS_TPCC_A_MEMINIT_STATUS,1'b0: No initialization is happening for MSS_TPCCA1'b1: Initialization is in progress for MSS_TPCCB" "0: No initialization is happening for..,?" group.long 0x300++0x3 line.long 0x0 "MSS_CTRL_TOP_PBIST_KEY_RST" hexmask.long.byte 0x0 4.--7. 1. "TOP_PBIST_KEY_RST_PBIST_ST_RST,MSS PBIST controller will be brought out of reset when value is 0xA" newline hexmask.long.byte 0x0 0.--3. 1. "TOP_PBIST_KEY_RST_PBIST_ST_KEY,Top PBIST Selftest Key. Valid value is 0x5" group.long 0x400++0xB line.long 0x0 "MSS_CTRL_R5SS0_CTI_TRIG_SEL" hexmask.long.byte 0x0 8.--15. 1. "R5SS0_CTI_TRIG_SEL_TRIG1,Used for selecting the trigger source for 1st trigger of MSS_R5SS" newline hexmask.long.byte 0x0 0.--7. 1. "R5SS0_CTI_TRIG_SEL_TRIG0,Used for selecting the trigger source for 0th trigger of MSS_R5SS" line.long 0x4 "MSS_CTRL_R5SS1_CTI_TRIG_SEL" hexmask.long.byte 0x4 8.--15. 1. "R5SS1_CTI_TRIG_SEL_TRIG1,Used for selecting the trigger source for 1st trigger of MSS_R5SS" newline hexmask.long.byte 0x4 0.--7. 1. "R5SS1_CTI_TRIG_SEL_TRIG0,Used for selecting the trigger source for 0th trigger of MSS_R5SS" line.long 0x8 "MSS_CTRL_DBGSS_CTI_TRIG_SEL" hexmask.long.byte 0x8 24.--31. 1. "DBGSS_CTI_TRIG_SEL_TRIG3,Used for selecting the trigger source for 3rd trigger of ONE_MCU_CTI" newline hexmask.long.byte 0x8 16.--23. 1. "DBGSS_CTI_TRIG_SEL_TRIG2,Used for selecting the trigger source for 2nd trigger of ONE_MCU_CTI" newline hexmask.long.byte 0x8 8.--15. 1. "DBGSS_CTI_TRIG_SEL_TRIG1,Used for selecting the trigger source for 1st trigger of ONE_MCU_CTI" newline hexmask.long.byte 0x8 0.--7. 1. "DBGSS_CTI_TRIG_SEL_TRIG0,Used for selecting the trigger source for 0th trigger of ONE_MCU_CTI" group.long 0x420++0x43 line.long 0x0 "MSS_CTRL_MCAN0_HALTEN" bitfld.long 0x0 3. "MCAN0_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x0 2. "MCAN0_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x0 1. "MCAN0_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x0 0. "MCAN0_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x4 "MSS_CTRL_MCAN1_HALTEN" bitfld.long 0x4 3. "MCAN1_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x4 2. "MCAN1_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x4 1. "MCAN1_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x4 0. "MCAN1_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x8 "MSS_CTRL_MCAN2_HALTEN" bitfld.long 0x8 3. "MCAN2_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x8 2. "MCAN2_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x8 1. "MCAN2_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x8 0. "MCAN2_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0xC "MSS_CTRL_MCAN3_HALTEN" bitfld.long 0xC 3. "MCAN3_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0xC 2. "MCAN3_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0xC 1. "MCAN3_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0xC 0. "MCAN3_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x10 "MSS_CTRL_LIN0_HALTEN" bitfld.long 0x10 3. "LIN0_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x10 2. "LIN0_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x10 1. "LIN0_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x10 0. "LIN0_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x14 "MSS_CTRL_LIN1_HALTEN" bitfld.long 0x14 3. "LIN1_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x14 2. "LIN1_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x14 1. "LIN1_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x14 0. "LIN1_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x18 "MSS_CTRL_LIN2_HALTEN" bitfld.long 0x18 3. "LIN2_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x18 2. "LIN2_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x18 1. "LIN2_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x18 0. "LIN2_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x1C "MSS_CTRL_LIN3_HALTEN" bitfld.long 0x1C 3. "LIN3_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x1C 2. "LIN3_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x1C 1. "LIN3_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x1C 0. "LIN3_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x20 "MSS_CTRL_LIN4_HALTEN" bitfld.long 0x20 3. "LIN4_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x20 2. "LIN4_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x20 1. "LIN4_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x20 0. "LIN4_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x24 "MSS_CTRL_I2C0_HALTEN" bitfld.long 0x24 3. "I2C0_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x24 2. "I2C0_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x24 1. "I2C0_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x24 0. "I2C0_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x28 "MSS_CTRL_I2C1_HALTEN" bitfld.long 0x28 3. "I2C1_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x28 2. "I2C1_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x28 1. "I2C1_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x28 0. "I2C1_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x2C "MSS_CTRL_I2C2_HALTEN" bitfld.long 0x2C 3. "I2C2_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x2C 2. "I2C2_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x2C 1. "I2C2_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x2C 0. "I2C2_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x30 "MSS_CTRL_I2C3_HALTEN" bitfld.long 0x30 3. "I2C3_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x30 2. "I2C3_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x30 1. "I2C3_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x30 0. "I2C3_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x34 "MSS_CTRL_RTI0_HALTEN" bitfld.long 0x34 3. "RTI0_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x34 2. "RTI0_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x34 1. "RTI0_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x34 0. "RTI0_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x38 "MSS_CTRL_RTI1_HALTEN" bitfld.long 0x38 3. "RTI1_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x38 2. "RTI1_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x38 1. "RTI1_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x38 0. "RTI1_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x3C "MSS_CTRL_RTI2_HALTEN" bitfld.long 0x3C 3. "RTI2_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x3C 2. "RTI2_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x3C 1. "RTI2_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x3C 0. "RTI2_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x40 "MSS_CTRL_RTI3_HALTEN" bitfld.long 0x40 3. "RTI3_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x40 2. "RTI3_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x40 1. "RTI3_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x40 0. "RTI3_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.long 0x474++0x27 line.long 0x0 "MSS_CTRL_CPSW_HALTEN" bitfld.long 0x0 3. "CPSW_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x0 2. "CPSW_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x0 1. "CPSW_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x0 0. "CPSW_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x4 "MSS_CTRL_MCRC0_HALTEN" bitfld.long 0x4 3. "MCRC0_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x4 2. "MCRC0_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x4 1. "MCRC0_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x4 0. "MCRC0_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x8 "MSS_CTRL_MCAN4_HALTEN" bitfld.long 0x8 3. "MCAN4_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x8 2. "MCAN4_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x8 1. "MCAN4_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x8 0. "MCAN4_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0xC "MSS_CTRL_MCAN5_HALTEN" bitfld.long 0xC 3. "MCAN5_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0xC 2. "MCAN5_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0xC 1. "MCAN5_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0xC 0. "MCAN5_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x10 "MSS_CTRL_MCAN6_HALTEN" bitfld.long 0x10 3. "MCAN6_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x10 2. "MCAN6_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x10 1. "MCAN6_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x10 0. "MCAN6_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x14 "MSS_CTRL_MCAN7_HALTEN" bitfld.long 0x14 3. "MCAN7_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x14 2. "MCAN7_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x14 1. "MCAN7_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x14 0. "MCAN7_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x18 "MSS_CTRL_RTI4_HALTEN" bitfld.long 0x18 3. "RTI4_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x18 2. "RTI4_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x18 1. "RTI4_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x18 0. "RTI4_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x1C "MSS_CTRL_RTI5_HALTEN" bitfld.long 0x1C 3. "RTI5_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x1C 2. "RTI5_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x1C 1. "RTI5_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x1C 0. "RTI5_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x20 "MSS_CTRL_RTI6_HALTEN" bitfld.long 0x20 3. "RTI6_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x20 2. "RTI6_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x20 1. "RTI6_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x20 0. "RTI6_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" line.long 0x24 "MSS_CTRL_RTI7_HALTEN" bitfld.long 0x24 3. "RTI7_HALTEN_CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x24 2. "RTI7_HALTEN_CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x24 1. "RTI7_HALTEN_CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.long 0x24 0. "RTI7_HALTEN_CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.long 0x800++0xB line.long 0x0 "MSS_CTRL_TPTC_DBS_CONFIG" bitfld.long 0x0 4.--5. "TPTC_DBS_CONFIG_TPTC_A1,DBS [default burst size] tieoff value for TPTC A1. DBS tieoff defines optimally sized cmd.Both the read and write controller will always issue commands that are less than or equal to the DBS tieoff value. This will typically be on.." "0,1,2,3" newline bitfld.long 0x0 0.--1. "TPTC_DBS_CONFIG_TPTC_A0,DBS [default burst size] tieoff value for TPTC A0. DBS tieoff defines optimally sized cmd.Both the read and write controller will always issue commands that are less than or equal to the DBS tieoff value. This will typically be on.." "0,1,2,3" line.long 0x4 "MSS_CTRL_TPTC_BOUNDARY_CFG" hexmask.long.byte 0x4 8.--13. 1. "TPTC_BOUNDARY_CFG_TPTC_A1_SIZE,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A1Example: Writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB" newline hexmask.long.byte 0x4 0.--5. 1. "TPTC_BOUNDARY_CFG_TPTC_A0_SIZE,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A0Example: Writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB" line.long 0x8 "MSS_CTRL_TPTC_XID_REORDER_CFG" bitfld.long 0x8 8. "TPTC_XID_REORDER_CFG_TPTC_A1_DISABLE,Writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A1" "0,1" newline bitfld.long 0x8 0. "TPTC_XID_REORDER_CFG_TPTC_A0_DISABLE,Writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A0" "0,1" group.long 0x810++0x1B line.long 0x0 "MSS_CTRL_CPSW_CONTROL" bitfld.long 0x0 24. "CPSW_CONTROL_RGMII2_ID_MODE,Internal delay mode for port 2. Only for TX1'b0 ID mode is disabled1'b1 ID mode is enabled" "0,1" newline bitfld.long 0x0 22. "CPSW_CONTROL_RMII2_REF_CLK_SEL,To select the rmii_ref_clk loopback mux output either from PAD or from MSS_RCM. Write 1'b0 to get clock will be from IO pad[pad loopback]. Write 1'b1 to get clock from internal loopback." "0,1" newline bitfld.long 0x0 20. "CPSW_CONTROL_RMII2_REF_CLK_OE_N,RMII_REF_CLK IO Output enable control1'b0: Output enable1'b1: Output Disable" "0,1" newline bitfld.long 0x0 16.--18. "CPSW_CONTROL_PORT2_MODE_SEL,Port 2 Interface 3'b000 = MII3'b001 = RMII3'b010 = RGMII011 - 111 = Not Supported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "CPSW_CONTROL_RGMII1_ID_MODE,Internal delay mode for port 1. Only for TX1'b0 ID mode is disabled1'b1 ID mode is enabled" "0,1" newline bitfld.long 0x0 6. "CPSW_CONTROL_RMII1_REF_CLK_SEL,To select the rmii_ref_clk loopback mux output either from PAD or from MSS_RCM. Write 1'b0 to get clock will be from IO pad[pad loopback]. Write 1'b1 to get clock from internal source" "0,1" newline bitfld.long 0x0 4. "CPSW_CONTROL_RMII1_REF_CLK_OE_N,RMII_REF_CLK IO Output enable control1'b0: Output enable1'b1: Output Disable" "0,1" newline bitfld.long 0x0 0.--2. "CPSW_CONTROL_PORT1_MODE_SEL,Port 1 Interface 3'b000 = MII3'b001 = RMII3'b010 = RGMII011 - 111 = Not Supported" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_OSPI_CONFIG" bitfld.long 0x4 12.--14. "OSPI_CONFIG_RTXIP_PENDING,Real time xip indication for OSPIWrite 3'b111 for real time xip is pendingWrite 3'b000 for real time xip is doneconfiguration changes must be done when FSS is idle/not configured/no transactions" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "OSPI_CONFIG_ICLK_SEL,Write 3'b111 to switch to loopback clock as OSPI input IO clockWrite 3'b000 to switch to OSPI DQS as OSPI input IO clockconfiguration changes must be done when FSS is idle/not configured/no transactions" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "OSPI_CONFIG_EXT_CLK,Write 3'b111 to external clock as OSPI baud clock source - needed for DFT IO char." "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_CTRL_PRU_ICSS_IDLE_CONTROL" bitfld.long 0x8 0. "PRU_ICSS_IDLE_CONTROL_NOGATE,Writing 1'b0 will enable local auto-clock gating [lower power] at IP level with increase in access/functional latency. Following IPs are controlled with this signalICSSM" "0,1" line.long 0xC "MSS_CTRL_PRU_ICSS_PRU0_GPI_SEL" hexmask.long 0xC 0.--29. 1. "PRU_ICSS_PRU0_GPI_SEL_SEL,GPI or PWMXBAR select for ICSM Port03'b000 GPI3'111 PWMXBAR" line.long 0x10 "MSS_CTRL_PRU_ICSS_PRU1_GPI_SEL" hexmask.long 0x10 0.--29. 1. "PRU_ICSS_PRU1_GPI_SEL_SEL,GPI or PWMXBAR select for ICSM Port03'b000 GPI3'111 PWMXBAR" line.long 0x14 "MSS_CTRL_PRU_ICSS_PRU0_GPIO_OUT_CTRL" hexmask.long 0x14 0.--29. 1. "PRU_ICSS_PRU0_GPIO_OUT_CTRL_OUTDISABLE,GPO output disable for ICSSM Port 0 IO. Disable output for using the pin as input. Each Bit maps to the corresponding bit in the IO3'b000 Output Enable3'111 Output Disable" line.long 0x18 "MSS_CTRL_PRU_ICSS_PRU1_GPIO_OUT_CTRL" hexmask.long 0x18 0.--29. 1. "PRU_ICSS_PRU1_GPIO_OUT_CTRL_OUTDISABLE,GPO output disable for ICSSM Port 1 IO. Disable output for using the pin as input. Each Bit maps to the corresponding bit in the IO3'b000 Output Enable3'111 Output Disable" group.long 0x830++0x17 line.long 0x0 "MSS_CTRL_TPCC0_INTAGG_MASK" bitfld.long 0x0 17. "TPCC0_INTAGG_MASK_TPTC_A1,Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 16. "TPCC0_INTAGG_MASK_TPTC_A0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 8. "TPCC0_INTAGG_MASK_TPCC_A_INT7,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 7. "TPCC0_INTAGG_MASK_TPCC_A_INT6,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 6. "TPCC0_INTAGG_MASK_TPCC_A_INT5,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 5. "TPCC0_INTAGG_MASK_TPCC_A_INT4,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 4. "TPCC0_INTAGG_MASK_TPCC_A_INT3,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "TPCC0_INTAGG_MASK_TPCC_A_INT2,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "TPCC0_INTAGG_MASK_TPCC_A_INT1,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "TPCC0_INTAGG_MASK_TPCC_A_INT0,Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "TPCC0_INTAGG_MASK_TPCC_A_INTG,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_TPCC0_INTAGG_STATUS" bitfld.long 0x4 17. "TPCC0_INTAGG_STATUS_TPTC_A1,Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 16. "TPCC0_INTAGG_STATUS_TPTC_A0,Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 8. "TPCC0_INTAGG_STATUS_TPCC_A_INT7,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 7. "TPCC0_INTAGG_STATUS_TPCC_A_INT6,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 6. "TPCC0_INTAGG_STATUS_TPCC_A_INT5,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 5. "TPCC0_INTAGG_STATUS_TPCC_A_INT4,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 4. "TPCC0_INTAGG_STATUS_TPCC_A_INT3,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "TPCC0_INTAGG_STATUS_TPCC_A_INT2,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "TPCC0_INTAGG_STATUS_TPCC_A_INT1,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "TPCC0_INTAGG_STATUS_TPCC_A_INT0,Status of Interrupt from TPCC A Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "TPCC0_INTAGG_STATUS_TPCC_A_INTG,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_TPCC0_INTAGG_STATUS_RAW" bitfld.long 0x8 17. "TPCC0_INTAGG_STATUS_RAW_TPTC_A1,Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in TPCC0_INTAGG_MASK" "0,1" newline bitfld.long 0x8 16. "TPCC0_INTAGG_STATUS_RAW_TPTC_A0,Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC0_INTAGG_MASK" "0,1" newline bitfld.long 0x8 8. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT7,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 7. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT6,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 6. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT5,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 5. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT4,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 4. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT3,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 3. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT2,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 2. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT1,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.long 0x8 1. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INT0,Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in TPCC0_INTAGG_MASK" "0,1" newline bitfld.long 0x8 0. "TPCC0_INTAGG_STATUS_RAW_TPCC_A_INTG,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" line.long 0xC "MSS_CTRL_INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL" bitfld.long 0xC 20.--22. "INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL_MISC_PERIPH_DYNAMIC_CLK_GATE_EN,dynamic clock gate feature enable. Multibit writeWrite 0x111 to enable Write 0x000 to disable2 extra clock latency for the first access after the clock is gated and SCRP_PERI is not.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 16.--18. "INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL_MISC_CONFIG1_DYNAMIC_CLK_GATE_EN,dynamic clock gate feature enable. Multibit writeWrite 0x111 to enable Write 0x000 to disable2 extra clock latency for the first access after the clock is gated and SCRP_PERI is not.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL_MISC_CONFIG0_DYNAMIC_CLK_GATE_EN,dynamic clock gate feature enable. Multibit writeWrite 0x111 to enable Write 0x000 to disable2 extra clock latency for the first access after the clock is gated and SCRP_PERI is not.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--10. "INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL_PERI_DYNAMIC_CLK_GATE_EN,dynamic clock gate feature enable. Multibit writeWrite 0x111 to enable Write 0x000 to disable2 extra clock latency for the first access after the clock is gated and SCRP_PERI is not gated" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4.--6. "INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL_INFRA_G1_DYNAMIC_CLK_GATE_EN,dynamic clock gate feature enable. Multibit writeWrite 0x111 to enable Write 0x000 to disable2 extra clock latency for the first access after the clock is gated and SCRP_PERI is not.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "INTERCONNECT_CLK_GATE_DYNAMIC_CONTROL_INFRA_G0_DYNAMIC_CLK_GATE_EN,dynamic clock gate feature enable. Multibit writeWrite 0x111 to enable Write 0x000 to disable2 extra clock latency for the first access after the clock is gated and SCRP_PERI is not.." "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_CTRL_OSPI_BOOT_CONFIG_MASK" hexmask.long.tbyte 0x10 0.--19. 1. "OSPI_BOOT_CONFIG_MASK_BOOT_SIZE,OSPI boot size registerconfiguration changes must be done when FSS is idle/not configured/no transactions" line.long 0x14 "MSS_CTRL_OSPI_BOOT_CONFIG_SEG" hexmask.long.tbyte 0x14 0.--19. 1. "OSPI_BOOT_CONFIG_SEG_BOOT_SEG,OSPI segment selector for programmed boot sizeconfiguration changes must be done when FSS is idle/not configured/no transactions" rgroup.long 0x848++0x3 line.long 0x0 "MSS_CTRL_PRU_ICSS_RX_ERR_COUNTER" hexmask.long.byte 0x0 8.--15. 1. "PRU_ICSS_RX_ERR_COUNTER_MII1_RXERR_CNT,Counts the error in MII1_RX_CLK" newline hexmask.long.byte 0x0 0.--7. 1. "PRU_ICSS_RX_ERR_COUNTER_MII0_RXERR_CNT,Counts the error in MII0_RX_CLK" group.long 0x84C++0x3 line.long 0x0 "MSS_CTRL_PRU_ICSS_RX_ERR_COUNTER_CLR" bitfld.long 0x0 1. "PRU_ICSS_RX_ERR_COUNTER_CLR_MII1_RXERR_WRT1CLR,Clears the Counter which counts the error in MII1_RX_CLK1'b0: Inactive clear1'b1: Clears the counter" "0,1" newline bitfld.long 0x0 0. "PRU_ICSS_RX_ERR_COUNTER_CLR_MII0_RXERR_WRT1CLR,Clears the Counter which counts the error in MII0_RX_CLK1'b0: Inactive clear1'b1: Clears the counter" "0,1" group.long 0x1008++0x1B line.long 0x0 "MSS_CTRL_LOCK0_KICK0,- KICK0 component." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "MSS_CTRL_LOCK0_KICK1,- KICK1 component." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "MSS_CTRL_INTR_RAW_STATUS,Interrupt Raw Status/Set Register." bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "MSS_CTRL_INTR_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear register." bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "MSS_CTRL_INTR_ENABLE,Interrupt Enable register." bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "MSS_CTRL_INTR_ENABLE_CLEAR,Interrupt Enable Clear register." bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "MSS_CTRL_EOI,EOI register." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "MSS_CTRL_FAULT_ADDRESS,Fault Address register." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "MSS_CTRL_FAULT_TYPE_STATUS,Fault Type Status register." bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." line.long 0x8 "MSS_CTRL_FAULT_ATTR_STATUS,Fault Attribute Status register." hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "MSS_CTRL_FAULT_CLEAR,Fault Clear register." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" group.long 0x4000++0x13 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_MBOX_WRITE_DONE" bitfld.long 0x0 28. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_7,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_6,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_5,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_4,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_3,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_2,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_1,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "R5SS0_CORE0_MBOX_WRITE_DONE_PROC_0,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_MBOX_READ_REQ" bitfld.long 0x4 28. "R5SS0_CORE0_MBOX_READ_REQ_PROC_7,This is request from processor 7 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "R5SS0_CORE0_MBOX_READ_REQ_PROC_6,This is request from processor 6 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "R5SS0_CORE0_MBOX_READ_REQ_PROC_5,This is request from processor 5 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "R5SS0_CORE0_MBOX_READ_REQ_PROC_4,This is request from processor 4 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "R5SS0_CORE0_MBOX_READ_REQ_PROC_3,This is request from processor 3 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "R5SS0_CORE0_MBOX_READ_REQ_PROC_2,This is request from processor 2 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "R5SS0_CORE0_MBOX_READ_REQ_PROC_1,This is request from processor 1 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "R5SS0_CORE0_MBOX_READ_REQ_PROC_0,This is request from processor 0 to mss_cr5a. Requesting it to read from mailbox." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK" hexmask.long.byte 0x8 0.--7. 1. "R5SS0_CORE0_MBOX_READ_DONE_ACK_PROC,Write pulse bit field:For bits 0 to7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" line.long 0xC "MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE" bitfld.long 0xC 28. "R5SS0_CORE0_MBOX_READ_DONE_PROC_7,This register should be written once finishing Reading from proc7's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 24. "R5SS0_CORE0_MBOX_READ_DONE_PROC_6,This register should be written once finishing Reading from proc6's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 20. "R5SS0_CORE0_MBOX_READ_DONE_PROC_5,This register should be written once finishing Reading from proc5's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 16. "R5SS0_CORE0_MBOX_READ_DONE_PROC_4,This register should be written once finishing Reading from proc4's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 12. "R5SS0_CORE0_MBOX_READ_DONE_PROC_3,This register should be written once finishing Reading from proc3's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 8. "R5SS0_CORE0_MBOX_READ_DONE_PROC_2,This register should be written once finishing Reading from proc2's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 4. "R5SS0_CORE0_MBOX_READ_DONE_PROC_1,This register should be written once finishing Reading from proc1's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 0. "R5SS0_CORE0_MBOX_READ_DONE_PROC_0,This register should be written once finishing Reading from proc0's mailbox written by CR5A" "0,1" line.long 0x10 "MSS_CTRL_R5SS0_CORE0_SW_INT" bitfld.long 0x10 0. "R5SS0_CORE0_SW_INT_PULSE,Write_pulse bit field:Writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.long 0x4020++0xB line.long 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CORE0_MASK" bitfld.long 0x0 22. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_F_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_E_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_R5SS1_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_R5SS0_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_OPTI_FLASH_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_HSM_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B1_AHB_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A1_AHB_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B0_AHB_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A0_AHB_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_SCRM2SCRP1_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_SCRM2SCRP0_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_OSPI_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_MBOX_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_DTHE_A_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B1_AXIS_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A1_AXIS_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B0_AXIS_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A0_AXIS_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_D_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_C_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_B_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_A_ADDR_ERR0,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CORE0_STATUS" bitfld.long 0x4 22. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_F_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_E_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_R5SS1_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_R5SS0_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_OPTI_FLASH_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_HSM_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B1_AHB_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A1_AHB_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B0_AHB_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A0_AHB_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_SCRM2SCRP1_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_SCRM2SCRP0_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_OSPI_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_MBOX_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_DTHE_A_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B1_AXIS_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A1_AXIS_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B0_AXIS_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A0_AXIS_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_D_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_C_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_B_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_A_ADDR_ERR0,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CORE0_STATUS_RAW" bitfld.long 0x8 22. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_F_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_E_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_R5SS1_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_R5SS0_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_OPTI_FLASH_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_HSM_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B1_AHB_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A1_AHB_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B0_AHB_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A0_AHB_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_SCRM2SCRP1_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_SCRM2SCRP0_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_OSPI_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_MBOX_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_DTHE_A_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B1_AXIS_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A1_AXIS_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B0_AXIS_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A0_AXIS_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_D_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_C_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_B_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_A_ADDR_ERR0,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.long 0x4030++0xB line.long 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CORE0_MASK" bitfld.long 0x0 22. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_F_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_E_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_R5SS1_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_R5SS0_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_OPTI_FLASH_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_HSM_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B1_AHB_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A1_AHB_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B0_AHB_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A0_AHB_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_SCRM2SCRP1_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_SCRM2SCRP0_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_OSPI_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_MBOX_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_DTHE_A_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B1_AXIS_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A1_AXIS_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5B0_AXIS_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_CR5A0_AXIS_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_D_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_C_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_B_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_PROT_ERRAGG_R5SS0_CPU0_MASK_MPU_L2_BANK_A_PROT_ERR0,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CORE0_STATUS" bitfld.long 0x4 22. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_F_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_E_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_R5SS1_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_R5SS0_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_OPTI_FLASH_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_HSM_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B1_AHB_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A1_AHB_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B0_AHB_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A0_AHB_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_SCRM2SCRP1_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_SCRM2SCRP0_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_OSPI_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_MBOX_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_DTHE_A_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B1_AXIS_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A1_AXIS_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5B0_AXIS_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_CR5A0_AXIS_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_D_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_C_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_B_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_MPU_L2_BANK_A_PROT_ERR0,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CORE0_STATUS_RAW" bitfld.long 0x8 22. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_F_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_E_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_R5SS1_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_R5SS0_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_OPTI_FLASH_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_HSM_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B1_AHB_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A1_AHB_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B0_AHB_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A0_AHB_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_SCRM2SCRP1_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_SCRM2SCRP0_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_OSPI_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_MBOX_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_DTHE_A_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B1_AXIS_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A1_AXIS_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5B0_AXIS_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_CR5A0_AXIS_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_D_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_C_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_B_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW_MPU_L2_BANK_A_PROT_ERR0,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0x8000++0x13 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_MBOX_WRITE_DONE" bitfld.long 0x0 28. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_7,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_6,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_5,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_4,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_3,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_2,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_1,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "R5SS0_CORE1_MBOX_WRITE_DONE_PROC_0,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_MBOX_READ_REQ" bitfld.long 0x4 28. "R5SS0_CORE1_MBOX_READ_REQ_PROC_7,This is request from processor 7 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "R5SS0_CORE1_MBOX_READ_REQ_PROC_6,This is request from processor 6 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "R5SS0_CORE1_MBOX_READ_REQ_PROC_5,This is request from processor 5 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "R5SS0_CORE1_MBOX_READ_REQ_PROC_4,This is request from processor 4 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "R5SS0_CORE1_MBOX_READ_REQ_PROC_3,This is request from processor 3 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "R5SS0_CORE1_MBOX_READ_REQ_PROC_2,This is request from processor 2 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "R5SS0_CORE1_MBOX_READ_REQ_PROC_1,This is request from processor 1 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "R5SS0_CORE1_MBOX_READ_REQ_PROC_0,This is request from processor 0 to mss_CR5B. Requesting it to read from mailbox." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK" hexmask.long.byte 0x8 0.--7. 1. "R5SS0_CORE1_MBOX_READ_DONE_ACK_PROC,Write pulse bit field:For bits 0 to7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" line.long 0xC "MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE" bitfld.long 0xC 28. "R5SS0_CORE1_MBOX_READ_DONE_PROC_7,This register should be written once finishing Reading from proc7's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 24. "R5SS0_CORE1_MBOX_READ_DONE_PROC_6,This register should be written once finishing Reading from proc6's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 20. "R5SS0_CORE1_MBOX_READ_DONE_PROC_5,This register should be written once finishing Reading from proc5's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 16. "R5SS0_CORE1_MBOX_READ_DONE_PROC_4,This register should be written once finishing Reading from proc4's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 12. "R5SS0_CORE1_MBOX_READ_DONE_PROC_3,This register should be written once finishing Reading from proc3's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 8. "R5SS0_CORE1_MBOX_READ_DONE_PROC_2,This register should be written once finishing Reading from proc2's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 4. "R5SS0_CORE1_MBOX_READ_DONE_PROC_1,This register should be written once finishing Reading from proc1's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 0. "R5SS0_CORE1_MBOX_READ_DONE_PROC_0,This register should be written once finishing Reading from proc0's mailbox written by CR5B" "0,1" line.long 0x10 "MSS_CTRL_R5SS0_CORE1_SW_INT" bitfld.long 0x10 0. "R5SS0_CORE1_SW_INT_PULSE,Write_pulse bit field:Writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.long 0x8020++0xB line.long 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CORE1_MASK" bitfld.long 0x0 22. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_F_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_E_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_R5SS1_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_R5SS0_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_OPTI_FLASH_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_HSM_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B1_AHB_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A1_AHB_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B0_AHB_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A0_AHB_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_SCRM2SCRP1_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_SCRM2SCRP0_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_OSPI_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_MBOX_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_DTHE_A_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B1_AXIS_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A1_AXIS_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B0_AXIS_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A0_AXIS_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_D_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_C_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_B_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_A_ADDR_ERR1,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CORE1_STATUS" bitfld.long 0x4 22. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_F_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_E_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_R5SS1_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_R5SS0_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_OPTI_FLASH_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_HSM_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B1_AHB_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A1_AHB_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B0_AHB_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A0_AHB_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_SCRM2SCRP1_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_SCRM2SCRP0_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_OSPI_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_MBOX_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_DTHE_A_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B1_AXIS_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A1_AXIS_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B0_AXIS_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A0_AXIS_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_D_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_C_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_B_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_A_ADDR_ERR1,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CORE1_STATUS_RAW" bitfld.long 0x8 22. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_F_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_E_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_R5SS1_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_R5SS0_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_OPTI_FLASH_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_HSM_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B1_AHB_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A1_AHB_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B0_AHB_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A0_AHB_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_SCRM2SCRP1_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_SCRM2SCRP0_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_OSPI_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_MBOX_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_DTHE_A_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B1_AXIS_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A1_AXIS_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B0_AXIS_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A0_AXIS_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_D_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_C_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_B_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_A_ADDR_ERR1,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.long 0x8030++0xB line.long 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CORE1_MASK" bitfld.long 0x0 22. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_F_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_E_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_R5SS1_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_R5SS0_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_OPTI_FLASH_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_HSM_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B1_AHB_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A1_AHB_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B0_AHB_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A0_AHB_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_SCRM2SCRP1_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_SCRM2SCRP0_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_OSPI_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_MBOX_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_DTHE_A_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B1_AXIS_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A1_AXIS_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5B0_AXIS_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_CR5A0_AXIS_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_D_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_C_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_B_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_PROT_ERRAGG_R5SS0_CPU1_MASK_MPU_L2_BANK_A_PROT_ERR1,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CORE1_STATUS" bitfld.long 0x4 22. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_F_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_E_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_R5SS1_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_R5SS0_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_OPTI_FLASH_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_HSM_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B1_AHB_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A1_AHB_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B0_AHB_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A0_AHB_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_SCRM2SCRP1_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_SCRM2SCRP0_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_OSPI_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_MBOX_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_DTHE_A_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B1_AXIS_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A1_AXIS_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5B0_AXIS_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_CR5A0_AXIS_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_D_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_C_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_B_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_MPU_L2_BANK_A_PROT_ERR1,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CORE1_STATUS_RAW" bitfld.long 0x8 22. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_F_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_E_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_R5SS1_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_R5SS0_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_OPTI_FLASH_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_HSM_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B1_AHB_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A1_AHB_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B0_AHB_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A0_AHB_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_SCRM2SCRP1_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_SCRM2SCRP0_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_OSPI_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_MBOX_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_DTHE_A_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B1_AXIS_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A1_AXIS_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5B0_AXIS_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_CR5A0_AXIS_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_D_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_C_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_B_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW_MPU_L2_BANK_A_PROT_ERR1,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0xC000++0x13 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_MBOX_WRITE_DONE" bitfld.long 0x0 28. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_7,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_6,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_5,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_4,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_3,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_2,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_1,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "R5SS1_CORE0_MBOX_WRITE_DONE_PROC_0,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_MBOX_READ_REQ" bitfld.long 0x4 28. "R5SS1_CORE0_MBOX_READ_REQ_PROC_7,This is request from processor 7 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "R5SS1_CORE0_MBOX_READ_REQ_PROC_6,This is request from processor 6 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "R5SS1_CORE0_MBOX_READ_REQ_PROC_5,This is request from processor 5 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "R5SS1_CORE0_MBOX_READ_REQ_PROC_4,This is request from processor 4 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "R5SS1_CORE0_MBOX_READ_REQ_PROC_3,This is request from processor 3 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "R5SS1_CORE0_MBOX_READ_REQ_PROC_2,This is request from processor 2 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "R5SS1_CORE0_MBOX_READ_REQ_PROC_1,This is request from processor 1 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "R5SS1_CORE0_MBOX_READ_REQ_PROC_0,This is request from processor 0 to mss_cr5a. Requesting it to read from mailbox." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK" hexmask.long.byte 0x8 0.--7. 1. "R5SS1_CORE0_MBOX_READ_DONE_ACK_PROC,Write pulse bit field:For bits 0 to7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" line.long 0xC "MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE" bitfld.long 0xC 28. "R5SS1_CORE0_MBOX_READ_DONE_PROC_7,This register should be written once finishing Reading from proc7's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 24. "R5SS1_CORE0_MBOX_READ_DONE_PROC_6,This register should be written once finishing Reading from proc6's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 20. "R5SS1_CORE0_MBOX_READ_DONE_PROC_5,This register should be written once finishing Reading from proc5's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 16. "R5SS1_CORE0_MBOX_READ_DONE_PROC_4,This register should be written once finishing Reading from proc4's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 12. "R5SS1_CORE0_MBOX_READ_DONE_PROC_3,This register should be written once finishing Reading from proc3's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 8. "R5SS1_CORE0_MBOX_READ_DONE_PROC_2,This register should be written once finishing Reading from proc2's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 4. "R5SS1_CORE0_MBOX_READ_DONE_PROC_1,This register should be written once finishing Reading from proc1's mailbox written by CR5A" "0,1" newline bitfld.long 0xC 0. "R5SS1_CORE0_MBOX_READ_DONE_PROC_0,This register should be written once finishing Reading from proc0's mailbox written by CR5A" "0,1" line.long 0x10 "MSS_CTRL_R5SS1_CORE0_SW_INT" bitfld.long 0x10 0. "R5SS1_CORE0_SW_INT_PULSE,Write_pulse bit field:Writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.long 0xC020++0xB line.long 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CORE0_MASK" bitfld.long 0x0 22. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_F_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_E_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_R5SS1_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_R5SS0_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_OPTI_FLASH_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_HSM_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B1_AHB_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A1_AHB_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B0_AHB_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A0_AHB_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_SCRM2SCRP1_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_SCRM2SCRP0_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_OSPI_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_MBOX_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_DTHE_A_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B1_AXIS_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A1_AXIS_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B0_AXIS_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A0_AXIS_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_D_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_C_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_B_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_A_ADDR_ERR2,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CORE0_STATUS" bitfld.long 0x4 22. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_F_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_E_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_R5SS1_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_R5SS0_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_OPTI_FLASH_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_HSM_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B1_AHB_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A1_AHB_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B0_AHB_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A0_AHB_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_SCRM2SCRP1_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_SCRM2SCRP0_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_OSPI_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_MBOX_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_DTHE_A_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B1_AXIS_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A1_AXIS_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B0_AXIS_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A0_AXIS_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_D_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_C_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_B_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_A_ADDR_ERR2,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CORE0_STATUS_RAW" bitfld.long 0x8 22. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_F_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_E_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_R5SS1_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_R5SS0_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_OPTI_FLASH_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_HSM_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B1_AHB_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A1_AHB_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B0_AHB_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A0_AHB_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_SCRM2SCRP1_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_SCRM2SCRP0_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_OSPI_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_MBOX_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_DTHE_A_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B1_AXIS_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A1_AXIS_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B0_AXIS_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A0_AXIS_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_D_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_C_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_B_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_A_ADDR_ERR2,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.long 0xC030++0xB line.long 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CORE0_MASK" bitfld.long 0x0 22. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_F_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_E_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_R5SS1_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_R5SS0_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_OPTI_FLASH_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_HSM_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B1_AHB_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A1_AHB_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B0_AHB_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A0_AHB_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_SCRM2SCRP1_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_SCRM2SCRP0_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_OSPI_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_MBOX_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_DTHE_A_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B1_AXIS_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A1_AXIS_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5B0_AXIS_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_CR5A0_AXIS_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_D_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_C_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_B_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_PROT_ERRAGG_R5SS1_CPU0_MASK_MPU_L2_BANK_A_PROT_ERR2,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CORE0_STATUS" bitfld.long 0x4 22. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_F_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_E_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_R5SS1_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_R5SS0_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_OPTI_FLASH_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_HSM_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B1_AHB_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A1_AHB_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B0_AHB_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A0_AHB_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_SCRM2SCRP1_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_SCRM2SCRP0_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_OSPI_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_MBOX_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_DTHE_A_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B1_AXIS_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A1_AXIS_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5B0_AXIS_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_CR5A0_AXIS_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_D_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_C_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_B_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_MPU_L2_BANK_A_PROT_ERR2,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CORE0_STATUS_RAW" bitfld.long 0x8 22. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_F_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_E_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_R5SS1_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_R5SS0_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_OPTI_FLASH_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_HSM_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B1_AHB_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A1_AHB_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B0_AHB_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A0_AHB_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_SCRM2SCRP1_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_SCRM2SCRP0_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_OSPI_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_MBOX_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_DTHE_A_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B1_AXIS_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A1_AXIS_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5B0_AXIS_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_CR5A0_AXIS_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_D_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_C_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_B_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW_MPU_L2_BANK_A_PROT_ERR2,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0x10000++0x13 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_MBOX_WRITE_DONE" bitfld.long 0x0 28. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_7,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_6,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_5,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_4,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_3,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_2,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_1,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "R5SS1_CORE1_MBOX_WRITE_DONE_PROC_0,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_MBOX_READ_REQ" bitfld.long 0x4 28. "R5SS1_CORE1_MBOX_READ_REQ_PROC_7,This is request from processor 7 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "R5SS1_CORE1_MBOX_READ_REQ_PROC_6,This is request from processor 6 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "R5SS1_CORE1_MBOX_READ_REQ_PROC_5,This is request from processor 5 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "R5SS1_CORE1_MBOX_READ_REQ_PROC_4,This is request from processor 4 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "R5SS1_CORE1_MBOX_READ_REQ_PROC_3,This is request from processor 3 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "R5SS1_CORE1_MBOX_READ_REQ_PROC_2,This is request from processor 2 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "R5SS1_CORE1_MBOX_READ_REQ_PROC_1,This is request from processor 1 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "R5SS1_CORE1_MBOX_READ_REQ_PROC_0,This is request from processor 0 to mss_CR5B. Requesting it to read from mailbox." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK" hexmask.long.byte 0x8 0.--7. 1. "R5SS1_CORE1_MBOX_READ_DONE_ACK_PROC,Write pulse bit field:For bits 0 to7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" line.long 0xC "MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE" bitfld.long 0xC 28. "R5SS1_CORE1_MBOX_READ_DONE_PROC_7,This register should be written once finishing Reading from proc7's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 24. "R5SS1_CORE1_MBOX_READ_DONE_PROC_6,This register should be written once finishing Reading from proc6's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 20. "R5SS1_CORE1_MBOX_READ_DONE_PROC_5,This register should be written once finishing Reading from proc5's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 16. "R5SS1_CORE1_MBOX_READ_DONE_PROC_4,This register should be written once finishing Reading from proc4's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 12. "R5SS1_CORE1_MBOX_READ_DONE_PROC_3,This register should be written once finishing Reading from proc3's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 8. "R5SS1_CORE1_MBOX_READ_DONE_PROC_2,This register should be written once finishing Reading from proc2's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 4. "R5SS1_CORE1_MBOX_READ_DONE_PROC_1,This register should be written once finishing Reading from proc1's mailbox written by CR5B" "0,1" newline bitfld.long 0xC 0. "R5SS1_CORE1_MBOX_READ_DONE_PROC_0,This register should be written once finishing Reading from proc0's mailbox written by CR5B" "0,1" line.long 0x10 "MSS_CTRL_R5SS1_CORE1_SW_INT" bitfld.long 0x10 0. "R5SS1_CORE1_SW_INT_PULSE,Write_pulse bit field:Writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.long 0x10020++0xB line.long 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CORE1_MASK" bitfld.long 0x0 22. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_F_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_E_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_R5SS1_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_R5SS0_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_OPTI_FLASH_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_HSM_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B1_AHB_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A1_AHB_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B0_AHB_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A0_AHB_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_SCRM2SCRP1_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_SCRM2SCRP0_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_OSPI_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_MBOX_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_DTHE_A_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B1_AXIS_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A1_AXIS_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B0_AXIS_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A0_AXIS_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_D_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_C_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_B_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_A_ADDR_ERR3,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CORE1_STATUS" bitfld.long 0x4 22. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_F_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_E_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_R5SS1_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_R5SS0_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_OPTI_FLASH_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_HSM_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B1_AHB_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A1_AHB_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B0_AHB_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A0_AHB_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_SCRM2SCRP1_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_SCRM2SCRP0_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_OSPI_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_MBOX_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_DTHE_A_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B1_AXIS_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A1_AXIS_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B0_AXIS_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A0_AXIS_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_D_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_C_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_B_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_A_ADDR_ERR3,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CORE1_STATUS_RAW" bitfld.long 0x8 22. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_F_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_E_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_R5SS1_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_R5SS0_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_OPTI_FLASH_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_HSM_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B1_AHB_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A1_AHB_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B0_AHB_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A0_AHB_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_SCRM2SCRP1_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_SCRM2SCRP0_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_OSPI_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_MBOX_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_DTHE_A_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B1_AXIS_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A1_AXIS_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B0_AXIS_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A0_AXIS_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_D_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_C_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_B_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_A_ADDR_ERR3,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.long 0x10030++0xB line.long 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CORE1_MASK" bitfld.long 0x0 22. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_F_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_E_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_R5SS1_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_R5SS0_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_OPTI_FLASH_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_HSM_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B1_AHB_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A1_AHB_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B0_AHB_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A0_AHB_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_SCRM2SCRP1_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_SCRM2SCRP0_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_OSPI_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_MBOX_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_DTHE_A_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B1_AXIS_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A1_AXIS_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5B0_AXIS_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_CR5A0_AXIS_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_D_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_C_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_B_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "MPU_PROT_ERRAGG_R5SS1_CPU1_MASK_MPU_L2_BANK_A_PROT_ERR3,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CORE1_STATUS" bitfld.long 0x4 22. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_F_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_E_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_R5SS1_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_R5SS0_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_OPTI_FLASH_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_HSM_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B1_AHB_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A1_AHB_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B0_AHB_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A0_AHB_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_SCRM2SCRP1_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_SCRM2SCRP0_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_OSPI_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_MBOX_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_DTHE_A_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B1_AXIS_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A1_AXIS_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5B0_AXIS_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_CR5A0_AXIS_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_D_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_C_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_B_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_MPU_L2_BANK_A_PROT_ERR3,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CORE1_STATUS_RAW" bitfld.long 0x8 22. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_F_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_E_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_R5SS1_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_R5SS0_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_OPTI_FLASH_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_HSM_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B1_AHB_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A1_AHB_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B0_AHB_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A0_AHB_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_SCRM2SCRP1_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_SCRM2SCRP0_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_OSPI_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_MBOX_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_DTHE_A_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B1_AXIS_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A1_AXIS_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5B0_AXIS_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_CR5A0_AXIS_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_D_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_C_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_B_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW_MPU_L2_BANK_A_PROT_ERR3,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0x14000++0x1F line.long 0x0 "MSS_CTRL_PRU_ICSS_PRU0_MBOX_WRITE_DONE" bitfld.long 0x0 28. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_7,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_6,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_5,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_4,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_3,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_2,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_1,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "PRU_ICSS_PRU0_MBOX_WRITE_DONE_PROC_0,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_PRU_ICSS_PRU0_MBOX_READ_REQ" bitfld.long 0x4 28. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_7,This is request from processor 7 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_6,This is request from processor 6 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_5,This is request from processor 5 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_4,This is request from processor 4 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_3,This is request from processor 3 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_2,This is request from processor 2 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_1,This is request from processor 1 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "PRU_ICSS_PRU0_MBOX_READ_REQ_PROC_0,This is request from processor 0 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" line.long 0x8 "MSS_CTRL_PRU_ICSS_PRU0_MBOX_READ_DONE_ACK" hexmask.long.byte 0x8 0.--7. 1. "PRU_ICSS_PRU0_MBOX_READ_DONE_ACK_PROC,Write pulse bit field:For bits 0 to7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU0.For bits 8 to15:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU1." line.long 0xC "MSS_CTRL_PRU_ICSS_PRU0_MBOX_READ_DONE" bitfld.long 0xC 28. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_7,This register should be written once finishing Reading from corresponding proc7's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 24. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_6,This register should be written once finishing Reading from corresponding proc6's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 20. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_5,This register should be written once finishing Reading from corresponding proc5's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 16. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_4,This register should be written once finishing Reading from corresponding proc4's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 12. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_3,This register should be written once finishing Reading from corresponding proc3's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 8. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_2,This register should be written once finishing Reading from corresponding proc2's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 4. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_1,This register should be written once finishing Reading from corresponding proc1's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0xC 0. "PRU_ICSS_PRU0_MBOX_READ_DONE_PROC_0,This register should be written once finishing Reading from corresponding proc0's mailbox written by ICSSM_PRU" "0,1" line.long 0x10 "MSS_CTRL_PRU_ICSS_PRU1_MBOX_WRITE_DONE" bitfld.long 0x10 28. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_7,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x10 24. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_6,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x10 20. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_5,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x10 16. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_4,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x10 12. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_3,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x10 8. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_2,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x10 4. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_1,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x10 0. "PRU_ICSS_PRU1_MBOX_WRITE_DONE_PROC_0,Write pulse bit field:This register should be written once finishing Writing into the mailbox memory of processor 0" "0,1" line.long 0x14 "MSS_CTRL_PRU_ICSS_PRU1_MBOX_READ_REQ" bitfld.long 0x14 28. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_7,This is request from processor 7 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 24. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_6,This is request from processor 6 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 20. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_5,This is request from processor 5 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 16. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_4,This is request from processor 4 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 12. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_3,This is request from processor 3 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 8. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_2,This is request from processor 2 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 4. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_1,This is request from processor 1 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x14 0. "PRU_ICSS_PRU1_MBOX_READ_REQ_PROC_0,This is request from processor 0 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" line.long 0x18 "MSS_CTRL_PRU_ICSS_PRU1_MBOX_READ_DONE_ACK" hexmask.long.byte 0x18 0.--7. 1. "PRU_ICSS_PRU1_MBOX_READ_DONE_ACK_PROC,Write pulse bit field:For bits 0 to7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU0.For bits 8 to15:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU1." line.long 0x1C "MSS_CTRL_PRU_ICSS_PRU1_MBOX_READ_DONE" bitfld.long 0x1C 28. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_7,This register should be written once finishing Reading from corresponding proc7's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 24. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_6,This register should be written once finishing Reading from corresponding proc6's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 20. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_5,This register should be written once finishing Reading from corresponding proc5's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 16. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_4,This register should be written once finishing Reading from corresponding proc4's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 12. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_3,This register should be written once finishing Reading from corresponding proc3's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 8. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_2,This register should be written once finishing Reading from corresponding proc2's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 4. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_1,This register should be written once finishing Reading from corresponding proc1's mailbox written by ICSSM_PRU" "0,1" newline bitfld.long 0x1C 0. "PRU_ICSS_PRU1_MBOX_READ_DONE_PROC_0,This register should be written once finishing Reading from corresponding proc0's mailbox written by ICSSM_PRU" "0,1" group.long 0x18000++0xB line.long 0x0 "MSS_CTRL_TPCC0_ERRAGG_MASK" bitfld.long 0x0 26. "TPCC0_ERRAGG_MASK_TPTC_A1_READ_ACCESS_ERROR,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 25. "TPCC0_ERRAGG_MASK_TPTC_A0_READ_ACCESS_ERROR,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 24. "TPCC0_ERRAGG_MASK_TPCC_A_READ_ACCESS_ERROR,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "TPCC0_ERRAGG_MASK_TPTC_A1_WRITE_ACCESS_ERROR,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "TPCC0_ERRAGG_MASK_TPTC_A0_WRITE_ACCESS_ERROR,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "TPCC0_ERRAGG_MASK_TPCC_A_WRITE_ACCESS_ERROR,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "TPCC0_ERRAGG_MASK_TPCC_A_PAR_ERR,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "TPCC0_ERRAGG_MASK_TPTC_A1_ERR,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "TPCC0_ERRAGG_MASK_TPTC_A0_ERR,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "TPCC0_ERRAGG_MASK_TPCC_A_MPINT,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "TPCC0_ERRAGG_MASK_TPCC_A_ERRINT,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1'b1 : Error is Masked1'b0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_TPCC0_ERRAGG_STATUS" bitfld.long 0x4 26. "TPCC0_ERRAGG_STATUS_TPTC_A1_READ_ACCESS_ERROR,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 25. "TPCC0_ERRAGG_STATUS_TPTC_A0_READ_ACCESS_ERROR,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 24. "TPCC0_ERRAGG_STATUS_TPCC_A_READ_ACCESS_ERROR,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "TPCC0_ERRAGG_STATUS_TPTC_A1_WRITE_ACCESS_ERROR,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "TPCC0_ERRAGG_STATUS_TPTC_A0_WRITE_ACCESS_ERROR,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "TPCC0_ERRAGG_STATUS_TPCC_A_WRITE_ACCESS_ERROR,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "TPCC0_ERRAGG_STATUS_TPCC_A_PAR_ERR,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "TPCC0_ERRAGG_STATUS_TPTC_A1_ERR,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "TPCC0_ERRAGG_STATUS_TPTC_A0_ERR,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "TPCC0_ERRAGG_STATUS_TPCC_A_MPINT,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "TPCC0_ERRAGG_STATUS_TPCC_A_ERRINT,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in TPCC0_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_TPCC0_ERRAGG_STATUS_RAW" bitfld.long 0x8 26. "TPCC0_ERRAGG_STATUS_RAW_TPTC_A1_READ_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 25. "TPCC0_ERRAGG_STATUS_RAW_TPTC_A0_READ_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 24. "TPCC0_ERRAGG_STATUS_RAW_TPCC_A_READ_ACCESS_ERROR,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "TPCC0_ERRAGG_STATUS_RAW_TPTC_A1_WRITE_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "TPCC0_ERRAGG_STATUS_RAW_TPTC_A0_WRITE_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "TPCC0_ERRAGG_STATUS_RAW_TPCC_A_WRITE_ACCESS_ERROR,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "TPCC0_ERRAGG_STATUS_RAW_TPCC_A_PAR_ERR,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "TPCC0_ERRAGG_STATUS_RAW_TPTC_A1_ERR,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "TPCC0_ERRAGG_STATUS_RAW_TPTC_A0_ERR,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "TPCC0_ERRAGG_STATUS_RAW_TPCC_A_MPINT,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "TPCC0_ERRAGG_STATUS_RAW_TPCC_A_ERRINT,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC0_ERRAGG_MASK" "0,1" group.long 0x18010++0xB line.long 0x0 "MSS_CTRL_MMR_ACCESS_ERRAGG_MASK0" bitfld.long 0x0 11. "MMR_ACCESS_ERRAGG_MASK0_HSM_CTRL_WR,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 10. "MMR_ACCESS_ERRAGG_MASK0_HSM_CTRL_RD,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 9. "MMR_ACCESS_ERRAGG_MASK0_HSM_SOC_CTRL_WR,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 8. "MMR_ACCESS_ERRAGG_MASK0_HSM_SOC_CTRL_RD,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 7. "MMR_ACCESS_ERRAGG_MASK0_TOP_RCM_WR,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 6. "MMR_ACCESS_ERRAGG_MASK0_TOP_RCM_RD,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 5. "MMR_ACCESS_ERRAGG_MASK0_TOP_CTRL_WR,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 4. "MMR_ACCESS_ERRAGG_MASK0_TOP_CTRL_RD,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "MMR_ACCESS_ERRAGG_MASK0_MSS_RCM_WR,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "MMR_ACCESS_ERRAGG_MASK0_MSS_RCM_RD,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "MMR_ACCESS_ERRAGG_MASK0_MSS_CTRL_WR,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "MMR_ACCESS_ERRAGG_MASK0_MSS_CTRL_RD,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MMR_ACCESS_ERRAGG_STATUS0" bitfld.long 0x4 11. "MMR_ACCESS_ERRAGG_STATUS0_HSM_CTRL_WR,Status of Interrupt from HSM_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 10. "MMR_ACCESS_ERRAGG_STATUS0_HSM_CTRL_RD,Status of Interrupt from HSM_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 9. "MMR_ACCESS_ERRAGG_STATUS0_HSM_SOC_CTRL_WR,Status of Interrupt from HSM_SOC_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 8. "MMR_ACCESS_ERRAGG_STATUS0_HSM_SOC_CTRL_RD,Status of Interrupt from HSM_SOC_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 7. "MMR_ACCESS_ERRAGG_STATUS0_TOP_RCM_WR,Status of Interrupt from TOP_RCMSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 6. "MMR_ACCESS_ERRAGG_STATUS0_TOP_RCM_RD,Status of Interrupt from TOP_RCMSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 5. "MMR_ACCESS_ERRAGG_STATUS0_TOP_CTRL_WR,Status of Interrupt from TOP_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 4. "MMR_ACCESS_ERRAGG_STATUS0_TOP_CTRL_RD,Status of Interrupt from TOP_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "MMR_ACCESS_ERRAGG_STATUS0_MSS_RCM_WR,Status of Interrupt from MSS_RCMSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "MMR_ACCESS_ERRAGG_STATUS0_MSS_RCM_RD,Status of Interrupt from MSS_RCMSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "MMR_ACCESS_ERRAGG_STATUS0_MSS_CTRL_WR,Status of Interrupt from MSS_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "MMR_ACCESS_ERRAGG_STATUS0_MSS_CTRL_RD,Status of Interrupt from MSS_CTRLSet only if Interupt is unmasked in MMR_ACCESS_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_MMR_ACCESS_ERRAGG_STATUS_RAW0" bitfld.long 0x8 11. "MMR_ACCESS_ERRAGG_STATUS_RAW0_HSM_CTRL_WR,Raw Status of Interrupt from HSM_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 10. "MMR_ACCESS_ERRAGG_STATUS_RAW0_HSM_CTRL_RD,Raw Status of Interrupt from HSM_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 9. "MMR_ACCESS_ERRAGG_STATUS_RAW0_HSM_SOC_CTRL_WR,Raw Status of Interrupt from HSM_SOC_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 8. "MMR_ACCESS_ERRAGG_STATUS_RAW0_HSM_SOC_CTRL_RD,Raw Status of Interrupt from HSM_SOC_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 7. "MMR_ACCESS_ERRAGG_STATUS_RAW0_TOP_RCM_WR,Raw Status of Interrupt from TOP_RCM. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 6. "MMR_ACCESS_ERRAGG_STATUS_RAW0_TOP_RCM_RD,Raw Status of Interrupt from TOP_RCM. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 5. "MMR_ACCESS_ERRAGG_STATUS_RAW0_TOP_CTRL_WR,Raw Status of Interrupt from TOP_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 4. "MMR_ACCESS_ERRAGG_STATUS_RAW0_TOP_CTRL_RD,Raw Status of Interrupt from TOP_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 3. "MMR_ACCESS_ERRAGG_STATUS_RAW0_MSS_RCM_WR,Raw Status of Interrupt from MSS_RCM. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 2. "MMR_ACCESS_ERRAGG_STATUS_RAW0_MSS_RCM_RD,Raw Status of Interrupt from MSS_RCM. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 1. "MMR_ACCESS_ERRAGG_STATUS_RAW0_MSS_CTRL_WR,Raw Status of Interrupt from MSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" newline bitfld.long 0x8 0. "MMR_ACCESS_ERRAGG_STATUS_RAW0_MSS_CTRL_RD,Raw Status of Interrupt from MSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MMR_ACCESS_ERRAGG_MASK0" "0,1" group.long 0x18080++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE0_ECC_CORR_ERRAGG_MASK" bitfld.long 0x0 6. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 5. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 4. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS0_CPU0_ECC_CORR_ERRAGG_MASK_R5SS0_CPU0_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_ECC_CORR_ERRAGG_STATUS" bitfld.long 0x4 6. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 5. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 4. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU0_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 6. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 5. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 4. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 3. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 2. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x18090++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE0_ECC_UNCORR_ERRAGG_MASK" bitfld.long 0x0 4. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU0_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU0_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU0_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU0_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU0_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_ECC_UNCORR_ERRAGG_STATUS" bitfld.long 0x4 4. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU0_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU0_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU0_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU0_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU0_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 4. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 3. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 2. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 1. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 0. "R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" group.long 0x180A0++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE1_ECC_CORR_ERRAGG_MASK" bitfld.long 0x0 6. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 5. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 4. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS0_CPU1_ECC_CORR_ERRAGG_MASK_R5SS0_CPU1_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_ECC_CORR_ERRAGG_STATUS" bitfld.long 0x4 6. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 5. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 4. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS0_CPU1_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 6. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 5. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 4. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 3. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 2. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x180B0++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE1_ECC_UNCORR_ERRAGG_MASK" bitfld.long 0x0 4. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU1_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU1_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU1_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU1_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS0_CPU1_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_ECC_UNCORR_ERRAGG_STATUS" bitfld.long 0x4 4. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU1_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU1_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU1_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU1_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS0_CPU1_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 4. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 3. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 2. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 1. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 0. "R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU1_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" group.long 0x180C0++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE0_ECC_CORR_ERRAGG_MASK" bitfld.long 0x0 6. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 5. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 4. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS1_CPU0_ECC_CORR_ERRAGG_MASK_R5SS1_CPU0_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_ECC_CORR_ERRAGG_STATUS" bitfld.long 0x4 6. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 5. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 4. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU0_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 6. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 5. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 4. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 3. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 2. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x180D0++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE0_ECC_UNCORR_ERRAGG_MASK" bitfld.long 0x0 4. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU0_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU0_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU0_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU0_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU0_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_ECC_UNCORR_ERRAGG_STATUS" bitfld.long 0x4 4. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU0_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU0_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU0_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU0_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU0_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 4. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 3. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 2. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 1. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 0. "R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU0_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" group.long 0x180E0++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE1_ECC_CORR_ERRAGG_MASK" bitfld.long 0x0 6. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 5. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 4. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS1_CPU1_ECC_CORR_ERRAGG_MASK_R5SS1_CPU1_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_ECC_CORR_ERRAGG_STATUS" bitfld.long 0x4 6. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 5. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 4. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_R5SS1_CPU1_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 6. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 5. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 4. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 3. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 2. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x180F0++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE1_ECC_UNCORR_ERRAGG_MASK" bitfld.long 0x0 4. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU1_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 3. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU1_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 2. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU1_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU1_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_MASK_R5SS1_CPU1_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_ECC_UNCORR_ERRAGG_STATUS" bitfld.long 0x4 4. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU1_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 3. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU1_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 2. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU1_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU1_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_R5SS1_CPU1_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.long 0x8 4. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 3. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 2. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 1. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" newline bitfld.long 0x8 0. "R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS1_CPU1_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this.." "0,1" group.long 0x18100++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE0_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.long 0x0 2. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_MASK_R5SS0_CPU0_B1TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_MASK_R5SS0_CPU0_B0TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_MASK_R5SS0_CPU0_ATCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.long 0x4 2. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS0_CPU0_B1TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS0_CPU0_B0TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS0_CPU0_ATCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.long 0x8 2. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS0_CPU0_B1TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS0_CPU0_B0TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS0_CPU0_ATCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x18110++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE1_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.long 0x0 2. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_MASK_R5SS0_CPU1_B1TCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_MASK_R5SS0_CPU1_B1TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_MASK_R5SS0_CPU1_ATCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.long 0x4 2. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS0_CPU1_B1TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS0_CPU1_B0TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS0_CPU1_ATCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.long 0x8 2. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS0_CPU1_B1TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS0_CPU1_B0TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS0_CPU1_ATCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x18120++0x3 line.long 0x0 "MSS_CTRL_R5SS0_TCM_ADDRPARITY_CLR" bitfld.long 0x0 20.--22. "R5SS0_TCM_ADDRPARITY_CLR_B1TCM1_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "R5SS0_TCM_ADDRPARITY_CLR_B1TCM0_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "R5SS0_TCM_ADDRPARITY_CLR_B0CM1_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "R5SS0_TCM_ADDRPARITY_CLR_B0TCM0_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "R5SS0_TCM_ADDRPARITY_CLR_ATCM1_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS0_TCM_ADDRPARITY_CLR_ATCM0_ERRADDR_CLR,Pulse bit-field Writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" rgroup.long 0x18124++0x17 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_ADDRPARITY_ERR_ATCM" hexmask.long.tbyte 0x0 0.--19. 1. "R5SS0_CORE0_ADDRPARITY_ERR_ATCM_ADDR,Address lathched when parity error is occurred for ATCM of CR5A" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_ADDRPARITY_ERR_ATCM" hexmask.long.tbyte 0x4 0.--19. 1. "R5SS0_CORE1_ADDRPARITY_ERR_ATCM_ADDR,Address lathched when parity error is occurred for ATCM of CR5B" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_ERR_ADDRPARITY_B0TCM" hexmask.long.tbyte 0x8 0.--19. 1. "R5SS0_CORE0_ERR_ADDRPARITY_B0TCM_ADDR,Address lathched when parity error is occurred for B0TCM of CR5A" line.long 0xC "MSS_CTRL_R5SS0_CORE1_ERR_ADDRPARITY_B0TCM" hexmask.long.tbyte 0xC 0.--19. 1. "R5SS0_CORE1_ERR_ADDRPARITY_B0TCM_ADDR,Address lathched when parity error is occurred for B0TCM of CR5B" line.long 0x10 "MSS_CTRL_R5SS0_CORE0_ERR_ADDRPARITY_B1TCM" hexmask.long.tbyte 0x10 0.--19. 1. "R5SS0_CORE0_ERR_ADDRPARITY_B1TCM_ADDR,Address lathched when parity error is occurred for B1TCM of CR5A" line.long 0x14 "MSS_CTRL_R5SS0_CORE1_ERR_ADDRPARITY_B1TCM" hexmask.long.tbyte 0x14 0.--19. 1. "R5SS0_CORE1_ERR_ADDRPARITY_B1TCM_ADDR,Address lathched when parity error is occurred for B1TCM of CR5B" group.long 0x1813C++0xF line.long 0x0 "MSS_CTRL_R5SS0_TCM_ADDRPARITY_ERRFORCE" bitfld.long 0x0 20.--22. "R5SS0_TCM_ADDRPARITY_ERRFORCE_B1TCM1,Write pulse bit field:Writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "R5SS0_TCM_ADDRPARITY_ERRFORCE_B1TCM0,Write pulse bit field:Writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "R5SS0_TCM_ADDRPARITY_ERRFORCE_B0TCM1,Write pulse bit field:Writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "R5SS0_TCM_ADDRPARITY_ERRFORCE_B0TCM0,Write pulse bit field:Writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "R5SS0_TCM_ADDRPARITY_ERRFORCE_ATCM1,Write pulse bit field:Writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS0_TCM_ADDRPARITY_ERRFORCE_ATCM0,Write pulse bit field:Writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.long 0x4 2. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_MASK_R5SS1_CPU0_B1TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x4 1. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_MASK_R5SS1_CPU0_B0TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x4 0. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_MASK_R5SS1_CPU0_ATCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.long 0x8 2. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS1_CPU0_B1TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS1_CPU0_B0TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS1_CPU0_ATCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0xC "MSS_CTRL_R5SS1_CORE0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.long 0xC 2. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS1_CPU0_B1TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0xC 1. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS1_CPU0_B0TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0xC 0. "R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS1_CPU0_ATCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x18150++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE1_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.long 0x0 2. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_MASK_R5SS1_CPU1_B1TCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 1. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_MASK_R5SS1_CPU1_B0TCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" newline bitfld.long 0x0 0. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_MASK_R5SS1_CPU1_ATCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1'b1 : Interrupt is Masked1'b0 : Interrupt is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.long 0x4 2. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS1_CPU1_B1TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 1. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS1_CPU1_B0TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x4 0. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_R5SS1_CPU1_ATCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.long 0x8 2. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS1_CPU1_B1TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 1. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS1_CPU1_B0TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.long 0x8 0. "R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW_R5SS1_CPU1_ATCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.long 0x18160++0x3 line.long 0x0 "MSS_CTRL_R5SS1_TCM_ADDRPARITY_CLR" bitfld.long 0x0 20.--22. "R5SS1_TCM_ADDRPARITY_CLR_B1TCM1_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "R5SS1_TCM_ADDRPARITY_CLR_B1TCM0_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "R5SS1_TCM_ADDRPARITY_CLR_B0CM1_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "R5SS1_TCM_ADDRPARITY_CLR_B0TCM0_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "R5SS1_TCM_ADDRPARITY_CLR_ATCM1_ERRADDR_CLR,Write pulse bit field:Writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS1_TCM_ADDRPARITY_CLR_ATCM0_ERRADDR_CLR,Pulse bit-field Writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" rgroup.long 0x18164++0x17 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_ADDRPARITY_ERR_ATCM" hexmask.long.tbyte 0x0 0.--19. 1. "R5SS1_CORE0_ADDRPARITY_ERR_ATCM_ADDR,Address lathched when parity error is occurred for ATCM of CR5A" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_ADDRPARITY_ERR_ATCM" hexmask.long.tbyte 0x4 0.--19. 1. "R5SS1_CORE1_ADDRPARITY_ERR_ATCM_ADDR,Address lathched when parity error is occurred for ATCM of CR5B" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_ERR_ADDRPARITY_B0TCM" hexmask.long.tbyte 0x8 0.--19. 1. "R5SS1_CORE0_ERR_ADDRPARITY_B0TCM_ADDR,Address lathched when parity error is occurred for B0TCM of CR5A" line.long 0xC "MSS_CTRL_R5SS1_CORE1_ERR_ADDRPARITY_B0TCM" hexmask.long.tbyte 0xC 0.--19. 1. "R5SS1_CORE1_ERR_ADDRPARITY_B0TCM_ADDR,Address lathched when parity error is occurred for B0TCM of CR5B" line.long 0x10 "MSS_CTRL_R5SS1_CORE0_ERR_ADDRPARITY_B1TCM" hexmask.long.tbyte 0x10 0.--19. 1. "R5SS1_CORE0_ERR_ADDRPARITY_B1TCM_ADDR,Address lathched when parity error is occurred for B1TCM of CR5A" line.long 0x14 "MSS_CTRL_R5SS1_CORE1_ERR_ADDRPARITY_B1TCM" hexmask.long.tbyte 0x14 0.--19. 1. "R5SS1_CORE1_ERR_ADDRPARITY_B1TCM_ADDR,Address lathched when parity error is occurred for B1TCM of CR5B" group.long 0x1817C++0x7 line.long 0x0 "MSS_CTRL_R5SS1_TCM_ADDRPARITY_ERRFORCE" bitfld.long 0x0 20.--22. "R5SS1_TCM_ADDRPARITY_ERRFORCE_B1TCM1,Write pulse bit field:Writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "R5SS1_TCM_ADDRPARITY_ERRFORCE_B1TCM0,Write pulse bit field:Writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "R5SS1_TCM_ADDRPARITY_ERRFORCE_B0TCM1,Write pulse bit field:Writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "R5SS1_TCM_ADDRPARITY_ERRFORCE_B0TCM0,Write pulse bit field:Writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "R5SS1_TCM_ADDRPARITY_ERRFORCE_ATCM1,Write pulse bit field:Writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "R5SS1_TCM_ADDRPARITY_ERRFORCE_ATCM0,Write pulse bit field:Writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_TPCC0_PARITY_CTRL" bitfld.long 0x4 16. "TPCC0_PARITY_CTRL_TPCC_A_PARITY_ERR_CLR,Write pulse bit field:parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr" "0,1" newline bitfld.long 0x4 4. "TPCC0_PARITY_CTRL_TPCC_A_PARITY_TESTEN,parity test enable for tpcc a" "0,1" newline bitfld.long 0x4 0. "TPCC0_PARITY_CTRL_TPCC_A_PARITY_EN,Writing 1'b1 enables parity for TPCC_A" "0,1" rgroup.long 0x18184++0x3 line.long 0x0 "MSS_CTRL_TPCC0_PARITY_STATUS" hexmask.long.word 0x0 0.--8. 1. "TPCC0_PARITY_STATUS_TPCC_A_PARITY_ADDR,Address where parity error happened for tpcca" group.long 0x18188++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL" bitfld.long 0x0 16. "TMU_R5SS0_CORE0_ROM_PARITY_CTRL_TMU0_ROM_PARITY_ERR_CLR,Write pulse bit field:parity clear bit. Writing 1'b1 will clear the tmu0_rom_parity_err_addr" "0,1" newline bitfld.long 0x0 1. "TMU_R5SS0_CORE0_ROM_PARITY_CTRL_TMU0_ROM_PARITY_FORCE_ERR,Force parity error on the read interface" "0,1" newline bitfld.long 0x0 0. "TMU_R5SS0_CORE0_ROM_PARITY_CTRL_TMU0_ROM_PARITY_EN,Writing 1'b1 enables parity for TMU0" "0,1" rgroup.long 0x1818C++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS0_CORE0_ROM_PARITY_STATUS" hexmask.long.word 0x0 0.--10. 1. "TMU_R5SS0_CORE0_ROM_PARITY_STATUS_TMU0_ROM_PARITY_ERR_ADDR,Address where parity error happened for tmu0" group.long 0x18190++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL" bitfld.long 0x0 16. "TMU_R5SS0_CORE1_ROM_PARITY_CTRL_TMU1_ROM_PARITY_ERR_CLR,Write pulse bit field:parity clear bit. Writing 1'b1 will clear the tmu1_rom_parity_err_addr" "0,1" newline bitfld.long 0x0 1. "TMU_R5SS0_CORE1_ROM_PARITY_CTRL_TMU1_ROM_PARITY_FORCE_ERR,Force parity error on the read interface" "0,1" newline bitfld.long 0x0 0. "TMU_R5SS0_CORE1_ROM_PARITY_CTRL_TMU1_ROM_PARITY_EN,Writing 1'b1 enables parity for TMU1" "0,1" rgroup.long 0x18194++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS0_CORE1_ROM_PARITY_STATUS" hexmask.long.word 0x0 0.--10. 1. "TMU_R5SS0_CORE1_ROM_PARITY_STATUS_TMU1_ROM_PARITY_ERR_ADDR,Address where parity error happened for tmu1" group.long 0x18198++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS1_CORE0_ROM_PARITY_CTRL" bitfld.long 0x0 16. "TMU_R5SS1_CORE0_ROM_PARITY_CTRL_TMU0_ROM_PARITY_ERR_CLR,Write pulse bit field:parity clear bit. Writing 1'b1 will clear the tmu0_rom_parity_err_addr" "0,1" newline bitfld.long 0x0 1. "TMU_R5SS1_CORE0_ROM_PARITY_CTRL_TMU0_ROM_PARITY_FORCE_ERR,Force parity error on the read interface" "0,1" newline bitfld.long 0x0 0. "TMU_R5SS1_CORE0_ROM_PARITY_CTRL_TMU0_ROM_PARITY_EN,Writing 1'b1 enables parity for TMU0" "0,1" rgroup.long 0x1819C++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS1_CORE0_ROM_PARITY_STATUS" hexmask.long.word 0x0 0.--10. 1. "TMU_R5SS1_CORE0_ROM_PARITY_STATUS_TMU0_ROM_PARITY_ERR_ADDR,Address where parity error happened for tmu0" group.long 0x181A0++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS1_CORE1_ROM_PARITY_CTRL" bitfld.long 0x0 16. "TMU_R5SS1_CORE1_ROM_PARITY_CTRL_TMU1_ROM_PARITY_ERR_CLR,Write pulse bit field:parity clear bit. Writing 1'b1 will clear the tmu1_rom_parity_err_addr" "0,1" newline bitfld.long 0x0 1. "TMU_R5SS1_CORE1_ROM_PARITY_CTRL_TMU1_ROM_PARITY_FORCE_ERR,Force parity error on the read interface" "0,1" newline bitfld.long 0x0 0. "TMU_R5SS1_CORE1_ROM_PARITY_CTRL_TMU1_ROM_PARITY_EN,Writing 1'b1 enables parity for TMU1" "0,1" rgroup.long 0x181A4++0x3 line.long 0x0 "MSS_CTRL_TMU_R5SS1_CORE1_ROM_PARITY_STATUS" hexmask.long.word 0x0 0.--10. 1. "TMU_R5SS1_CORE1_ROM_PARITY_STATUS_TMU1_ROM_PARITY_ERR_ADDR,Address where parity error happened for tmu1" group.long 0x184A0++0x7 line.long 0x0 "MSS_CTRL_OSPI0_BUS_SAFETY_CTRL" hexmask.long.byte 0x0 16.--23. 1. "OSPI0_BUS_SAFETY_CTRL_TYPE,This bitfield gives a top level idea of the available bus [cmd wr ws rd] for the particular Target/Initiator and whether it follows the VBUS protocol or not. Bit 0 - 1'b1 indicates the Command bus is implemented to this.." newline bitfld.long 0x0 8. "OSPI0_BUS_SAFETY_CTRL_ERR_CLEAR,Set this bit to 1'b1 to clear the error status for this port" "0,1" newline bitfld.long 0x0 0.--2. "OSPI0_BUS_SAFETY_CTRL_ENABLE,Set this bit to 3'b111 to enable the safety configuration for this port. Set this bit to 3'b000 to disable the safety configuration for this port." "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_OSPI0_BUS_SAFETY_FI" hexmask.long.byte 0x4 24.--31. 1. "OSPI0_BUS_SAFETY_FI_SAFE,This bitfield is used to inject fault on Read write command and request bus on the safe Interconnect. Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2 - Set.." newline hexmask.long.byte 0x4 16.--23. 1. "OSPI0_BUS_SAFETY_FI_MAIN,This bitfield is used to inject fault on Read write command and request bus on the main Interconnect.Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2 - Set.." newline hexmask.long.byte 0x4 8.--15. 1. "OSPI0_BUS_SAFETY_FI_DATA,Set bit 0 to 1'b1 to inject sec and ded faults on [31:0] bits of data bus.Set bit 1 to 1'b1 to inject sec and ded faults on [64:32] bits of data bus." newline bitfld.long 0x4 5. "OSPI0_BUS_SAFETY_FI_DED,Set this bit to 1'b1 inject ded error on data at this port" "0,1" newline bitfld.long 0x4 4. "OSPI0_BUS_SAFETY_FI_SEC,Set this bit to 1'b1 to inject sec error on data at this port" "0,1" newline bitfld.long 0x4 3. "OSPI0_BUS_SAFETY_FI_GLOBAL_SAFE_REQ,Set this bit 1'b1 to inject fault for request signals on Safe Interconnect." "0,1" newline bitfld.long 0x4 2. "OSPI0_BUS_SAFETY_FI_GLOBAL_MAIN_REQ,Set this bit to 1'b1 to inject fault for request signals on main Interconnect." "0,1" newline bitfld.long 0x4 1. "OSPI0_BUS_SAFETY_FI_GLOBAL_SAFE,This is a global safe Fault injection signal. Set this bit to inject fault on all the safety buses of the safe interconnect except req signal. Writing a 1'b1 injects fault on interconnect." "0,1" newline bitfld.long 0x4 0. "OSPI0_BUS_SAFETY_FI_GLOBAL_MAIN,This is a global main Fault injection signal. Set this bit to inject fault on all the buses of the main interconnect except req signal. Writing a 1'b1 injects fault on interconnect." "0,1" rgroup.long 0x184A8++0x17 line.long 0x0 "MSS_CTRL_OSPI0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "OSPI0_BUS_SAFETY_ERR_DED,This flag signals detection of dual error in Data at this port.Flag is generted for 32 bit segment of Data BusBit 0 - 1'b1 indicates ded on [31:0] bit of Data busBit 1 - 1'b1 indicates ded on [63:32] bit of Data busBit [7:2] -.." newline hexmask.long.byte 0x0 16.--23. 1. "OSPI0_BUS_SAFETY_ERR_SEC,This flag signals detection of single error in Data at this port. Flag is generted for 32 bit segment of Data BusBit 0 - 1'b1 indicates sec on [31:0] bit of Data busBit 1 - 1'b1 indicates sec on [63:32] bit of Data busBit [7:2] -.." newline hexmask.long.byte 0x0 8.--15. 1. "OSPI0_BUS_SAFETY_ERR_COMP_CHECK,This is used to verify the proper functioning of fault Injection on all the buses.1'b1 indicates error in the corresponding Bus has been injected successfully. Bit 0 - This is a Bitwise AND of error compares of all command.." newline hexmask.long.byte 0x0 0.--7. 1. "OSPI0_BUS_SAFETY_ERR_COMP_ERR,1'b1 indicates error in the corresponding Bus whenever a fault is detected at any bus signalBit 0 - This is a Bitwise OR of error compares of all command bus signals.Bit 1 - This is a Bitwise OR of error compares of all.." line.long 0x4 "MSS_CTRL_OSPI0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.long.byte 0x4 8.--15. 1. "OSPI0_BUS_SAFETY_ERR_STAT_DATA0_D1,Read this bitfield for Comparator status for Higher 32 bits [63:32] of data bus at this port. It represent the position of the flipped bit in case of SEC." newline hexmask.long.byte 0x4 0.--7. 1. "OSPI0_BUS_SAFETY_ERR_STAT_DATA0_D0,Read this bitfield for Comparator status for lower 32 bits [31:0] of data bus at this port. It represent the position of the flipped bit in case of SEC." line.long 0x8 "MSS_CTRL_OSPI0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x8 0.--31. 1. "OSPI0_BUS_SAFETY_ERR_STAT_CMD_STAT,Read this bitfield for comparator status for command bus for this port. 1'b1 on any of the bits indicates an error on Command Bus" line.long 0xC "MSS_CTRL_OSPI0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0xC 0.--31. 1. "OSPI0_BUS_SAFETY_ERR_STAT_WRITE_STAT,Read this bitfield for comparator status for Write bus for this port. 1'b1 at any bit indicates error on Write Bus" line.long 0x10 "MSS_CTRL_OSPI0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x10 0.--31. 1. "OSPI0_BUS_SAFETY_ERR_STAT_READ_STAT,Read this bitfield for comapartor status for read signals at this port. 1'b1 on any of the bits indicates an error on Read bus." line.long 0x14 "MSS_CTRL_OSPI0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x14 0.--31. 1. "OSPI0_BUS_SAFETY_ERR_STAT_WRITERESP_STAT,Read this bitfield for comparator status for Write response bus for this port. 1'b1 indicates error on Write Rsponse Bus." group.long 0x18880++0x7 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_CTRL" hexmask.long.byte 0x0 16.--23. 1. "L2OCRAM_BANK4_BUS_SAFETY_CTRL_TYPE,This bitfield gives a top level idea of the available bus [cmd wr ws rd] for the particular Target/Initiator and whether it follows the VBUS protocol or not. Bit 0 - 1'b1 indicates the Command bus is implemented to this.." newline bitfld.long 0x0 8. "L2OCRAM_BANK4_BUS_SAFETY_CTRL_ERR_CLEAR,Set this bit to 1'b1 to clear the error status for this port" "0,1" newline bitfld.long 0x0 0.--2. "L2OCRAM_BANK4_BUS_SAFETY_CTRL_ENABLE,Set this bit to 3'b111 to enable the safety configuration for this port. Set this bit to 3'b000 to disable the safety configuration for this port." "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_FI" hexmask.long.byte 0x4 24.--31. 1. "L2OCRAM_BANK4_BUS_SAFETY_FI_SAFE,This bitfield is used to inject fault on Read write command and request bus on the safe Interconnect. Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2.." newline hexmask.long.byte 0x4 16.--23. 1. "L2OCRAM_BANK4_BUS_SAFETY_FI_MAIN,This bitfield is used to inject fault on Read write command and request bus on the main Interconnect.Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2 -.." newline hexmask.long.byte 0x4 8.--15. 1. "L2OCRAM_BANK4_BUS_SAFETY_FI_DATA,Set bit 0 to 1'b1 to inject sec and ded faults on [31:0] bits of data bus.Set bit 1 to 1'b1 to inject sec and ded faults on [64:32] bits of data bus." newline bitfld.long 0x4 5. "L2OCRAM_BANK4_BUS_SAFETY_FI_DED,Set this bit to 1'b1 inject ded error on data at this port" "0,1" newline bitfld.long 0x4 4. "L2OCRAM_BANK4_BUS_SAFETY_FI_SEC,Set this bit to 1'b1 to inject sec error on data at this port" "0,1" newline bitfld.long 0x4 3. "L2OCRAM_BANK4_BUS_SAFETY_FI_GLOBAL_SAFE_REQ,Set this bit 1'b1 to inject fault for request signals on Safe Interconnect." "0,1" newline bitfld.long 0x4 2. "L2OCRAM_BANK4_BUS_SAFETY_FI_GLOBAL_MAIN_REQ,Set this bit to 1'b1 to inject fault for request signals on main Interconnect." "0,1" newline bitfld.long 0x4 1. "L2OCRAM_BANK4_BUS_SAFETY_FI_GLOBAL_SAFE,This is a global safe Fault injection signal. Set this bit to inject fault on all the safety buses of the safe interconnect except req signal. Writing a 1'b1 injects fault on interconnect." "0,1" newline bitfld.long 0x4 0. "L2OCRAM_BANK4_BUS_SAFETY_FI_GLOBAL_MAIN,This is a global main Fault injection signal. Set this bit to inject fault on all the buses of the main interconnect except req signal. Writing a 1'b1 injects fault on interconnect." "0,1" rgroup.long 0x18888++0x17 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_DED,This flag signals detection of dual error in Data at this port.Flag is generted for 32 bit segment of Data BusBit 0 - 1'b1 indicates ded on [31:0] bit of Data busBit 1 - 1'b1 indicates ded on [63:32] bit of Data busBit.." newline hexmask.long.byte 0x0 16.--23. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_SEC,This flag signals detection of single error in Data at this port. Flag is generted for 32 bit segment of Data BusBit 0 - 1'b1 indicates sec on [31:0] bit of Data busBit 1 - 1'b1 indicates sec on [63:32] bit of Data busBit.." newline hexmask.long.byte 0x0 8.--15. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_COMP_CHECK,This is used to verify the proper functioning of fault Injection on all the buses.1'b1 indicates error in the corresponding Bus has been injected successfully. Bit 0 - This is a Bitwise AND of error compares of all.." newline hexmask.long.byte 0x0 0.--7. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_COMP_ERR,1'b1 indicates error in the corresponding Bus whenever a fault is detected at any bus signalBit 0 - This is a Bitwise OR of error compares of all command bus signals.Bit 1 - This is a Bitwise OR of error compares of.." line.long 0x4 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_DATA0" hexmask.long.byte 0x4 8.--15. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_DATA0_D1,Read this bitfield for Comparator status for Higher 32 bits [63:32] of data bus at this port. It represent the position of the flipped bit in case of SEC." newline hexmask.long.byte 0x4 0.--7. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_DATA0_D0,Read this bitfield for Comparator status for lower 32 bits [31:0] of data bus at this port. It represent the position of the flipped bit in case of SEC." line.long 0x8 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x8 0.--31. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_CMD_STAT,Read this bitfield for comparator status for command bus for this port. 1'b1 on any of the bits indicates an error on Command Bus" line.long 0xC "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0xC 0.--31. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_WRITE_STAT,Read this bitfield for comparator status for Write bus for this port. 1'b1 at any bit indicates error on Write Bus" line.long 0x10 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x10 0.--31. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_READ_STAT,Read this bitfield for comapartor status for read signals at this port. 1'b1 on any of the bits indicates an error on Read bus." line.long 0x14 "MSS_CTRL_L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x14 0.--31. 1. "L2OCRAM_BANK4_BUS_SAFETY_ERR_STAT_WRITERESP_STAT,Read this bitfield for comparator status for Write response bus for this port. 1'b1 indicates error on Write Rsponse Bus." group.long 0x188A0++0x7 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_CTRL" hexmask.long.byte 0x0 16.--23. 1. "L2OCRAM_BANK5_BUS_SAFETY_CTRL_TYPE,This bitfield gives a top level idea of the available bus [cmd wr ws rd] for the particular Target/Initiator and whether it follows the VBUS protocol or not. Bit 0 - 1'b1 indicates the Command bus is implemented to this.." newline bitfld.long 0x0 8. "L2OCRAM_BANK5_BUS_SAFETY_CTRL_ERR_CLEAR,Set this bit to 1'b1 to clear the error status for this port" "0,1" newline bitfld.long 0x0 0.--2. "L2OCRAM_BANK5_BUS_SAFETY_CTRL_ENABLE,Set this bit to 3'b111 to enable the safety configuration for this port. Set this bit to 3'b000 to disable the safety configuration for this port." "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_FI" hexmask.long.byte 0x4 24.--31. 1. "L2OCRAM_BANK5_BUS_SAFETY_FI_SAFE,This bitfield is used to inject fault on Read write command and request bus on the safe Interconnect. Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2.." newline hexmask.long.byte 0x4 16.--23. 1. "L2OCRAM_BANK5_BUS_SAFETY_FI_MAIN,This bitfield is used to inject fault on Read write command and request bus on the main Interconnect.Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2 -.." newline hexmask.long.byte 0x4 8.--15. 1. "L2OCRAM_BANK5_BUS_SAFETY_FI_DATA,Set bit 0 to 1'b1 to inject sec and ded faults on [31:0] bits of data bus.Set bit 1 to 1'b1 to inject sec and ded faults on [64:32] bits of data bus." newline bitfld.long 0x4 5. "L2OCRAM_BANK5_BUS_SAFETY_FI_DED,Set this bit to 1'b1 inject ded error on data at this port" "0,1" newline bitfld.long 0x4 4. "L2OCRAM_BANK5_BUS_SAFETY_FI_SEC,Set this bit to 1'b1 to inject sec error on data at this port" "0,1" newline bitfld.long 0x4 3. "L2OCRAM_BANK5_BUS_SAFETY_FI_GLOBAL_SAFE_REQ,Set this bit 1'b1 to inject fault for request signals on Safe Interconnect." "0,1" newline bitfld.long 0x4 2. "L2OCRAM_BANK5_BUS_SAFETY_FI_GLOBAL_MAIN_REQ,Set this bit to 1'b1 to inject fault for request signals on main Interconnect." "0,1" newline bitfld.long 0x4 1. "L2OCRAM_BANK5_BUS_SAFETY_FI_GLOBAL_SAFE,This is a global safe Fault injection signal. Set this bit to inject fault on all the safety buses of the safe interconnect except req signal. Writing a 1'b1 injects fault on interconnect." "0,1" newline bitfld.long 0x4 0. "L2OCRAM_BANK5_BUS_SAFETY_FI_GLOBAL_MAIN,This is a global main Fault injection signal. Set this bit to inject fault on all the buses of the main interconnect except req signal. Writing a 1'b1 injects fault on interconnect." "0,1" rgroup.long 0x188A8++0x17 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_DED,This flag signals detection of dual error in Data at this port.Flag is generted for 32 bit segment of Data BusBit 0 - 1'b1 indicates ded on [31:0] bit of Data busBit 1 - 1'b1 indicates ded on [63:32] bit of Data busBit.." newline hexmask.long.byte 0x0 16.--23. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_SEC,This flag signals detection of single error in Data at this port. Flag is generted for 32 bit segment of Data BusBit 0 - 1'b1 indicates sec on [31:0] bit of Data busBit 1 - 1'b1 indicates sec on [63:32] bit of Data busBit.." newline hexmask.long.byte 0x0 8.--15. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_COMP_CHECK,This is used to verify the proper functioning of fault Injection on all the buses.1'b1 indicates error in the corresponding Bus has been injected successfully. Bit 0 - This is a Bitwise AND of error compares of all.." newline hexmask.long.byte 0x0 0.--7. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_COMP_ERR,1'b1 indicates error in the corresponding Bus whenever a fault is detected at any bus signalBit 0 - This is a Bitwise OR of error compares of all command bus signals.Bit 1 - This is a Bitwise OR of error compares of.." line.long 0x4 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_DATA0" hexmask.long.byte 0x4 8.--15. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_DATA0_D1,Read this bitfield for Comparator status for Higher 32 bits [63:32] of data bus at this port. It represent the position of the flipped bit in case of SEC." newline hexmask.long.byte 0x4 0.--7. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_DATA0_D0,Read this bitfield for Comparator status for lower 32 bits [31:0] of data bus at this port. It represent the position of the flipped bit in case of SEC." line.long 0x8 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x8 0.--31. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_CMD_STAT,Read this bitfield for comparator status for command bus for this port. 1'b1 on any of the bits indicates an error on Command Bus" line.long 0xC "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0xC 0.--31. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_WRITE_STAT,Read this bitfield for comparator status for Write bus for this port. 1'b1 at any bit indicates error on Write Bus" line.long 0x10 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x10 0.--31. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_READ_STAT,Read this bitfield for comapartor status for read signals at this port. 1'b1 on any of the bits indicates an error on Read bus." line.long 0x14 "MSS_CTRL_L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x14 0.--31. 1. "L2OCRAM_BANK5_BUS_SAFETY_ERR_STAT_WRITERESP_STAT,Read this bitfield for comparator status for Write response bus for this port. 1'b1 indicates error on Write Rsponse Bus." tree.end tree "MSS_IOMUX" base ad:0x53100000 group.long 0x0++0x29F line.long 0x0 "IOMUX_QSPI0_CSN0_CFG_REG,QSPI0_CSn0 IO config register." bitfld.long 0x0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x4 "IOMUX_QSPI0_CSN1_CFG_REG,QSPI0_CSn1 IO config register." bitfld.long 0x4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x8 "IOMUX_QSPI0_CLK_CFG_REG,QSPI0_CLK IO config register." bitfld.long 0x8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC "IOMUX_QSPI0_D0_CFG_REG,QSPI0_D0 IO config register." bitfld.long 0xC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x10 "IOMUX_QSPI0_D1_CFG_REG,QSPI0_D1 IO config register." bitfld.long 0x10 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x10 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x10 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x10 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x10 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x10 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x10 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x10 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x10 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x10 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x10 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x10 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x10 0.--3. 1. "FUNC_SEL,Function select" line.long 0x14 "IOMUX_QSPI0_D2_CFG_REG,QSPI0_D2 IO config register." bitfld.long 0x14 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x14 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x14 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x14 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x14 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x14 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x14 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x14 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x14 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x14 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x14 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x14 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x14 0.--3. 1. "FUNC_SEL,Function select" line.long 0x18 "IOMUX_QSPI0_D3_CFG_REG,QSPI0_D3 IO config register." bitfld.long 0x18 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x18 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x18 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x18 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x18 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x18 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x18 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x18 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x18 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x18 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x18 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x18 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x18 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C "IOMUX_MCAN0_RX_CFG_REG,MCAN0_RX IO config register." bitfld.long 0x1C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x20 "IOMUX_MCAN0_TX_CFG_REG,MCAN0_TX IO config register." bitfld.long 0x20 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x20 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x20 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x20 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x20 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x20 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x20 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x20 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x20 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x20 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x20 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x20 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x20 0.--3. 1. "FUNC_SEL,Function select" line.long 0x24 "IOMUX_MCAN1_RX_CFG_REG,MCAN1_RX IO config register." bitfld.long 0x24 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x24 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x24 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x24 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x24 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x24 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x24 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x24 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x24 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x24 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x24 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x24 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x24 0.--3. 1. "FUNC_SEL,Function select" line.long 0x28 "IOMUX_MCAN1_TX_CFG_REG,MCAN1_TX IO config register." bitfld.long 0x28 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x28 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x28 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x28 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x28 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x28 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x28 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x28 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x28 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x28 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x28 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x28 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x28 0.--3. 1. "FUNC_SEL,Function select" line.long 0x2C "IOMUX_SPI0_CS0_CFG_REG,SPI0_CS0 IO config register." bitfld.long 0x2C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x2C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x2C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x2C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x2C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x2C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x2C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x2C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x2C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x2C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x2C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x2C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x2C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x30 "IOMUX_SPI0_CLK_CFG_REG,SPI0_CLK IO config register." bitfld.long 0x30 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x30 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x30 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x30 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x30 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x30 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x30 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x30 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x30 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x30 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x30 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x30 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x30 0.--3. 1. "FUNC_SEL,Function select" line.long 0x34 "IOMUX_SPI0_D0_CFG_REG,SPI0_D0 IO config register." bitfld.long 0x34 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x34 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x34 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x34 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x34 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x34 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x34 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x34 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x34 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x34 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x34 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x34 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x34 0.--3. 1. "FUNC_SEL,Function select" line.long 0x38 "IOMUX_SPI0_D1_CFG_REG,SPI0_D1 IO config register." bitfld.long 0x38 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x38 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x38 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x38 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x38 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x38 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x38 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x38 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x38 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x38 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x38 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x38 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x38 0.--3. 1. "FUNC_SEL,Function select" line.long 0x3C "IOMUX_SPI1_CS0_CFG_REG,SPI1_CS0 IO config register." bitfld.long 0x3C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x3C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x3C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x3C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x3C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x3C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x3C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x3C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x3C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x3C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x3C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x3C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x3C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x40 "IOMUX_SPI1_CLK_CFG_REG,SPI1_CLK IO config register." bitfld.long 0x40 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x40 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x40 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x40 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x40 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x40 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x40 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x40 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x40 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x40 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x40 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x40 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x40 0.--3. 1. "FUNC_SEL,Function select" line.long 0x44 "IOMUX_SPI1_D0_CFG_REG,SPI1_D0 IO config register." bitfld.long 0x44 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x44 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x44 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x44 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x44 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x44 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x44 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x44 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x44 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x44 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x44 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x44 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x44 0.--3. 1. "FUNC_SEL,Function select" line.long 0x48 "IOMUX_SPI1_D1_CFG_REG,SPI1_D1 IO config register." bitfld.long 0x48 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x48 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x48 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x48 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x48 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x48 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x48 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x48 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x48 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x48 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x48 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x48 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x48 0.--3. 1. "FUNC_SEL,Function select" line.long 0x4C "IOMUX_LIN1_RXD_CFG_REG,LIN1_RXD IO config register." bitfld.long 0x4C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x4C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x4C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x4C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x4C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x4C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x4C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x4C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x4C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x4C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x4C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x4C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x4C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x50 "IOMUX_LIN1_TXD_CFG_REG,LIN1_TXD IO config register." bitfld.long 0x50 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x50 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x50 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x50 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x50 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x50 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x50 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x50 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x50 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x50 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x50 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x50 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x50 0.--3. 1. "FUNC_SEL,Function select" line.long 0x54 "IOMUX_LIN2_RXD_CFG_REG,LIN2_RXD IO config register." bitfld.long 0x54 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x54 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x54 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x54 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x54 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x54 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x54 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x54 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x54 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x54 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x54 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x54 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x54 0.--3. 1. "FUNC_SEL,Function select" line.long 0x58 "IOMUX_LIN2_TXD_CFG_REG,LIN2_TXD IO config register." bitfld.long 0x58 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x58 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x58 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x58 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x58 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x58 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x58 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x58 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x58 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x58 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x58 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x58 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x58 0.--3. 1. "FUNC_SEL,Function select" line.long 0x5C "IOMUX_I2C1_SCL_CFG_REG,I2C1_SCL IO config register." bitfld.long 0x5C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x5C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x5C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x5C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x5C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x5C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x5C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x5C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x5C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x5C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x5C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x5C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x5C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x60 "IOMUX_I2C1_SDA_CFG_REG,I2C1_SDA IO config register." bitfld.long 0x60 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x60 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x60 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x60 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x60 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x60 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x60 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x60 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x60 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x60 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x60 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x60 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x60 0.--3. 1. "FUNC_SEL,Function select" line.long 0x64 "IOMUX_UART0_RTSN_CFG_REG,UART0_RTSn IO config register." bitfld.long 0x64 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x64 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x64 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x64 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x64 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x64 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x64 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x64 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x64 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x64 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x64 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x64 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x64 0.--3. 1. "FUNC_SEL,Function select" line.long 0x68 "IOMUX_UART0_CTSN_CFG_REG,UART0_CTSn IO config register." bitfld.long 0x68 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x68 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x68 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x68 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x68 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x68 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x68 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x68 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x68 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x68 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x68 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x68 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x68 0.--3. 1. "FUNC_SEL,Function select" line.long 0x6C "IOMUX_UART0_RXD_CFG_REG,UART0_RXD IO config register." bitfld.long 0x6C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x6C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x6C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x6C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x6C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x6C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x6C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x6C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x6C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x6C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x6C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x6C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x6C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x70 "IOMUX_UART0_TXD_CFG_REG,UART0_TXD IO config register." bitfld.long 0x70 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x70 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x70 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x70 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x70 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x70 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x70 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x70 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x70 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x70 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x70 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x70 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x70 0.--3. 1. "FUNC_SEL,Function select" line.long 0x74 "IOMUX_RGMII1_RXC_CFG_REG,RGMII1_RXC IO config register." bitfld.long 0x74 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x74 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x74 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x74 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x74 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x74 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x74 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x74 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x74 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x74 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x74 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x74 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x74 0.--3. 1. "FUNC_SEL,Function select" line.long 0x78 "IOMUX_RGMII1_RX_CTL_CFG_REG,RGMII1_RX_CTL IO config register." bitfld.long 0x78 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x78 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x78 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x78 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x78 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x78 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x78 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x78 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x78 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x78 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x78 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x78 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x78 0.--3. 1. "FUNC_SEL,Function select" line.long 0x7C "IOMUX_RGMII1_RD0_CFG_REG,RGMII1_RD0 IO config register." bitfld.long 0x7C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x7C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x7C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x7C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x7C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x7C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x7C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x7C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x7C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x7C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x7C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x7C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x7C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x80 "IOMUX_RGMII1_RD1_CFG_REG,RGMII1_RD1 IO config register." bitfld.long 0x80 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x80 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x80 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x80 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x80 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x80 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x80 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x80 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x80 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x80 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x80 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x80 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x80 0.--3. 1. "FUNC_SEL,Function select" line.long 0x84 "IOMUX_RGMII1_RD2_CFG_REG,RGMII1_RD2 IO config register." bitfld.long 0x84 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x84 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x84 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x84 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x84 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x84 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x84 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x84 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x84 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x84 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x84 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x84 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x84 0.--3. 1. "FUNC_SEL,Function select" line.long 0x88 "IOMUX_RGMII1_RD3_CFG_REG,RGMII1_RD3 IO config register." bitfld.long 0x88 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x88 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x88 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x88 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x88 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x88 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x88 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x88 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x88 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x88 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x88 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x88 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x88 0.--3. 1. "FUNC_SEL,Function select" line.long 0x8C "IOMUX_RGMII1_TXC_CFG_REG,RGMII1_TXC IO config register." bitfld.long 0x8C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x8C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x8C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x8C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x8C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x8C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x8C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x8C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x8C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x8C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x8C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x8C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x8C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x90 "IOMUX_RGMII1_TX_CTL_CFG_REG,RGMII1_TX_CTL IO config register." bitfld.long 0x90 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x90 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x90 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x90 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x90 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x90 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x90 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x90 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x90 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x90 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x90 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x90 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x90 0.--3. 1. "FUNC_SEL,Function select" line.long 0x94 "IOMUX_RGMII1_TD0_CFG_REG,RGMII1_TD0 IO config register." bitfld.long 0x94 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x94 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x94 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x94 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x94 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x94 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x94 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x94 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x94 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x94 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x94 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x94 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x94 0.--3. 1. "FUNC_SEL,Function select" line.long 0x98 "IOMUX_RGMII1_TD1_CFG_REG,RGMII1_TD1 IO config register." bitfld.long 0x98 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x98 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x98 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x98 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x98 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x98 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x98 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x98 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x98 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x98 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x98 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x98 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x98 0.--3. 1. "FUNC_SEL,Function select" line.long 0x9C "IOMUX_RGMII1_TD2_CFG_REG,RGMII1_TD2 IO config register." bitfld.long 0x9C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x9C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x9C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x9C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x9C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x9C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x9C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x9C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x9C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x9C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x9C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x9C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x9C 0.--3. 1. "FUNC_SEL,Function select" line.long 0xA0 "IOMUX_RGMII1_TD3_CFG_REG,RGMII1_TD3 IO config register." bitfld.long 0xA0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xA0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xA0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xA0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xA0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xA0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xA0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xA0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xA0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xA0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xA0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xA0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xA0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xA4 "IOMUX_MDIO0_MDIO_CFG_REG,MDIO0_MDIO IO config register." bitfld.long 0xA4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xA4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xA4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xA4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xA4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xA4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xA4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xA4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xA4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xA4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xA4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xA4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xA4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xA8 "IOMUX_MDIO0_MDC_CFG_REG,MDIO0_MDC IO config register." bitfld.long 0xA8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xA8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xA8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xA8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xA8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xA8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xA8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xA8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xA8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xA8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xA8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xA8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xA8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xAC "IOMUX_EPWM0_A_CFG_REG,EPWM0_A IO config register." bitfld.long 0xAC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xAC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xAC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xAC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xAC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xAC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xAC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xAC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xAC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xAC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xAC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xAC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xAC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xB0 "IOMUX_EPWM0_B_CFG_REG,EPWM0_B IO config register." bitfld.long 0xB0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xB0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xB0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xB0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xB0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xB0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xB0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xB0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xB0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xB0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xB0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xB0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xB0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xB4 "IOMUX_EPWM1_A_CFG_REG,EPWM1_A IO config register." bitfld.long 0xB4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xB4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xB4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xB4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xB4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xB4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xB4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xB4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xB4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xB4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xB4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xB4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xB4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xB8 "IOMUX_EPWM1_B_CFG_REG,EPWM1_B IO config register." bitfld.long 0xB8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xB8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xB8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xB8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xB8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xB8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xB8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xB8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xB8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xB8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xB8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xB8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xB8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xBC "IOMUX_EPWM2_A_CFG_REG,EPWM2_A IO config register." bitfld.long 0xBC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xBC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xBC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xBC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xBC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xBC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xBC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xBC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xBC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xBC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xBC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xBC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xBC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC0 "IOMUX_EPWM2_B_CFG_REG,EPWM2_B IO config register." bitfld.long 0xC0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xC0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xC0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xC0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xC0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xC0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xC0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xC0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xC0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xC0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC4 "IOMUX_EPWM3_A_CFG_REG,EPWM3_A IO config register." bitfld.long 0xC4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xC4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xC4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xC4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xC4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xC4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xC4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xC4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xC4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xC4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC8 "IOMUX_EPWM3_B_CFG_REG,EPWM3_B IO config register." bitfld.long 0xC8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xC8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xC8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xC8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xC8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xC8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xC8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xC8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xC8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xC8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xCC "IOMUX_EPWM4_A_CFG_REG,EPWM4_A IO config register." bitfld.long 0xCC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xCC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xCC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xCC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xCC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xCC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xCC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xCC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xCC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xCC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xCC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xCC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xCC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xD0 "IOMUX_EPWM4_B_CFG_REG,EPWM4_B IO config register." bitfld.long 0xD0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xD0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xD0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xD0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xD0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xD0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xD0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xD0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xD0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xD0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xD0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xD0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xD0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xD4 "IOMUX_EPWM5_A_CFG_REG,EPWM5_A IO config register." bitfld.long 0xD4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xD4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xD4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xD4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xD4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xD4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xD4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xD4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xD4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xD4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xD4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xD4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xD4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xD8 "IOMUX_EPWM5_B_CFG_REG,EPWM5_B IO config register." bitfld.long 0xD8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xD8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xD8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xD8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xD8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xD8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xD8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xD8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xD8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xD8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xD8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xD8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xD8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xDC "IOMUX_EPWM6_A_CFG_REG,EPWM6_A IO config register." bitfld.long 0xDC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xDC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xDC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xDC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xDC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xDC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xDC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xDC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xDC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xDC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xDC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xDC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xDC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xE0 "IOMUX_EPWM6_B_CFG_REG,EPWM6_B IO config register." bitfld.long 0xE0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xE0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xE0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xE0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xE0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xE0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xE0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xE0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xE0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xE0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xE0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xE0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xE0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xE4 "IOMUX_EPWM7_A_CFG_REG,EPWM7_A IO config register." bitfld.long 0xE4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xE4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xE4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xE4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xE4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xE4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xE4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xE4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xE4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xE4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xE4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xE4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xE4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xE8 "IOMUX_EPWM7_B_CFG_REG,EPWM7_B IO config register." bitfld.long 0xE8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xE8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xE8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xE8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xE8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xE8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xE8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xE8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xE8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xE8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xE8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xE8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xE8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xEC "IOMUX_EPWM8_A_CFG_REG,EPWM8_A IO config register." bitfld.long 0xEC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xEC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xEC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xEC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xEC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xEC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xEC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xEC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xEC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xEC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xEC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xEC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xEC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xF0 "IOMUX_EPWM8_B_CFG_REG,EPWM8_B IO config register." bitfld.long 0xF0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xF0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xF0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xF0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xF0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xF0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xF0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xF0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xF0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xF0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xF0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xF0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xF0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xF4 "IOMUX_EPWM9_A_CFG_REG,EPWM9_A IO config register." bitfld.long 0xF4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xF4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xF4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xF4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xF4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xF4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xF4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xF4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xF4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xF4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xF4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xF4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xF4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xF8 "IOMUX_EPWM9_B_CFG_REG,EPWM9_B IO config register." bitfld.long 0xF8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xF8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xF8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xF8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xF8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xF8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xF8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xF8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xF8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xF8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xF8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xF8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xF8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xFC "IOMUX_EPWM10_A_CFG_REG,EPWM10_A IO config register." bitfld.long 0xFC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0xFC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0xFC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0xFC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xFC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0xFC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xFC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0xFC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xFC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0xFC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0xFC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0xFC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0xFC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x100 "IOMUX_EPWM10_B_CFG_REG,EPWM10_B IO config register." bitfld.long 0x100 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x100 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x100 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x100 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x100 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x100 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x100 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x100 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x100 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x100 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x100 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x100 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x100 0.--3. 1. "FUNC_SEL,Function select" line.long 0x104 "IOMUX_EPWM11_A_CFG_REG,EPWM11_A IO config register." bitfld.long 0x104 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x104 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x104 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x104 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x104 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x104 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x104 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x104 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x104 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x104 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x104 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x104 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x104 0.--3. 1. "FUNC_SEL,Function select" line.long 0x108 "IOMUX_EPWM11_B_CFG_REG,EPWM11_B IO config register." bitfld.long 0x108 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x108 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x108 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x108 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x108 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x108 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x108 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x108 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x108 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x108 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x108 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x108 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x108 0.--3. 1. "FUNC_SEL,Function select" line.long 0x10C "IOMUX_EPWM12_A_CFG_REG,EPWM12_A IO config register." bitfld.long 0x10C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x10C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x10C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x10C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x10C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x10C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x10C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x10C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x10C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x10C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x10C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x10C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x10C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x110 "IOMUX_EPWM12_B_CFG_REG,EPWM12_B IO config register." bitfld.long 0x110 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x110 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x110 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x110 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x110 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x110 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x110 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x110 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x110 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x110 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x110 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x110 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x110 0.--3. 1. "FUNC_SEL,Function select" line.long 0x114 "IOMUX_EPWM13_A_CFG_REG,EPWM13_A IO config register." bitfld.long 0x114 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x114 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x114 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x114 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x114 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x114 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x114 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x114 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x114 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x114 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x114 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x114 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x114 0.--3. 1. "FUNC_SEL,Function select" line.long 0x118 "IOMUX_EPWM13_B_CFG_REG,EPWM13_B IO config register." bitfld.long 0x118 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x118 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x118 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x118 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x118 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x118 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x118 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x118 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x118 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x118 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x118 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x118 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x118 0.--3. 1. "FUNC_SEL,Function select" line.long 0x11C "IOMUX_EPWM14_A_CFG_REG,EPWM14_A IO config register." bitfld.long 0x11C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x11C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x11C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x11C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x11C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x11C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x11C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x11C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x11C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x11C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x11C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x11C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x11C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x120 "IOMUX_EPWM14_B_CFG_REG,EPWM14_B IO config register." bitfld.long 0x120 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x120 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x120 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x120 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x120 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x120 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x120 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x120 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x120 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x120 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x120 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x120 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x120 0.--3. 1. "FUNC_SEL,Function select" line.long 0x124 "IOMUX_EPWM15_A_CFG_REG,EPWM15_A IO config register." bitfld.long 0x124 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x124 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x124 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x124 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x124 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x124 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x124 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x124 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x124 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x124 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x124 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x124 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x124 0.--3. 1. "FUNC_SEL,Function select" line.long 0x128 "IOMUX_EPWM15_B_CFG_REG,EPWM15_B IO config register." bitfld.long 0x128 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x128 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x128 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x128 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x128 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x128 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x128 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x128 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x128 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x128 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x128 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x128 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x128 0.--3. 1. "FUNC_SEL,Function select" line.long 0x12C "IOMUX_UART1_RXD_CFG_REG,UART1_RXD IO config register." bitfld.long 0x12C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x12C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x12C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x12C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x12C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x12C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x12C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x12C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x12C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x12C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x12C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x12C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x12C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x130 "IOMUX_UART1_TXD_CFG_REG,UART1_TXD IO config register." bitfld.long 0x130 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x130 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x130 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x130 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x130 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x130 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x130 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x130 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x130 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x130 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x130 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x130 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x130 0.--3. 1. "FUNC_SEL,Function select" line.long 0x134 "IOMUX_MMC0_CLK_CFG_REG,MMC0_CLK IO config register." bitfld.long 0x134 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x134 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x134 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x134 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x134 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x134 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x134 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x134 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x134 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x134 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x134 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x134 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x134 0.--3. 1. "FUNC_SEL,Function select" line.long 0x138 "IOMUX_MMC0_CMD_CFG_REG,MMC0_CMD IO config register." bitfld.long 0x138 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x138 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x138 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x138 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x138 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x138 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x138 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x138 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x138 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x138 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x138 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x138 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x138 0.--3. 1. "FUNC_SEL,Function select" line.long 0x13C "IOMUX_MMC0_D0_CFG_REG,MMC0_D0 IO config register." bitfld.long 0x13C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x13C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x13C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x13C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x13C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x13C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x13C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x13C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x13C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x13C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x13C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x13C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x13C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x140 "IOMUX_MMC0_D1_CFG_REG,MMC0_D1 IO config register." bitfld.long 0x140 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x140 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x140 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x140 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x140 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x140 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x140 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x140 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x140 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x140 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x140 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x140 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x140 0.--3. 1. "FUNC_SEL,Function select" line.long 0x144 "IOMUX_MMC0_D2_CFG_REG,MMC0_D2 IO config register." bitfld.long 0x144 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x144 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x144 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x144 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x144 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x144 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x144 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x144 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x144 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x144 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x144 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x144 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x144 0.--3. 1. "FUNC_SEL,Function select" line.long 0x148 "IOMUX_MMC0_D3_CFG_REG,MMC0_D3 IO config register." bitfld.long 0x148 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x148 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x148 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x148 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x148 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x148 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x148 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x148 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x148 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x148 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x148 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x148 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x148 0.--3. 1. "FUNC_SEL,Function select" line.long 0x14C "IOMUX_MMC0_WP_CFG_REG,MMC0_WP IO config register." bitfld.long 0x14C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x14C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x14C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x14C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x14C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x14C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x14C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x14C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x14C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x14C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x14C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x14C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x14C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x150 "IOMUX_MMC0_CD_CFG_REG,MMC0_CD IO config register." bitfld.long 0x150 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x150 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x150 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x150 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x150 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x150 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x150 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x150 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x150 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x150 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x150 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x150 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x150 0.--3. 1. "FUNC_SEL,Function select" line.long 0x154 "IOMUX_PR0_MDIO0_MDIO_CFG_REG,PR0_MDIO0_MDIO IO config register." bitfld.long 0x154 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x154 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x154 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x154 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x154 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x154 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x154 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x154 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x154 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x154 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x154 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x154 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x154 0.--3. 1. "FUNC_SEL,Function select" line.long 0x158 "IOMUX_PR0_MDIO0_MDC_CFG_REG,PR0_MDIO0_MDC IO config register." bitfld.long 0x158 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x158 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x158 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x158 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x158 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x158 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x158 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x158 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x158 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x158 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x158 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x158 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x158 0.--3. 1. "FUNC_SEL,Function select" line.long 0x15C "IOMUX_PR0_PRU0_GPO5_CFG_REG,PR0_PRU0_GPO5 IO config register." bitfld.long 0x15C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x15C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x15C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x15C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x15C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x15C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x15C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x15C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x15C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x15C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x15C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x15C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x15C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x160 "IOMUX_PR0_PRU0_GPO9_CFG_REG,PR0_PRU0_GPO9 IO config register." bitfld.long 0x160 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x160 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x160 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x160 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x160 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x160 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x160 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x160 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x160 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x160 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x160 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x160 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x160 0.--3. 1. "FUNC_SEL,Function select" line.long 0x164 "IOMUX_PR0_PRU0_GPO10_CFG_REG,PR0_PRU0_GPO10 IO config register." bitfld.long 0x164 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x164 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x164 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x164 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x164 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x164 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x164 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x164 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x164 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x164 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x164 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x164 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x164 0.--3. 1. "FUNC_SEL,Function select" line.long 0x168 "IOMUX_PR0_PRU0_GPO8_CFG_REG,PR0_PRU0_GPO8 IO config register." bitfld.long 0x168 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x168 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x168 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x168 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x168 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x168 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x168 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x168 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x168 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x168 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x168 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x168 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x168 0.--3. 1. "FUNC_SEL,Function select" line.long 0x16C "IOMUX_PR0_PRU0_GPO6_CFG_REG,PR0_PRU0_GPO6 IO config register." bitfld.long 0x16C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x16C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x16C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x16C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x16C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x16C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x16C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x16C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x16C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x16C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x16C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x16C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x16C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x170 "IOMUX_PR0_PRU0_GPO4_CFG_REG,PR0_PRU0_GPO4 IO config register." bitfld.long 0x170 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x170 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x170 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x170 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x170 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x170 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x170 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x170 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x170 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x170 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x170 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x170 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x170 0.--3. 1. "FUNC_SEL,Function select" line.long 0x174 "IOMUX_PR0_PRU0_GPO0_CFG_REG,PR0_PRU0_GPO0 IO config register." bitfld.long 0x174 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x174 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x174 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x174 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x174 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x174 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x174 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x174 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x174 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x174 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x174 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x174 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x174 0.--3. 1. "FUNC_SEL,Function select" line.long 0x178 "IOMUX_PR0_PRU0_GPO1_CFG_REG,PR0_PRU0_GPO1 IO config register." bitfld.long 0x178 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x178 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x178 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x178 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x178 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x178 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x178 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x178 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x178 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x178 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x178 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x178 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x178 0.--3. 1. "FUNC_SEL,Function select" line.long 0x17C "IOMUX_PR0_PRU0_GPO2_CFG_REG,PR0_PRU0_GPO2 IO config register." bitfld.long 0x17C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x17C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x17C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x17C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x17C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x17C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x17C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x17C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x17C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x17C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x17C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x17C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x17C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x180 "IOMUX_PR0_PRU0_GPO3_CFG_REG,PR0_PRU0_GPO3 IO config register." bitfld.long 0x180 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x180 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x180 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x180 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x180 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x180 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x180 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x180 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x180 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x180 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x180 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x180 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x180 0.--3. 1. "FUNC_SEL,Function select" line.long 0x184 "IOMUX_PR0_PRU0_GPO16_CFG_REG,PR0_PRU0_GPO16 IO config register." bitfld.long 0x184 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x184 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x184 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x184 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x184 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x184 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x184 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x184 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x184 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x184 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x184 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x184 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x184 0.--3. 1. "FUNC_SEL,Function select" line.long 0x188 "IOMUX_PR0_PRU0_GPO15_CFG_REG,PR0_PRU0_GPO15 IO config register." bitfld.long 0x188 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x188 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x188 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x188 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x188 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x188 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x188 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x188 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x188 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x188 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x188 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x188 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x188 0.--3. 1. "FUNC_SEL,Function select" line.long 0x18C "IOMUX_PR0_PRU0_GPO11_CFG_REG,PR0_PRU0_GPO11 IO config register." bitfld.long 0x18C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x18C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x18C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x18C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x18C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x18C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x18C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x18C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x18C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x18C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x18C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x18C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x18C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x190 "IOMUX_PR0_PRU0_GPO12_CFG_REG,PR0_PRU0_GPO12 IO config register." bitfld.long 0x190 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x190 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x190 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x190 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x190 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x190 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x190 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x190 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x190 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x190 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x190 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x190 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x190 0.--3. 1. "FUNC_SEL,Function select" line.long 0x194 "IOMUX_PR0_PRU0_GPO13_CFG_REG,PR0_PRU0_GPO13 IO config register." bitfld.long 0x194 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x194 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x194 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x194 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x194 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x194 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x194 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x194 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x194 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x194 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x194 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x194 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x194 0.--3. 1. "FUNC_SEL,Function select" line.long 0x198 "IOMUX_PR0_PRU0_GPO14_CFG_REG,PR0_PRU0_GPO14 IO config register." bitfld.long 0x198 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x198 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x198 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x198 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x198 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x198 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x198 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x198 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x198 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x198 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x198 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x198 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x198 0.--3. 1. "FUNC_SEL,Function select" line.long 0x19C "IOMUX_PR0_PRU1_GPO5_CFG_REG,PR0_PRU1_GPO5 IO config register." bitfld.long 0x19C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x19C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x19C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x19C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x19C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x19C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x19C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x19C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x19C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x19C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x19C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x19C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x19C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1A0 "IOMUX_PR0_PRU1_GPO9_CFG_REG,PR0_PRU1_GPO9 IO config register." bitfld.long 0x1A0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1A0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1A0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1A0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1A0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1A0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1A0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1A0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1A0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1A0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1A0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1A0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1A0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1A4 "IOMUX_PR0_PRU1_GPO10_CFG_REG,PR0_PRU1_GPO10 IO config register." bitfld.long 0x1A4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1A4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1A4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1A4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1A4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1A4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1A4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1A4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1A4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1A4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1A4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1A4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1A4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1A8 "IOMUX_PR0_PRU1_GPO8_CFG_REG,PR0_PRU1_GPO8 IO config register." bitfld.long 0x1A8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1A8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1A8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1A8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1A8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1A8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1A8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1A8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1A8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1A8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1A8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1A8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1A8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1AC "IOMUX_PR0_PRU1_GPO6_CFG_REG,PR0_PRU1_GPO6 IO config register." bitfld.long 0x1AC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1AC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1AC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1AC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1AC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1AC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1AC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1AC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1AC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1AC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1AC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1AC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1AC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1B0 "IOMUX_PR0_PRU1_GPO4_CFG_REG,PR0_PRU1_GPO4 IO config register." bitfld.long 0x1B0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1B0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1B0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1B0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1B0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1B0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1B0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1B0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1B0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1B0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1B0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1B0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1B0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1B4 "IOMUX_PR0_PRU1_GPO0_CFG_REG,PR0_PRU1_GPO0 IO config register." bitfld.long 0x1B4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1B4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1B4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1B4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1B4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1B4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1B4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1B4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1B4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1B4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1B4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1B4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1B4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1B8 "IOMUX_PR0_PRU1_GPO1_CFG_REG,PR0_PRU1_GPO1 IO config register." bitfld.long 0x1B8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1B8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1B8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1B8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1B8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1B8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1B8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1B8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1B8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1B8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1B8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1B8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1B8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1BC "IOMUX_PR0_PRU1_GPO2_CFG_REG,PR0_PRU1_GPO2 IO config register." bitfld.long 0x1BC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1BC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1BC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1BC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1BC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1BC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1BC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1BC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1BC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1BC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1BC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1BC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1BC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C0 "IOMUX_PR0_PRU1_GPO3_CFG_REG,PR0_PRU1_GPO3 IO config register." bitfld.long 0x1C0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1C0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1C0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1C0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1C0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1C0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1C0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1C0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1C0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1C0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C4 "IOMUX_PR0_PRU1_GPO16_CFG_REG,PR0_PRU1_GPO16 IO config register." bitfld.long 0x1C4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1C4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1C4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1C4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1C4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1C4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1C4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1C4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1C4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1C4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C8 "IOMUX_PR0_PRU1_GPO15_CFG_REG,PR0_PRU1_GPO15 IO config register." bitfld.long 0x1C8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1C8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1C8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1C8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1C8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1C8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1C8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1C8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1C8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1C8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1CC "IOMUX_PR0_PRU1_GPO11_CFG_REG,PR0_PRU1_GPO11 IO config register." bitfld.long 0x1CC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1CC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1CC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1CC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1CC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1CC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1CC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1CC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1CC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1CC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1CC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1CC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1CC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1D0 "IOMUX_PR0_PRU1_GPO12_CFG_REG,PR0_PRU1_GPO12 IO config register." bitfld.long 0x1D0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1D0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1D0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1D0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1D0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1D0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1D0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1D0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1D0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1D0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1D0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1D0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1D0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1D4 "IOMUX_PR0_PRU1_GPO13_CFG_REG,PR0_PRU1_GPO13 IO config register." bitfld.long 0x1D4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1D4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1D4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1D4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1D4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1D4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1D4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1D4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1D4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1D4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1D4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1D4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1D4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1D8 "IOMUX_PR0_PRU1_GPO14_CFG_REG,PR0_PRU1_GPO14 IO config register." bitfld.long 0x1D8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1D8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1D8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1D8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1D8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1D8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1D8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1D8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1D8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1D8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1D8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1D8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1D8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1DC "IOMUX_PR0_PRU1_GPO19_CFG_REG,PR0_PRU1_GPO19 IO config register." bitfld.long 0x1DC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1DC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1DC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1DC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1DC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1DC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1DC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1DC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1DC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1DC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1DC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1DC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1DC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1E0 "IOMUX_PR0_PRU1_GPO18_CFG_REG,PR0_PRU1_GPO18 IO config register." bitfld.long 0x1E0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1E0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1E0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1E0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1E0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1E0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1E0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1E0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1E0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1E0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1E0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1E0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1E0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1E4 "IOMUX_EXT_REFCLK0_CFG_REG,EXT_REFCLK0 IO config register." bitfld.long 0x1E4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1E4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1E4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1E4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1E4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1E4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1E4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1E4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1E4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1E4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1E4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1E4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1E4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1E8 "IOMUX_SDFM0_CLK0_CFG_REG,SDFM0_CLK0 IO config register." bitfld.long 0x1E8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1E8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1E8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1E8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1E8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1E8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1E8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1E8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1E8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1E8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1E8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1E8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1E8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1EC "IOMUX_SDFM0_D0_CFG_REG,SDFM0_D0 IO config register." bitfld.long 0x1EC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1EC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1EC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1EC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1EC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1EC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1EC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1EC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1EC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1EC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1EC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1EC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1EC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1F0 "IOMUX_SDFM0_CLK1_CFG_REG,SDFM0_CLK1 IO config register." bitfld.long 0x1F0 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1F0 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1F0 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1F0 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1F0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1F0 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1F0 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1F0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1F0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1F0 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1F0 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1F0 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1F0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1F4 "IOMUX_SDFM0_D1_CFG_REG,SDFM0_D1 IO config register." bitfld.long 0x1F4 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1F4 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1F4 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1F4 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1F4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1F4 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1F4 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1F4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1F4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1F4 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1F4 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1F4 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1F4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1F8 "IOMUX_SDFM0_CLK2_CFG_REG,SDFM0_CLK2 IO config register." bitfld.long 0x1F8 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1F8 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1F8 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1F8 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1F8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1F8 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1F8 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1F8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1F8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1F8 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1F8 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1F8 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1F8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1FC "IOMUX_SDFM0_D2_CFG_REG,SDFM0_D2 IO config register." bitfld.long 0x1FC 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x1FC 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x1FC 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x1FC 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1FC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x1FC 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1FC 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x1FC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1FC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x1FC 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x1FC 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x1FC 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x1FC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x200 "IOMUX_SDFM0_CLK3_CFG_REG,SDFM0_CLK3 IO config register." bitfld.long 0x200 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x200 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x200 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x200 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x200 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x200 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x200 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x200 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x200 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x200 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x200 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x200 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x200 0.--3. 1. "FUNC_SEL,Function select" line.long 0x204 "IOMUX_SDFM0_D3_CFG_REG,SDFM0_D3 IO config register." bitfld.long 0x204 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x204 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x204 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x204 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x204 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x204 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x204 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x204 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x204 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x204 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x204 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x204 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x204 0.--3. 1. "FUNC_SEL,Function select" line.long 0x208 "IOMUX_EQEP0_A_CFG_REG,EQEP0_A IO config register." bitfld.long 0x208 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x208 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x208 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x208 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x208 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x208 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x208 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x208 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x208 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x208 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x208 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x208 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x208 0.--3. 1. "FUNC_SEL,Function select" line.long 0x20C "IOMUX_EQEP0_B_CFG_REG,EQEP0_B IO config register." bitfld.long 0x20C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x20C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x20C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x20C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x20C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x20C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x20C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x20C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x20C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x20C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x20C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x20C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x20C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x210 "IOMUX_EQEP0_STROBE_CFG_REG,EQEP0_STROBE IO config register." bitfld.long 0x210 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x210 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x210 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x210 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x210 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x210 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x210 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x210 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x210 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x210 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x210 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x210 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x210 0.--3. 1. "FUNC_SEL,Function select" line.long 0x214 "IOMUX_EQEP0_INDEX_CFG_REG,EQEP0_INDEX IO config register." bitfld.long 0x214 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x214 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x214 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x214 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x214 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x214 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x214 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x214 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x214 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x214 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x214 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x214 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x214 0.--3. 1. "FUNC_SEL,Function select" line.long 0x218 "IOMUX_I2C0_SDA_CFG_REG,I2C0_SDA IO config register." bitfld.long 0x218 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x218 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x218 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x218 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x218 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x218 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x218 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x218 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x218 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x218 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x218 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x218 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x218 0.--3. 1. "FUNC_SEL,Function select" line.long 0x21C "IOMUX_I2C0_SCL_CFG_REG,I2C0_SCL IO config register." bitfld.long 0x21C 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x21C 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x21C 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x21C 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x21C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x21C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x21C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x21C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x21C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x21C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x21C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x21C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x21C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x220 "IOMUX_MCAN2_TX_CFG_REG,MCAN2_TX IO config register." bitfld.long 0x220 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x220 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x220 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x220 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x220 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x220 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x220 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x220 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x220 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x220 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x220 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x220 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x220 0.--3. 1. "FUNC_SEL,Function select" line.long 0x224 "IOMUX_MCAN2_RX_CFG_REG,MCAN2_RX IO config register." bitfld.long 0x224 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x224 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x224 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x224 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x224 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x224 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x224 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x224 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x224 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x224 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x224 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x224 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x224 0.--3. 1. "FUNC_SEL,Function select" line.long 0x228 "IOMUX_CLKOUT0_CFG_REG,CLKOUT0 IO config register." bitfld.long 0x228 22. "SAFETY_OVERRIDE_SEL,mux Select Value to choose between Actual IO pad input and Safety override mux output1 Safety override mux output is selected0 Actual IO pad input is selected" "0,1" newline bitfld.long 0x228 21. "ICSSM_GPIO_SEL,mux Select Value to choose between ICSSM_GPIO and normal GPIO 1 ICSSM_GPIO is selected0 Normal GPIO is selected" "0,1" newline bitfld.long 0x228 20. "INP_INV_SEL,Select Value for chosing inverted version of PAD input for chip:0 : Non Inverted1 : Inverted" "0: Non Inverted1 : Inverted,?" newline bitfld.long 0x228 18.--19. "QUAL_SEL,Select Value for chosing input qualifer type for PAD.00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x228 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO.0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" newline bitfld.long 0x228 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x228 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x228 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x228 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x228 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x228 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x228 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline hexmask.long.byte 0x228 0.--3. 1. "FUNC_SEL,Function select" line.long 0x22C "IOMUX_WARMRSTN_CFG_REG,WARMRSTn IO config register." bitfld.long 0x22C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x22C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x22C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x22C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x22C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x22C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x22C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x230 "IOMUX_SAFETY_ERRORN_CFG_REG,SAFETY_ERRORn IO config register." bitfld.long 0x230 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x230 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x230 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x230 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x230 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x230 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x230 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x234 "IOMUX_TDI_CFG_REG,TDI IO config register." bitfld.long 0x234 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x234 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x234 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x234 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x234 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x234 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x234 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x238 "IOMUX_TDO_CFG_REG,TDO IO config register." bitfld.long 0x238 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x238 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x238 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x238 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x238 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x238 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x238 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x23C "IOMUX_TMS_CFG_REG,TMS IO config register." bitfld.long 0x23C 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x23C 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x23C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x23C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x23C 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x23C 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x23C 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x240 "IOMUX_TCK_CFG_REG,TCK IO config register." bitfld.long 0x240 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x240 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x240 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x240 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x240 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x240 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x240 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x244 "IOMUX_OSPI0_CLKLB_CFG_REG,OSPI0_CLKLB IO config register." bitfld.long 0x244 10. "SC1,IO Slew Rate Control :0 : higher slew rate.1:Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x244 9. "PUPDSEL,Internal Pull Resistor Direction Control bit0:Pull-down Resistor1:Pull-up Resistor" "0,1" newline bitfld.long 0x244 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x244 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x244 6. "OE_OVERRIDE_CTRL,Output Override Control bit (Active Low)This bit provides a software override for the default OE_N/GZ hardware control.0:Enable pad input override1:Disable pad input override" "0: Enable pad input override1:Disable pad input..,?" newline bitfld.long 0x244 5. "IE_OVERRIDE,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH)" "0: Override pad input signal to 0,1: Override pad input signal to 1" newline bitfld.long 0x244 4. "IE_OVERRIDE_CTRL,Input Override (Active Low)0:Override pad input signal to 0 (LOW)1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0: Override pad input signal to 0,1: Override pad input signal to 1" line.long 0x248 "IOMUX_QUAL_GRP_0_CFG_REG,QUAL_GRP_0 config register." hexmask.long.byte 0x248 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x24C "IOMUX_QUAL_GRP_1_CFG_REG,QUAL_GRP_1 config register." hexmask.long.byte 0x24C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x250 "IOMUX_QUAL_GRP_2_CFG_REG,QUAL_GRP_2 config register." hexmask.long.byte 0x250 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x254 "IOMUX_QUAL_GRP_3_CFG_REG,QUAL_GRP_3 config register." hexmask.long.byte 0x254 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x258 "IOMUX_QUAL_GRP_4_CFG_REG,QUAL_GRP_4 config register." hexmask.long.byte 0x258 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x25C "IOMUX_QUAL_GRP_5_CFG_REG,QUAL_GRP_5 config register." hexmask.long.byte 0x25C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x260 "IOMUX_QUAL_GRP_6_CFG_REG,QUAL_GRP_6 config register." hexmask.long.byte 0x260 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x264 "IOMUX_QUAL_GRP_7_CFG_REG,QUAL_GRP_7 config register." hexmask.long.byte 0x264 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x268 "IOMUX_QUAL_GRP_8_CFG_REG,QUAL_GRP_8 config register." hexmask.long.byte 0x268 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x26C "IOMUX_QUAL_GRP_9_CFG_REG,QUAL_GRP_9 config register." hexmask.long.byte 0x26C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x270 "IOMUX_QUAL_GRP_10_CFG_REG,QUAL_GRP_10 config register." hexmask.long.byte 0x270 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x274 "IOMUX_QUAL_GRP_11_CFG_REG,QUAL_GRP_11 config register." hexmask.long.byte 0x274 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x278 "IOMUX_QUAL_GRP_12_CFG_REG,QUAL_GRP_12 config register." hexmask.long.byte 0x278 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x27C "IOMUX_QUAL_GRP_13_CFG_REG,QUAL_GRP_13 config register." hexmask.long.byte 0x27C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x280 "IOMUX_QUAL_GRP_14_CFG_REG,QUAL_GRP_14 config register." hexmask.long.byte 0x280 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x284 "IOMUX_QUAL_GRP_15_CFG_REG,QUAL_GRP_15 config register." hexmask.long.byte 0x284 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x288 "IOMUX_QUAL_GRP_16_CFG_REG,QUAL_GRP_16 config register." hexmask.long.byte 0x288 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x28C "IOMUX_QUAL_GRP_17_CFG_REG,QUAL_GRP_17 config register." hexmask.long.byte 0x28C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x290 "IOMUX_USER_MODE_EN,USER_MODE_EN config register." hexmask.long 0x290 0.--31. 1. "USER_MODE_EN,Write 0XADADADAD to enable user mode write access to IO CFG space" line.long 0x294 "IOMUX_PADGLBL_CFG_REG,Global config register for IO." hexmask.long 0x294 0.--31. 1. "PADGLBL_CFG_REG,20 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs.3 : global_ie_n_val - Active low108 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs.11 :.." line.long 0x298 "IOMUX_IO_CFG_KICK0,KICK0 config register." hexmask.long 0x298 0.--31. 1. "IO_CFG_KICK0,Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU.write access to the above PIN MUX registers [including IOCFGKICK1]" line.long 0x29C "IOMUX_IO_CFG_KICK1,KICK1 config register." hexmask.long 0x29C 0.--31. 1. "IO_CFG_KICK1,Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers [excluding IOCFGKICK0]. IOCFGKICK0 has to be written with 83E70B13h to enable access to.." tree.end tree "MSS_MBOX0" base ad:0x72000000 group.long 0x0++0x3 line.long 0x0 "MSS_MBOX_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x3FFC++0x3 line.long 0x0 "MSS_MBOX_END" hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MSS_RCM" base ad:0x53208000 rgroup.long 0x10++0x3 line.long 0x0 "MSS_RCM_R5SS0_RST_STATUS,R5SS Reset Cause Status register of corresponding R5SS." hexmask.long.word 0x0 0.--10. 1. "R5SS0_RST_STATUS_CAUSE,Has the status because of which reset has happened. Bit0: POR ResetBit1: Warm Reset [ALso set during POR Reset]Bit2: CR5SS0 STC ResetBit3 Reset for CORE0 and MSS_CORE00_VIM using MSS_RCM::MSS_CR5SSA0_RST_CTRLBit4: Reset for.." group.long 0x14++0x13 line.long 0x0 "MSS_RCM_R5SS0_RST_CAUSE_CLR,R5SS Reset Cause Clear register of corresponding R5SS." bitfld.long 0x0 0.--2. "R5SS0_RST_CAUSE_CLR_CLR,Write pulse bit field:Clear bit for rst cause register [Writing 3'b111 will clear the rst cause register]" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_R5SS0_DBG_RST_EN,This register enables Core debug reset request to propogate to RCM." bitfld.long 0x4 16.--18. "R5SS0_DBG_RST_EN_EN_CORE1,Writing 3'b111 will block debug reset request from CORE1 toggling reset for CORE1 of respective R5SS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "R5SS0_DBG_RST_EN_EN_CORE0,Writing 3'b111 will block debug reset request from CORE0 toggling reset for CORE0 of respective R5SS" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_R5SS0_RST_ASSERDLY,This register controls the reset duration of the corrseponding R5SS." hexmask.long.byte 0x8 0.--7. 1. "R5SS0_RST_ASSERDLY_COMMON,Value decides number of cycles reset should be kept asserted for CR5SS related resets. Programming a value of 0xFF will keep the reset asserted untill a new value other than 0xFF is written to this registerThe actual duration is.." line.long 0xC "MSS_RCM_R5SS0_RST2ASSERTDLY,This register controls the delay of Reset assertion to the corresponding R5SS." hexmask.long.byte 0xC 24.--31. 1. "R5SS0_RST2ASSERTDLY_R5_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE1" hexmask.long.byte 0xC 16.--23. 1. "R5SS0_RST2ASSERTDLY_R5_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE0." newline hexmask.long.byte 0xC 8.--15. 1. "R5SS0_RST2ASSERTDLY_R5SS_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE1" hexmask.long.byte 0xC 0.--7. 1. "R5SS0_RST2ASSERTDLY_R5SS_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE0." line.long 0x10 "MSS_RCM_R5SS0_RST_WFICHECK,Enable WFI ceck before R5 Reset is asserted." bitfld.long 0x10 24.--26. "R5SS0_RST_WFICHECK_EN_R5_CORE1,Writing 3'b000 will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "R5SS0_RST_WFICHECK_R5A,Writing 3'b000 will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "R5SS0_RST_WFICHECK_EN_R5SS_CORE1,Writing 3'b000 will disable check for WFI before global reset assertion of CORE1" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "R5SS0_RST_WFICHECK_EN_R5SS_CORE0,Writing 3'b000 will disable check for WFI before global reset assertion of CORE0" "0,1,2,3,4,5,6,7" rgroup.long 0x30++0x3 line.long 0x0 "MSS_RCM_R5SS1_RST_STATUS,R5SS Reset Cause Status register of corresponding R5SS." hexmask.long.word 0x0 0.--10. 1. "R5SS1_RST_STATUS_CAUSE,Has the status because of which reset has happened. Bit0: POR ResetBit1: Warm Reset [ALso set during POR Reset]Bit2: CR5SS1 STC ResetBit3 Reset for CORE0 and MSS_CORE00_VIM using MSS_RCM::MSS_CR5SSA0_RST_CTRLBit4: Reset for.." group.long 0x34++0x13 line.long 0x0 "MSS_RCM_R5SS1_RST_CAUSE_CLR,R5SS Reset Cause Clear register of corresponding R5SS." bitfld.long 0x0 0.--2. "R5SS1_RST_CAUSE_CLR_CLR,Write pulse bit field:Clear bit for rst cause register [Writing 3'b111 will clear the rst cause register]" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_R5SS1_DBG_RST_EN,This register enables Core debug reset request to propogate to RCM." bitfld.long 0x4 16.--18. "R5SS1_DBG_RST_EN_EN_CORE1,Writing 3'b111 will block debug reset request from CORE1 toggling reset for CORE1 of respective R5SS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "R5SS1_DBG_RST_EN_EN_CORE0,Writing 3'b111 will block debug reset request from CORE0 toggling reset for CORE0 of respective R5SS" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_R5SS1_RST_ASSERDLY,This register controls the reset duration of the corrseponding R5SS." hexmask.long.byte 0x8 0.--7. 1. "R5SS1_RST_ASSERDLY_COMMON,Value decides number of cycles reset should be kept asserted for CR5SS related resets. Programming a value of 0xFF will keep the reset asserted untill a new value other than 0xFF is written to this registerThe actual duration is.." line.long 0xC "MSS_RCM_R5SS1_RST2ASSERTDLY,This register controls the delay of Reset assertion to the corresponding R5SS." hexmask.long.byte 0xC 24.--31. 1. "R5SS1_RST2ASSERTDLY_R5_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE1" hexmask.long.byte 0xC 16.--23. 1. "R5SS1_RST2ASSERTDLY_R5_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE0." newline hexmask.long.byte 0xC 8.--15. 1. "R5SS1_RST2ASSERTDLY_R5SS_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE1" hexmask.long.byte 0xC 0.--7. 1. "R5SS1_RST2ASSERTDLY_R5SS_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE0." line.long 0x10 "MSS_RCM_R5SS1_RST_WFICHECK,Enable WFI ceck before R5 Reset is asserted." bitfld.long 0x10 24.--26. "R5SS1_RST_WFICHECK_EN_R5_CORE1,Writing 3'b000 will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "R5SS1_RST_WFICHECK_R5A,Writing 3'b000 will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "R5SS1_RST_WFICHECK_EN_R5SS_CORE1,Writing 3'b000 will disable check for WFI before global reset assertion of CORE1" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "R5SS1_RST_WFICHECK_EN_R5SS_CORE0,Writing 3'b000 will disable check for WFI before global reset assertion of CORE0" "0,1,2,3,4,5,6,7" group.long 0x80++0x3 line.long 0x0 "MSS_RCM_CPSW_5_50_250_CLK_MUX_CTRL,CPSW CLK MUX CTRL to select DPLL_PER_HSDIV0_CLKOUT1 or DPLL_CORE_HSDIV0_CLKOUT1." bitfld.long 0x0 0.--2. "CPSW_5_50_250_CLK_MUX_CTRL_CLKSRCSEL,CPSW CLK MUX CTRL to select DPLL_PER_HSDIV0_CLKOUT1 or DPLL_CORE_HSDIV0_CLKOUT13'b000: DPLL_CORE_HSDIV0_CLKOUT1 [default]3'b111: DPLL_PER_HSDIV0_CLKOUT1**Note: The input clocks to the mux should be disabled when.." "0,1,2,3,4,5,6,7" group.long 0x100++0x23 line.long 0x0 "MSS_RCM_MCAN0_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x0 0.--11. 1. "MCAN0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x4 "MSS_RCM_MCAN1_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x4 0.--11. 1. "MCAN1_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x8 "MSS_RCM_MCAN2_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x8 0.--11. 1. "MCAN2_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0xC "MSS_RCM_MCAN3_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0xC 0.--11. 1. "MCAN3_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x10 "MSS_RCM_OSPI0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x10 0.--11. 1. "OSPI0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for OSPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x14 "MSS_RCM_RTI0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x14 0.--11. 1. "RTI0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x18 "MSS_RCM_RTI1_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x18 0.--11. 1. "RTI1_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x1C "MSS_RCM_RTI2_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x1C 0.--11. 1. "RTI2_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x20 "MSS_RCM_RTI3_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x20 0.--11. 1. "RTI3_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." group.long 0x128++0xF line.long 0x0 "MSS_RCM_WDT0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x0 0.--11. 1. "WDT0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x4 "MSS_RCM_WDT1_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x4 0.--11. 1. "WDT1_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x8 "MSS_RCM_WDT2_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x8 0.--11. 1. "WDT2_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0xC "MSS_RCM_WDT3_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0xC 0.--11. 1. "WDT3_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." group.long 0x13C++0x1F line.long 0x0 "MSS_RCM_MCSPI0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x0 0.--11. 1. "MCSPI0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x4 "MSS_RCM_MCSPI1_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x4 0.--11. 1. "MCSPI1_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x8 "MSS_RCM_MCSPI2_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x8 0.--11. 1. "MCSPI2_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0xC "MSS_RCM_MCSPI3_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0xC 0.--11. 1. "MCSPI3_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x10 "MSS_RCM_MCSPI4_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x10 0.--11. 1. "MCSPI4_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x14 "MSS_RCM_MMC0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x14 0.--11. 1. "MMC0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for MMCSD.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x18 "MSS_RCM_PRU_ICSS0_UART0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x18 0.--11. 1. "PRU_ICSS0_UART0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for ICSSM_UCLK.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x1C "MSS_RCM_CPTS_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x1C 0.--11. 1. "CPTS_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for CPTS.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." group.long 0x160++0x7 line.long 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x0 0.--11. 1. "CONTROLSS_PLL_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for CONTROLSS_PLL.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x4 "MSS_RCM_I2C_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x4 0.--11. 1. "I2C_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for I2C.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk src-0x000.." group.long 0x174++0x43 line.long 0x0 "MSS_RCM_LIN0_UART0_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x0 0.--11. 1. "LIN0_UART0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following.." line.long 0x4 "MSS_RCM_LIN1_UART1_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x4 0.--11. 1. "LIN1_UART1_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following.." line.long 0x8 "MSS_RCM_LIN2_UART2_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x8 0.--11. 1. "LIN2_UART2_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following.." line.long 0xC "MSS_RCM_LIN3_UART3_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0xC 0.--11. 1. "LIN3_UART3_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following.." line.long 0x10 "MSS_RCM_LIN4_UART4_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x10 0.--11. 1. "LIN4_UART4_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following.." line.long 0x14 "MSS_RCM_LIN5_UART5_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x14 0.--11. 1. "LIN5_UART5_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following.." line.long 0x18 "MSS_RCM_MCAN4_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x18 0.--11. 1. "MCAN4_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x1C "MSS_RCM_MCAN5_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x1C 0.--11. 1. "MCAN5_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x20 "MSS_RCM_MCAN6_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x20 0.--11. 1. "MCAN6_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x24 "MSS_RCM_MCAN7_CLK_SRC_SEL,Clock Source selection Register for corresponding Root clock." hexmask.long.word 0x24 0.--11. 1. "MCAN7_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values for.." line.long 0x28 "MSS_RCM_RTI4_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x28 0.--11. 1. "RTI4_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x2C "MSS_RCM_RTI5_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x2C 0.--11. 1. "RTI5_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x30 "MSS_RCM_RTI6_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x30 0.--11. 1. "RTI6_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x34 "MSS_RCM_RTI7_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x34 0.--11. 1. "RTI7_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Use the following values to.." line.long 0x38 "MSS_RCM_MCSPI5_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x38 0.--11. 1. "MCSPI5_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x3C "MSS_RCM_MCSPI6_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x3C 0.--11. 1. "MCSPI6_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." line.long 0x40 "MSS_RCM_MCSPI7_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x40 0.--11. 1. "MCSPI7_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to.." group.long 0x200++0x23 line.long 0x0 "MSS_RCM_MCAN0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x0 0.--11. 1. "MCAN0_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x4 "MSS_RCM_MCAN1_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x4 0.--11. 1. "MCAN1_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x8 "MSS_RCM_MCAN2_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x8 0.--11. 1. "MCAN2_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0xC "MSS_RCM_MCAN3_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0xC 0.--11. 1. "MCAN3_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x10 "MSS_RCM_OSPI0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x10 0.--11. 1. "OSPI0_CLK_DIV_VAL_CLKDIVR,Divider value OSPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x14 "MSS_RCM_RTI0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x14 0.--11. 1. "RTI0_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x18 "MSS_RCM_RTI1_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x18 0.--11. 1. "RTI1_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x1C "MSS_RCM_RTI2_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x1C 0.--11. 1. "RTI2_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x20 "MSS_RCM_RTI3_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x20 0.--11. 1. "RTI3_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." group.long 0x228++0xF line.long 0x0 "MSS_RCM_WDT0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x0 0.--11. 1. "WDT0_CLK_DIV_VAL_CLKDIVR,Divider value WDT selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x4 "MSS_RCM_WDT1_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x4 0.--11. 1. "WDT1_CLK_DIV_VAL_CLKDIVR,Divider value WDT selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x8 "MSS_RCM_WDT2_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x8 0.--11. 1. "WDT2_CLK_DIV_VAL_CLKDIVR,Divider value WDT selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0xC "MSS_RCM_WDT3_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0xC 0.--11. 1. "WDT3_CLK_DIV_VAL_CLKDIVR,Divider value WDT selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." group.long 0x23C++0x1F line.long 0x0 "MSS_RCM_MCSPI0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x0 0.--11. 1. "MCSPI0_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x4 "MSS_RCM_MCSPI1_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x4 0.--11. 1. "MCSPI1_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x8 "MSS_RCM_MCSPI2_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x8 0.--11. 1. "MCSPI2_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0xC "MSS_RCM_MCSPI3_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0xC 0.--11. 1. "MCSPI3_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x10 "MSS_RCM_MCSPI4_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x10 0.--11. 1. "MCSPI4_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x14 "MSS_RCM_MMC0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x14 0.--11. 1. "MMC0_CLK_DIV_VAL_CLKDIVR,Divider value MMCSD selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x18 "MSS_RCM_PRU_ICSS0_UART_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x18 0.--11. 1. "PRU_ICSS0_UART_CLK_DIV_VAL_CLKDIVR,Divider value ICSSM_UCLK selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x1C "MSS_RCM_CPTS_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x1C 0.--11. 1. "CPTS_CLK_DIV_VAL_CLKDIVR,Divider value CPTS selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." group.long 0x260++0x7 line.long 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_DIV_VAL,CONTROLSS_PLL_CLK Divider Value for Control subsystem." hexmask.long.word 0x0 0.--11. 1. "CONTROLSS_PLL_CLK_DIV_VAL_CLKDIVR,Divider value CONTROLSS_PLL selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x4 "MSS_RCM_I2C_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x4 0.--11. 1. "I2C_CLK_DIV_VAL_CLKDIVR,Divider value I2C selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." group.long 0x274++0x2B line.long 0x0 "MSS_RCM_LIN0_UART0_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x0 0.--11. 1. "LIN0_UART0_CLK_DIV_VAL_CLKDIVR,Divider value for corresponding UART and LIN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is.." line.long 0x4 "MSS_RCM_LIN1_UART1_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x4 0.--11. 1. "LIN1_UART1_CLK_DIV_VAL_CLKDIVR,Divider value for corresponding UART and LIN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is.." line.long 0x8 "MSS_RCM_LIN2_UART2_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x8 0.--11. 1. "LIN2_UART2_CLK_DIV_VAL_CLKDIVR,Divider value for corresponding UART and LIN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is.." line.long 0xC "MSS_RCM_LIN3_UART3_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0xC 0.--11. 1. "LIN3_UART3_CLK_DIV_VAL_CLKDIVR,Divider value for corresponding UART and LIN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is.." line.long 0x10 "MSS_RCM_LIN4_UART4_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x10 0.--11. 1. "LIN4_UART4_CLK_DIV_VAL_CLKDIVR,Divider value for corresponding UART and LIN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is.." line.long 0x14 "MSS_RCM_LIN5_UART5_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x14 0.--11. 1. "LIN5_UART5_CLK_DIV_VAL_CLKDIVR,Divider value for corresponding UART and LIN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is.." line.long 0x18 "MSS_RCM_RGMII_250_CLK_DIV_VAL,RGMII 250 CLK Divider Value." hexmask.long.word 0x18 0.--11. 1. "RGMII_250_CLK_DIV_VAL_CLKDIVR,Divider value RGMII selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x1C "MSS_RCM_RGMII_50_CLK_DIV_VAL,RGMII 50 CLK Divider Value." hexmask.long.word 0x1C 0.--11. 1. "RGMII_50_CLK_DIV_VAL_CLKDIVR,Divider value MII100 selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x20 "MSS_RCM_RGMII_5_CLK_DIV_VAL,RGMII 5 CLK Divider Value." hexmask.long.tbyte 0x20 0.--23. 1. "RGMII_5_CLK_DIV_VAL_CLKDIVR,Divider value MII10 selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x15' is required then '0x151515' should be.." line.long 0x24 "MSS_RCM_XTAL_MMC_32K_CLK_DIV_VAL,XTAL 32K CLK Divider Value for MMC." hexmask.long 0x24 0.--29. 1. "XTAL_MMC_32K_CLK_DIV_VAL_CLKDIVR,Divider value for XTAL_32K clock. To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x30C' is required then register should.." line.long 0x28 "MSS_RCM_XTAL_TEMPSENSE_32K_CLK_DIV_VAL,XTAL 32K CLK Divider Value for Temp Sensor." hexmask.long 0x28 0.--29. 1. "XTAL_TEMPSENSE_32K_CLK_DIV_VAL_CLKDIVR,Divider value for XTAL_32K clock. To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x30C' is required then register.." group.long 0x2A4++0x2B line.long 0x0 "MSS_RCM_MCAN4_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x0 0.--11. 1. "MCAN4_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x4 "MSS_RCM_MCAN5_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x4 0.--11. 1. "MCAN5_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x8 "MSS_RCM_MCAN6_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x8 0.--11. 1. "MCAN6_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0xC "MSS_RCM_MCAN7_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0xC 0.--11. 1. "MCAN7_CLK_DIV_VAL_CLKDIVR,Divider value corresponding MCAN selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x10 "MSS_RCM_RTI4_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x10 0.--11. 1. "RTI4_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x14 "MSS_RCM_RTI5_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x14 0.--11. 1. "RTI5_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x18 "MSS_RCM_RTI6_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x18 0.--11. 1. "RTI6_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x1C "MSS_RCM_RTI7_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x1C 0.--11. 1. "RTI7_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x20 "MSS_RCM_MCSPI5_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x20 0.--11. 1. "MCSPI5_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x24 "MSS_RCM_MCSPI6_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x24 0.--11. 1. "MCSPI6_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." line.long 0x28 "MSS_RCM_MCSPI7_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x28 0.--11. 1. "MCSPI7_CLK_DIV_VAL_CLKDIVR,Divider value Corresponding SPI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888'.." group.long 0x300++0x23 line.long 0x0 "MSS_RCM_MCAN0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x0 0.--2. "MCAN0_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_MCAN1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x4 0.--2. "MCAN1_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_MCAN2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x8 0.--2. "MCAN2_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_MCAN3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0xC 0.--2. "MCAN3_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_OSPI0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x10 0.--2. "OSPI0_CLK_GATE_GATED,Writing 3'b111 will gate clock for OSPI" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_RTI0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x14 0.--2. "RTI0_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_RTI1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x18 0.--2. "RTI1_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_RTI2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x1C 0.--2. "RTI2_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_RTI3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x20 0.--2. "RTI3_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" group.long 0x328++0xF line.long 0x0 "MSS_RCM_WDT0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x0 0.--2. "WDT0_CLK_GATE_GATED,Writing 3'b111 will gate clock for WDT" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_WDT1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x4 0.--2. "WDT1_CLK_GATE_GATED,Writing 3'b111 will gate clock for WDT" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_WDT2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x8 0.--2. "WDT2_CLK_GATE_GATED,Writing 3'b111 will gate clock for WDT" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_WDT3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0xC 0.--2. "WDT3_CLK_GATE_GATED,Writing 3'b111 will gate clock for WDT" "0,1,2,3,4,5,6,7" group.long 0x33C++0x1F line.long 0x0 "MSS_RCM_MCSPI0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x0 0.--2. "MCSPI0_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_MCSPI1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x4 0.--2. "MCSPI1_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_MCSPI2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x8 0.--2. "MCSPI2_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_MCSPI3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0xC 0.--2. "MCSPI3_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_MCSPI4_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x10 0.--2. "MCSPI4_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_MMC0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x14 0.--2. "MMC0_CLK_GATE_GATED,Writing 3'b111 will gate clock for MMCSD" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_PRU_ICSS0_UART_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x18 0.--2. "PRU_ICSS0_UART_CLK_GATE_GATED,Writing 3'b111 will gate clock for ICSSM_UCLK" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_CPTS_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x1C 0.--2. "CPTS_CLK_GATE_GATED,Writing 3'b111 will gate clock for CPTS" "0,1,2,3,4,5,6,7" group.long 0x360++0x27 line.long 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x0 0.--2. "CONTROLSS_PLL_CLK_GATE_GATED,Writing 3'b111 will gate clock for CONTROLSS_PLL" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_I2C0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x4 0.--2. "I2C0_CLK_GATE_GATED,Writing 3'b111 will gate clock for I2C" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_I2C1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x8 0.--2. "I2C1_CLK_GATE_GATED,Writing 3'b111 will gate clock for I2C" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_I2C2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0xC 0.--2. "I2C2_CLK_GATE_GATED,Writing 3'b111 will gate clock for I2C" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_I2C3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x10 0.--2. "I2C3_CLK_GATE_GATED,Writing 3'b111 will gate clock for I2C" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_LIN0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x14 0.--2. "LIN0_CLK_GATE_GATED,Writing 3'b111 will gate clock for SPIB" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_LIN1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x18 0.--2. "LIN1_CLK_GATE_GATED,Writing 3'b111 will gate clock for SPIB" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_LIN2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x1C 0.--2. "LIN2_CLK_GATE_GATED,Writing 3'b111 will gate clock for SPIB" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_LIN3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x20 0.--2. "LIN3_CLK_GATE_GATED,Writing 3'b111 will gate clock for SPIB" "0,1,2,3,4,5,6,7" line.long 0x24 "MSS_RCM_LIN4_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x24 0.--2. "LIN4_CLK_GATE_GATED,Writing 3'b111 will gate clock for SPIB" "0,1,2,3,4,5,6,7" group.long 0x38C++0x3B line.long 0x0 "MSS_RCM_UART0_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x0 0.--2. "UART0_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_UART1_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x4 0.--2. "UART1_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_UART2_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x8 0.--2. "UART2_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_UART3_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0xC 0.--2. "UART3_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_UART4_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x10 0.--2. "UART4_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_UART5_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x14 0.--2. "UART5_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_RGMII_250_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x18 0.--2. "RGMII_250_CLK_GATE_GATED,Writing 3'b111 will gate clock for RGMII" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_RGMII_50_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x1C 0.--2. "RGMII_50_CLK_GATE_GATED,Writing 3'b111 will gate clock for MII100" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_RGMII_5_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x20 0.--2. "RGMII_5_CLK_GATE_GATED,Writing 3'b111 will gate clock for MII10" "0,1,2,3,4,5,6,7" line.long 0x24 "MSS_RCM_MMC0_32K_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x24 0.--2. "MMC0_32K_CLK_GATE_GATED,Writing 3'b111 will gate clock for MMCSD_32K" "0,1,2,3,4,5,6,7" line.long 0x28 "MSS_RCM_TEMPSENSE_32K_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x28 0.--2. "TEMPSENSE_32K_CLK_GATE_GATED,Writing 3'b111 will gate clock for TEMPSENSE_32K" "0,1,2,3,4,5,6,7" line.long 0x2C "MSS_RCM_CPSW_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x2C 0.--2. "CPSW_CLK_GATE_GATED,Writing 3'b111 will gate clock for CPSW CPPI" "0,1,2,3,4,5,6,7" line.long 0x30 "MSS_RCM_PRU_ICSS0_IEP_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x30 0.--2. "PRU_ICSS0_IEP_CLK_GATE_GATED,Writing 3'b111 will gate clock for ICSSM_IEP" "0,1,2,3,4,5,6,7" line.long 0x34 "MSS_RCM_PRU_ICSS0_CORE_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x34 0.--2. "PRU_ICSS0_CORE_CLK_GATE_GATED,Writing 3'b111 will gate clock for ICSSM_CORE" "0,1,2,3,4,5,6,7" line.long 0x38 "MSS_RCM_MSS_PRU_ICSS_SYS_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x38 0.--2. "MSS_PRU_ICSS_SYS_CLK_GATE_GATED,Writing 3'b111 will gate clock for ICSSM_SYS" "0,1,2,3,4,5,6,7" group.long 0x3CC++0x2F line.long 0x0 "MSS_RCM_R5SS0_CORE0_GATE,Clock gating for individual CPU core." bitfld.long 0x0 0.--2. "R5SS0_CORE0_GATE_CLKGATE,Writing 3'b111 will gate clock to CORE0 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_R5SS1_CORE0_GATE,Clock gating for individual CPU core." bitfld.long 0x4 0.--2. "R5SS1_CORE0_GATE_CLKGATE,Writing 3'b111 will gate clock to CORE0 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_R5SS0_CORE1_GATE,Clock gating for individual CPU core." bitfld.long 0x8 0.--2. "R5SS0_CORE1_GATE_CLKGATE,Writing 3'b111 will gate clock to CORE1 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_R5SS1_CORE1_GATE,Clock gating for individual CPU core." bitfld.long 0xC 0.--2. "R5SS1_CORE1_GATE_CLKGATE,Writing 3'b111 will gate clock to CORE1 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_MSS_MCAN4_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x10 0.--2. "MSS_MCAN4_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_MSS_MCAN5_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x14 0.--2. "MSS_MCAN5_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_MSS_MCAN6_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x18 0.--2. "MSS_MCAN6_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_MSS_MCAN7_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x1C 0.--2. "MSS_MCAN7_CLK_GATE_GATED,Writing 3'b111 will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_RTI4_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x20 0.--2. "RTI4_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x24 "MSS_RCM_RTI5_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x24 0.--2. "RTI5_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x28 "MSS_RCM_RTI6_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x28 0.--2. "RTI6_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x2C "MSS_RCM_RTI7_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x2C 0.--2. "RTI7_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" rgroup.long 0x400++0x23 line.long 0x0 "MSS_RCM_MCAN0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "MCAN0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0x0 0.--7. 1. "MCAN0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0x4 "MSS_RCM_MCAN1_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "MCAN1_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0x4 0.--7. 1. "MCAN1_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0x8 "MSS_RCM_MCAN2_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x8 8.--15. 1. "MCAN2_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0x8 0.--7. 1. "MCAN2_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0xC "MSS_RCM_MCAN3_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0xC 8.--15. 1. "MCAN3_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0xC 0.--7. 1. "MCAN3_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0x10 "MSS_RCM_OSPI0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x10 8.--15. 1. "OSPI0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for OSPI" hexmask.long.byte 0x10 0.--7. 1. "OSPI0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for OSPI based on one hot encoding technique." line.long 0x14 "MSS_RCM_RTI0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x14 8.--15. 1. "RTI0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x14 0.--7. 1. "RTI0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x18 "MSS_RCM_RTI1_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x18 8.--15. 1. "RTI1_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x18 0.--7. 1. "RTI1_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x1C "MSS_RCM_RTI2_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x1C 8.--15. 1. "RTI2_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x1C 0.--7. 1. "RTI2_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x20 "MSS_RCM_RTI3_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x20 8.--15. 1. "RTI3_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x20 0.--7. 1. "RTI3_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." rgroup.long 0x428++0xF line.long 0x0 "MSS_RCM_WDT0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "WDT0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.long.byte 0x0 0.--7. 1. "WDT0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for WDT based on one hot encoding technique." line.long 0x4 "MSS_RCM_WDT1_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "WDT1_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.long.byte 0x4 0.--7. 1. "WDT1_CLK_STATUS_CLKINUSE,Status shows the source clock slected for WDT based on one hot encoding technique." line.long 0x8 "MSS_RCM_WDT2_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x8 8.--15. 1. "WDT2_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.long.byte 0x8 0.--7. 1. "WDT2_CLK_STATUS_CLKINUSE,Status shows the source clock slected for WDT based on one hot encoding technique." line.long 0xC "MSS_RCM_WDT3_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0xC 8.--15. 1. "WDT3_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.long.byte 0xC 0.--7. 1. "WDT3_CLK_STATUS_CLKINUSE,Status shows the source clock slected for WDT based on one hot encoding technique." rgroup.long 0x43C++0x1F line.long 0x0 "MSS_RCM_MCSPI0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "MCSPI0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x0 0.--7. 1. "MCSPI0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0x4 "MSS_RCM_MCSPI1_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "MCSPI1_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x4 0.--7. 1. "MCSPI1_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0x8 "MSS_RCM_MCSPI2_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x8 8.--15. 1. "MCSPI2_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x8 0.--7. 1. "MCSPI2_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0xC "MSS_RCM_MCSPI3_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0xC 8.--15. 1. "MCSPI3_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0xC 0.--7. 1. "MCSPI3_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0x10 "MSS_RCM_MCSPI4_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x10 8.--15. 1. "MCSPI4_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x10 0.--7. 1. "MCSPI4_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0x14 "MSS_RCM_MMC0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x14 8.--15. 1. "MMC0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for MMCSD" hexmask.long.byte 0x14 0.--7. 1. "MMC0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for MMCSD based on one hot encoding technique." line.long 0x18 "MSS_RCM_PRU_ICSS0_UART_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x18 8.--15. 1. "PRU_ICSS0_UART_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for ICSSM_UCLK" hexmask.long.byte 0x18 0.--7. 1. "PRU_ICSS0_UART_CLK_STATUS_CLKINUSE,Status shows the source clock slected for ICSSM_UCLK based on one hot encoding technique." line.long 0x1C "MSS_RCM_CPTS_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x1C 8.--15. 1. "CPTS_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for CPTS" hexmask.long.byte 0x1C 0.--7. 1. "CPTS_CLK_STATUS_CLKINUSE,Status shows the source clock slected for CPTS based on one hot encoding technique." rgroup.long 0x460++0x7 line.long 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "CONTROLSS_PLL_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for CONTROLSS_PLL" hexmask.long.byte 0x0 0.--7. 1. "CONTROLSS_PLL_CLK_STATUS_CLKINUSE,Status shows the source clock slected for CONTROLSS_PLL based on one hot encoding technique." line.long 0x4 "MSS_RCM_I2C_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "I2C_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for I2C" hexmask.long.byte 0x4 0.--7. 1. "I2C_CLK_STATUS_CLKINUSE,Status shows the source clock slected for I2C based on one hot encoding technique." rgroup.long 0x474++0x23 line.long 0x0 "MSS_RCM_LIN0_UART0_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "LIN0_UART0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.long.byte 0x0 0.--7. 1. "LIN0_UART0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding UART and LIN based on one hot encoding technique." line.long 0x4 "MSS_RCM_LIN1_UART1_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "LIN1_UART1_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.long.byte 0x4 0.--7. 1. "LIN1_UART1_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding UART and LIN based on one hot encoding technique." line.long 0x8 "MSS_RCM_LIN2_UART2_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x8 8.--15. 1. "LIN2_UART2_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.long.byte 0x8 0.--7. 1. "LIN2_UART2_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding UART and LIN based on one hot encoding technique." line.long 0xC "MSS_RCM_LIN3_UART3_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0xC 8.--15. 1. "LIN3_UART3_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.long.byte 0xC 0.--7. 1. "LIN3_UART3_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding UART and LIN based on one hot encoding technique." line.long 0x10 "MSS_RCM_LIN4_UART4_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x10 8.--15. 1. "LIN4_UART4_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.long.byte 0x10 0.--7. 1. "LIN4_UART4_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding UART and LIN based on one hot encoding technique." line.long 0x14 "MSS_RCM_LIN5_UART5_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x14 8.--15. 1. "LIN5_UART5_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.long.byte 0x14 0.--7. 1. "LIN5_UART5_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding UART and LIN based on one hot encoding technique." line.long 0x18 "MSS_RCM_RGMII_250_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x18 8.--15. 1. "RGMII_250_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for RGMII" line.long 0x1C "MSS_RCM_RGMII_50_CLK_STATUS,RGMII_50_CLK_STATUS." hexmask.long.byte 0x1C 8.--15. 1. "RGMII_50_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for MII100" line.long 0x20 "MSS_RCM_RGMII_5_CLK_STATUS,RGMII_5_CLK_STATUS." hexmask.long.byte 0x20 8.--15. 1. "RGMII_5_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for MII10" rgroup.long 0x49C++0x7 line.long 0x0 "MSS_RCM_MMC0_32K_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.word 0x0 8.--17. 1. "MMC0_32K_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for XTAL_32K" line.long 0x4 "MSS_RCM_TEMPSENSE_32K_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.word 0x4 8.--17. 1. "TEMPSENSE_32K_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for XTAL_32K" rgroup.long 0x4A8++0x2B line.long 0x0 "MSS_RCM_MCAN4_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "MCAN4_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0x0 0.--7. 1. "MCAN4_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0x4 "MSS_RCM_MCAN5_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "MCAN5_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0x4 0.--7. 1. "MCAN5_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0x8 "MSS_RCM_MCAN6_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x8 8.--15. 1. "MCAN6_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0x8 0.--7. 1. "MCAN6_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0xC "MSS_RCM_MCAN7_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0xC 8.--15. 1. "MCAN7_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.long.byte 0xC 0.--7. 1. "MCAN7_CLK_STATUS_CLKINUSE,Status shows the source clock slected for corresponding MCAN based on one hot encoding technique." line.long 0x10 "MSS_RCM_RTI4_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x10 8.--15. 1. "RTI4_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x10 0.--7. 1. "RTI4_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x14 "MSS_RCM_RTI5_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x14 8.--15. 1. "RTI5_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x14 0.--7. 1. "RTI5_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x18 "MSS_RCM_RTI6_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x18 8.--15. 1. "RTI6_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x18 0.--7. 1. "RTI6_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x1C "MSS_RCM_RTI7_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x1C 8.--15. 1. "RTI7_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.long.byte 0x1C 0.--7. 1. "RTI7_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding RTI based on one hot encoding technique." line.long 0x20 "MSS_RCM_MCSPI5_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x20 8.--15. 1. "MCSPI5_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x20 0.--7. 1. "MCSPI5_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0x24 "MSS_RCM_MCSPI6_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x24 8.--15. 1. "MCSPI6_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x24 0.--7. 1. "MCSPI6_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." line.long 0x28 "MSS_RCM_MCSPI7_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x28 8.--15. 1. "MCSPI7_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.long.byte 0x28 0.--7. 1. "MCSPI7_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Corresponding SPI based on one hot encoding technique." group.long 0x500++0xD3 line.long 0x0 "MSS_RCM_R5SS0_POR_RST_CTRL,R5SS POR Reset." bitfld.long 0x0 0.--2. "R5SS0_POR_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will assert por reset to R5SS Read is always 000" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_R5SS1_POR_RST_CTRL,R5SS POR Reset." bitfld.long 0x4 0.--2. "R5SS1_POR_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will assert por reset to R5SS Read is always 000" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_R5SS0_CORE0_GRST_CTRL,Core 0 Global Reset." bitfld.long 0x8 0.--2. "R5SS0_CORE0_GRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE0 and MSS_CORE0_VIM" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_R5SS1_CORE0_GRST_CTRL,Core 0 Global Reset." bitfld.long 0xC 0.--2. "R5SS1_CORE0_GRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE0 and MSS_CORE0_VIM" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_R5SS0_CORE1_GRST_CTRL,Core 1 Global Reset." bitfld.long 0x10 0.--2. "R5SS0_CORE1_GRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE1 and MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_R5SS1_CORE1_GRST_CTRL,Core 1 Global Reset." bitfld.long 0x14 0.--2. "R5SS1_CORE1_GRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE1 and MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_R5SS0_CORE0_LRST_CTRL,Core 0 Local Reset." bitfld.long 0x18 0.--2. "R5SS0_CORE0_LRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE0 only" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_R5SS1_CORE0_LRST_CTRL,Core 0 Local Reset." bitfld.long 0x1C 0.--2. "R5SS1_CORE0_LRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE0 only" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_R5SS0_CORE1_LRST_CTRL,Core 1 Local Reset." bitfld.long 0x20 0.--2. "R5SS0_CORE1_LRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE1 only" "0,1,2,3,4,5,6,7" line.long 0x24 "MSS_RCM_R5SS1_CORE1_LRST_CTRL,Core 1 Local Reset." bitfld.long 0x24 0.--2. "R5SS1_CORE1_LRST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:Writing 3'b111 will reset CORE1 only" "0,1,2,3,4,5,6,7" line.long 0x28 "MSS_RCM_R5SS0_VIM0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x28 0.--2. "R5SS0_VIM0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_CORE0_VIM Writing 3'b000 will deassert the reset" "0,1,2,3,4,5,6,7" line.long 0x2C "MSS_RCM_R5SS1_VIM0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x2C 0.--2. "R5SS1_VIM0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_CORE0_VIM Writing 3'b000 will deassert the reset" "0,1,2,3,4,5,6,7" line.long 0x30 "MSS_RCM_R5SS0_VIM1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x30 0.--2. "R5SS0_VIM1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" line.long 0x34 "MSS_RCM_R5SS1_VIM1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x34 0.--2. "R5SS1_VIM1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" line.long 0x38 "MSS_RCM_MCRC0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x38 0.--2. "MCRC0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MCRC" "0,1,2,3,4,5,6,7" line.long 0x3C "MSS_RCM_RTI0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x3C 0.--2. "RTI0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x40 "MSS_RCM_RTI1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x40 0.--2. "RTI1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x44 "MSS_RCM_RTI2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x44 0.--2. "RTI2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x48 "MSS_RCM_RTI3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x48 0.--2. "RTI3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x4C "MSS_RCM_WDT0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x4C 0.--2. "WDT0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset WDT" "0,1,2,3,4,5,6,7" line.long 0x50 "MSS_RCM_WDT1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x50 0.--2. "WDT1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset WDT" "0,1,2,3,4,5,6,7" line.long 0x54 "MSS_RCM_WDT2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x54 0.--2. "WDT2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset WDT" "0,1,2,3,4,5,6,7" line.long 0x58 "MSS_RCM_WDT3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x58 0.--2. "WDT3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset WDT" "0,1,2,3,4,5,6,7" line.long 0x5C "MSS_RCM_TOP_ESM_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x5C 0.--2. "TOP_ESM_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset ESM" "0,1,2,3,4,5,6,7" line.long 0x60 "MSS_RCM_DCC0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x60 0.--2. "DCC0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset DCC0" "0,1,2,3,4,5,6,7" line.long 0x64 "MSS_RCM_DCC1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x64 0.--2. "DCC1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset DCC1" "0,1,2,3,4,5,6,7" line.long 0x68 "MSS_RCM_DCC2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x68 0.--2. "DCC2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset DCC2" "0,1,2,3,4,5,6,7" line.long 0x6C "MSS_RCM_DCC3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x6C 0.--2. "DCC3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset DCC3" "0,1,2,3,4,5,6,7" line.long 0x70 "MSS_RCM_MCSPI0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x70 0.--2. "MCSPI0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x74 "MSS_RCM_MCSPI1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x74 0.--2. "MCSPI1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x78 "MSS_RCM_MCSPI2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x78 0.--2. "MCSPI2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x7C "MSS_RCM_MCSPI3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x7C 0.--2. "MCSPI3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x80 "MSS_RCM_MCSPI4_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x80 0.--2. "MCSPI4_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x84 "MSS_RCM_OSPI0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x84 0.--2. "OSPI0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset OSPI" "0,1,2,3,4,5,6,7" line.long 0x88 "MSS_RCM_MCAN0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x88 0.--2. "MCAN0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x8C "MSS_RCM_MCAN1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x8C 0.--2. "MCAN1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x90 "MSS_RCM_MCAN2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x90 0.--2. "MCAN2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x94 "MSS_RCM_MCAN3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x94 0.--2. "MCAN3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x98 "MSS_RCM_I2C0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x98 0.--2. "I2C0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding I2C" "0,1,2,3,4,5,6,7" line.long 0x9C "MSS_RCM_I2C1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x9C 0.--2. "I2C1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding I2C" "0,1,2,3,4,5,6,7" line.long 0xA0 "MSS_RCM_I2C2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xA0 0.--2. "I2C2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding I2C" "0,1,2,3,4,5,6,7" line.long 0xA4 "MSS_RCM_I2C3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xA4 0.--2. "I2C3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding I2C" "0,1,2,3,4,5,6,7" line.long 0xA8 "MSS_RCM_UART0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xA8 0.--2. "UART0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding UART instance" "0,1,2,3,4,5,6,7" line.long 0xAC "MSS_RCM_UART1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xAC 0.--2. "UART1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding UART instance" "0,1,2,3,4,5,6,7" line.long 0xB0 "MSS_RCM_UART2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xB0 0.--2. "UART2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding UART instance" "0,1,2,3,4,5,6,7" line.long 0xB4 "MSS_RCM_UART3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xB4 0.--2. "UART3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding UART instance" "0,1,2,3,4,5,6,7" line.long 0xB8 "MSS_RCM_UART4_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xB8 0.--2. "UART4_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding UART instance" "0,1,2,3,4,5,6,7" line.long 0xBC "MSS_RCM_UART5_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xBC 0.--2. "UART5_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding UART instance" "0,1,2,3,4,5,6,7" line.long 0xC0 "MSS_RCM_LIN0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xC0 0.--2. "LIN0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset LIN" "0,1,2,3,4,5,6,7" line.long 0xC4 "MSS_RCM_LIN1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xC4 0.--2. "LIN1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset LIN" "0,1,2,3,4,5,6,7" line.long 0xC8 "MSS_RCM_LIN2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xC8 0.--2. "LIN2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset LIN" "0,1,2,3,4,5,6,7" line.long 0xCC "MSS_RCM_LIN3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xCC 0.--2. "LIN3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset LIN" "0,1,2,3,4,5,6,7" line.long 0xD0 "MSS_RCM_LIN4_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xD0 0.--2. "LIN4_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset LIN" "0,1,2,3,4,5,6,7" group.long 0x5D8++0x27 line.long 0x0 "MSS_RCM_EDMA_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x0 12.--14. "EDMA_RST_CTRL_TPTCA1_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_TPTCA1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "EDMA_RST_CTRL_TPTCA0_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_TPTCA0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "EDMA_RST_CTRL_TPCCA_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_TPCCA" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "EDMA_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset EDMA" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_INFRA_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x4 0.--2. "INFRA_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS INFRA" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_CPSW_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x8 0.--2. "CPSW_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS CPSW" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_PRU_ICSS0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xC 0.--2. "PRU_ICSS0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS ICSSM" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_MMC0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x10 0.--2. "MMC0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MMCSD" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_GPIO0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x14 0.--2. "GPIO0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding GPIO" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_GPIO1_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x18 0.--2. "GPIO1_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding GPIO" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_GPIO2_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x1C 0.--2. "GPIO2_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding GPIO" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_GPIO3_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x20 0.--2. "GPIO3_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding GPIO" "0,1,2,3,4,5,6,7" line.long 0x24 "MSS_RCM_SPINLOCK0_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x24 0.--2. "SPINLOCK0_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset SPINLOCK" "0,1,2,3,4,5,6,7" group.long 0x604++0x3 line.long 0x0 "MSS_RCM_TEMPSENSE_32K_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x0 0.--2. "TEMPSENSE_32K_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset TEMPSENSE**Note: This bit will only be reset by PORz." "0,1,2,3,4,5,6,7" group.long 0x60C++0x2B line.long 0x0 "MSS_RCM_MCAN4_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x0 0.--2. "MCAN4_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_MCAN5_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x4 0.--2. "MCAN5_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_MCAN6_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x8 0.--2. "MCAN6_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_MCAN7_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0xC 0.--2. "MCAN7_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding MCAN" "0,1,2,3,4,5,6,7" line.long 0x10 "MSS_RCM_RTI4_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x10 0.--2. "RTI4_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x14 "MSS_RCM_RTI5_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x14 0.--2. "RTI5_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x18 "MSS_RCM_RTI6_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x18 0.--2. "RTI6_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x1C "MSS_RCM_RTI7_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x1C 0.--2. "RTI7_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset corresponding RTI" "0,1,2,3,4,5,6,7" line.long 0x20 "MSS_RCM_MCSPI5_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x20 0.--2. "MCSPI5_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x24 "MSS_RCM_MCSPI6_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x24 0.--2. "MCSPI6_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x28 "MSS_RCM_MCSPI7_RST_CTRL,This register is used to Reset respective IP." bitfld.long 0x28 0.--2. "MCSPI7_RST_CTRL_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset Corresponding SPI" "0,1,2,3,4,5,6,7" group.long 0x700++0xF line.long 0x0 "MSS_RCM_MSS_L2_BANK0_PD_CTRL,S/W control to Powers down the L2 Bank 0 and disconnect from Interconnect. AON AGOOD 0 or ISO =1 causes bus disconnect." bitfld.long 0x0 8.--10. "MSS_L2_BANK0_PD_CTRL_AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANK0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "MSS_L2_BANK0_PD_CTRL_AONIN,SW control for power signal 'AONIN' for MSS_L2_BANK0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MSS_L2_BANK0_PD_CTRL_ISO,SW control for power signal 'ISO' for MSS_L2_BANK0." "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_MSS_L2_BANK1_PD_CTRL,S/W control to Powers down the L2 Bank 1 and disconnect from Interconnect." bitfld.long 0x4 8.--10. "MSS_L2_BANK1_PD_CTRL_AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANK1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "MSS_L2_BANK1_PD_CTRL_AONIN,SW control for power signal 'AONIN' for MSS_L2_BANK1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "MSS_L2_BANK1_PD_CTRL_ISO,SW control for power signal 'ISO' for MSS_L2_BANK1" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_MSS_L2_BANK2_PD_CTRL,S/W control to Powers down the L2 Bank 2 and disconnect from Interconnect." bitfld.long 0x8 8.--10. "MSS_L2_BANK2_PD_CTRL_AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANK2" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "MSS_L2_BANK2_PD_CTRL_AONIN,SW control for power signal 'AONIN' for MSS_L2_BANK2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MSS_L2_BANK2_PD_CTRL_ISO,SW control for power signal 'ISO' for MSS_L2_BANK2" "0,1,2,3,4,5,6,7" line.long 0xC "MSS_RCM_MSS_L2_BANK3_PD_CTRL,S/W control to Powers down the L2 Bank 3 and disconnect from Interconnect." bitfld.long 0xC 8.--10. "MSS_L2_BANK3_PD_CTRL_AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANK3" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4.--6. "MSS_L2_BANK3_PD_CTRL_AONIN,SW control for power signal 'AONIN' for MSS_L2_BANK3" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "MSS_L2_BANK3_PD_CTRL_ISO,SW control for power signal 'ISO' for MSS_L2_BANK3" "0,1,2,3,4,5,6,7" rgroup.long 0x710++0xF line.long 0x0 "MSS_RCM_MSS_L2_BANK0_PD_STATUS,L2 Bank PD status. Pgood out observation." bitfld.long 0x0 1. "MSS_L2_BANK0_PD_STATUS_AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANK0" "0,1" bitfld.long 0x0 0. "MSS_L2_BANK0_PD_STATUS_AONOUT,SW status indicating the 'ponin' of MSS_L2_BANK0" "0,1" line.long 0x4 "MSS_RCM_MSS_L2_BANK1_PD_STATUS,L2 Bank PD status. Pgood out observation." bitfld.long 0x4 1. "MSS_L2_BANK1_PD_STATUS_AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANK1" "0,1" bitfld.long 0x4 0. "MSS_L2_BANK1_PD_STATUS_AONOUT,SW status indicating the 'ponin' of MSS_L2_BANK1" "0,1" line.long 0x8 "MSS_RCM_MSS_L2_BANK2_PD_STATUS,L2 Bank PD status. Pgood out observation." bitfld.long 0x8 1. "MSS_L2_BANK2_PD_STATUS_AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANK2" "0,1" bitfld.long 0x8 0. "MSS_L2_BANK2_PD_STATUS_AONOUT,SW status indicating the 'ponin' of MSS_L2_BANK2" "0,1" line.long 0xC "MSS_RCM_MSS_L2_BANK3_PD_STATUS,L2 Bank PD status. Pgood out observation." bitfld.long 0xC 1. "MSS_L2_BANK3_PD_STATUS_AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANK3" "0,1" bitfld.long 0xC 0. "MSS_L2_BANK3_PD_STATUS_AONOUT,SW status indicating the 'ponin' of MSS_L2_BANK3" "0,1" group.long 0x730++0x7 line.long 0x0 "MSS_RCM_L2OCRAM_BANK4_PD_CTRL,S/W control to Powers down the L2 Bank 4 and disconnect from Interconnect." bitfld.long 0x0 8.--10. "L2OCRAM_BANK4_PD_CTRL_AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANKE" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "L2OCRAM_BANK4_PD_CTRL_AONIN,SW control for power signal 'AONIN' for MSS_L2_BANKE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "L2OCRAM_BANK4_PD_CTRL_ISO,SW control for power signal 'ISO' for MSS_L2_BANKE" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_L2OCRAM_BANK5_PD_CTRL,S/W control to Powers down the L2 Bank 5 and disconnect from Interconnect." bitfld.long 0x4 8.--10. "L2OCRAM_BANK5_PD_CTRL_AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANKF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "L2OCRAM_BANK5_PD_CTRL_AONIN,SW control for power signal 'AONIN' for MSS_L2_BANKF" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "L2OCRAM_BANK5_PD_CTRL_ISO,SW control for power signal 'ISO' for MSS_L2_BANKF" "0,1,2,3,4,5,6,7" rgroup.long 0x738++0x7 line.long 0x0 "MSS_RCM_L2OCRAM_BANK4_PD_STATUS,L2 Bank PD status. Pgood out observation." bitfld.long 0x0 1. "L2OCRAM_BANK4_PD_STATUS_AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANKE" "0,1" bitfld.long 0x0 0. "L2OCRAM_BANK4_PD_STATUS_AONOUT,SW status indicating the 'ponin' of MSS_L2_BANKE" "0,1" line.long 0x4 "MSS_RCM_L2OCRAM_BANK5_PD_STATUS,L2 Bank PD status. Pgood out observation." bitfld.long 0x4 1. "L2OCRAM_BANK5_PD_STATUS_AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANKF" "0,1" bitfld.long 0x4 0. "L2OCRAM_BANK5_PD_STATUS_AONOUT,SW status indicating the 'ponin' of MSS_L2_BANKF" "0,1" group.long 0x800++0x3B line.long 0x0 "MSS_RCM_HSM_RTIA_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x0 0.--11. 1. "HSM_RTIA_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for HSM_Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values.." line.long 0x4 "MSS_RCM_HSM_WDT_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x4 0.--11. 1. "HSM_WDT_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for HSM_WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x8 "MSS_RCM_HSM_RTC_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x8 0.--11. 1. "HSM_RTC_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for HSM_RTC.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0xC "MSS_RCM_HSM_DMTA_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0xC 0.--11. 1. "HSM_DMTA_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for HSM_DMTA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x10 "MSS_RCM_HSM_DMTB_CLK_SRC_SEL,This Register is used for selecting the clock source for Corresponding root clock." hexmask.long.word 0x10 0.--11. 1. "HSM_DMTB_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for HSM_DMTB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Use the following values to select clk.." line.long 0x14 "MSS_RCM_HSM_RTI_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x14 0.--11. 1. "HSM_RTI_CLK_DIV_VAL_CLKDIVR,Divider value HSM RTI selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x18 "MSS_RCM_HSM_WDT_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x18 0.--11. 1. "HSM_WDT_CLK_DIV_VAL_CLKDIVR,Divider value HSM WDT selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x1C "MSS_RCM_HSM_RTC_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x1C 0.--11. 1. "HSM_RTC_CLK_DIV_VAL_CLKDIVR,Divider value HSM RTC selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x20 "MSS_RCM_HSM_DMTA_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x20 0.--11. 1. "HSM_DMTA_CLK_DIV_VAL_CLKDIVR,Divider value HSM DMTA selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x24 "MSS_RCM_HSM_DMTB_CLK_DIV_VAL,This Register is used to select the Divider value for respective clk." hexmask.long.word 0x24 0.--11. 1. "HSM_DMTB_CLK_DIV_VAL_CLKDIVR,Divider value HSM DMTB selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x28 "MSS_RCM_HSM_RTI_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x28 0.--2. "HSM_RTI_CLK_GATE_GATED,Writing 3'b111 will gate clock for HSM RTI" "0,1,2,3,4,5,6,7" line.long 0x2C "MSS_RCM_HSM_WDT_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x2C 0.--2. "HSM_WDT_CLK_GATE_GATED,Writing 3'b111 will gate clock for HSM WDT" "0,1,2,3,4,5,6,7" line.long 0x30 "MSS_RCM_HSM_RTC_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x30 0.--2. "HSM_RTC_CLK_GATE_GATED,Writing 3'b111 will gate clock for HSM RTC" "0,1,2,3,4,5,6,7" line.long 0x34 "MSS_RCM_HSM_DMTA_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x34 0.--2. "HSM_DMTA_CLK_GATE_GATED,Writing 3'b111 will gate clock for HSM DMTA" "0,1,2,3,4,5,6,7" line.long 0x38 "MSS_RCM_HSM_DMTB_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x38 0.--2. "HSM_DMTB_CLK_GATE_GATED,Writing 3'b111 will gate clock for HSM DMTB" "0,1,2,3,4,5,6,7" rgroup.long 0x83C++0x13 line.long 0x0 "MSS_RCM_HSM_RTI_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x0 8.--15. 1. "HSM_RTI_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for HSM_RTI" hexmask.long.byte 0x0 0.--7. 1. "HSM_RTI_CLK_STATUS_CLKINUSE,Status shows the source clock slected for HSM_RTI based on one hot encoding technique." line.long 0x4 "MSS_RCM_HSM_WDT_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x4 8.--15. 1. "HSM_WDT_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for HSM_WDT" hexmask.long.byte 0x4 0.--7. 1. "HSM_WDT_CLK_STATUS_CLKINUSE,Status shows the source clock slected for HSM_WDT based on one hot encoding technique." line.long 0x8 "MSS_RCM_HSM_RTC_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x8 8.--15. 1. "HSM_RTC_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for HSM_RTC" hexmask.long.byte 0x8 0.--7. 1. "HSM_RTC_CLK_STATUS_CLKINUSE,Status shows the source clock slected for HSM_RTC based on one hot encoding technique." line.long 0xC "MSS_RCM_HSM_DMTA_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0xC 8.--15. 1. "HSM_DMTA_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for HSM_DMTA" hexmask.long.byte 0xC 0.--7. 1. "HSM_DMTA_CLK_STATUS_CLKINUSE,Status shows the source clock slected for HSM_DMTA based on one hot encoding technique." line.long 0x10 "MSS_RCM_HSM_DMTB_CLK_STATUS,Clock source selection and Divider Value of respective clock." hexmask.long.byte 0x10 8.--15. 1. "HSM_DMTB_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for HSM_DMTB" hexmask.long.byte 0x10 0.--7. 1. "HSM_DMTB_CLK_STATUS_CLKINUSE,Status shows the source clock slected for HSM_DMTB based on one hot encoding technique." group.long 0x900++0xB line.long 0x0 "MSS_RCM_MCSPI5_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x0 0.--2. "MCSPI5_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x4 "MSS_RCM_MCSPI6_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x4 0.--2. "MCSPI6_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" line.long 0x8 "MSS_RCM_MCSPI7_CLK_GATE,This Register is used to enable clk gating for the respective clk." bitfld.long 0x8 0.--2. "MCSPI7_CLK_GATE_GATED,Writing 3'b111 will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" group.long 0x1008++0x1B line.long 0x0 "MSS_RCM_LOCK0_KICK0,- KICK0 component." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "MSS_RCM_LOCK0_KICK1,- KICK1 component." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "MSS_RCM_INTR_RAW_STATUS,Interrupt Raw Status/Set Register." bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "MSS_RCM_INTR_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear register." bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "MSS_RCM_INTR_ENABLE,Interrupt Enable register." bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "MSS_RCM_INTR_ENABLE_CLEAR,Interrupt Enable Clear register." bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "MSS_RCM_EOI,EOI register." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "MSS_RCM_FAULT_ADDRESS,Fault Address register." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "MSS_RCM_FAULT_TYPE_STATUS,Fault Type Status register." bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." line.long 0x8 "MSS_RCM_FAULT_ATTR_STATUS,Fault Attribute Status register." hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "MSS_RCM_FAULT_CLEAR,Fault Clear register." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree.end tree "OTTOCAL" base ad:0x0 tree "OTTOCAL0" base ad:0x502E0000 group.word 0x42++0x1 line.word 0x0 "OTTOCAL_HRPWR,HRPWM Power Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits [only available on ePWM1] 0:Disables MEP calibration logic in the HRPWM and reduces power consumption. 1:Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" group.word 0x4C++0x1 line.word 0x0 "OTTOCAL_HRMSTEP,HRPWM MEP Step Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled [HRCNFG[AUTOCONV] = 1] This 8-bit field contains the MEP_ScaleFactor [number of MEP steps per coarse steps] used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree "OTTOCAL1" base ad:0x502E1000 group.word 0x42++0x1 line.word 0x0 "OTTOCAL_HRPWR,HRPWM Power Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits [only available on ePWM1] 0:Disables MEP calibration logic in the HRPWM and reduces power consumption. 1:Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" group.word 0x4C++0x1 line.word 0x0 "OTTOCAL_HRMSTEP,HRPWM MEP Step Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled [HRCNFG[AUTOCONV] = 1] This 8-bit field contains the MEP_ScaleFactor [number of MEP steps per coarse steps] used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree "OTTOCAL2" base ad:0x502E2000 group.word 0x42++0x1 line.word 0x0 "OTTOCAL_HRPWR,HRPWM Power Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits [only available on ePWM1] 0:Disables MEP calibration logic in the HRPWM and reduces power consumption. 1:Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" group.word 0x4C++0x1 line.word 0x0 "OTTOCAL_HRMSTEP,HRPWM MEP Step Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled [HRCNFG[AUTOCONV] = 1] This 8-bit field contains the MEP_ScaleFactor [number of MEP steps per coarse steps] used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree "OTTOCAL3" base ad:0x502E3000 group.word 0x42++0x1 line.word 0x0 "OTTOCAL_HRPWR,HRPWM Power Register This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits [only available on ePWM1] 0:Disables MEP calibration logic in the HRPWM and reduces power consumption. 1:Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" group.word 0x4C++0x1 line.word 0x0 "OTTOCAL_HRMSTEP,HRPWM MEP Step Register This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values." hexmask.word.byte 0x0 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled [HRCNFG[AUTOCONV] = 1] This 8-bit field contains the MEP_ScaleFactor [number of MEP steps per coarse steps] used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree.end tree "PBIST0" base ad:0x53300000 group.word 0x164++0x1 line.word 0x0 "PBIST_DLR,Datalogger 0 ." hexmask.word.byte 0x0 8.--15. 1. "DLR1,Datalogger Register[8] : Reserevd[9] : Default Testing Mode. When in this mode ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config write to both this bit and bit [2] ofthe Datalogger Register.." hexmask.word.byte 0x0 0.--7. 1. "DLR0,Datalogger Register[1:0] : Reserved[2] : ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that arestored in the PBIST ROM[3] : Do not change this bit from its default value of 1[4] : Config access.." group.byte 0x180++0x0 line.byte 0x0 "PBIST_PACT,Pbist Active." bitfld.byte 0x0 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register[0]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is usedas the clock gate enable. As long as this bit is 0 any access to PBIST will not go.." "0: Disable internal PBIST clocksValue,1: Enable internal PBIST clocks" group.byte 0x184++0x0 line.byte 0x0 "PBIST_ID,PBIST ID." hexmask.byte 0x0 0.--4. 1. "PBIST_ID,PBIST ID.This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. The value of this register does not effect the functionality of the CPU interface." rgroup.byte 0x190++0x0 line.byte 0x0 "PBIST_FSFR0,Fail status fail - port 0 ." bitfld.byte 0x0 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test.Value 0 = No failure occurredValue 1 = Indicates a failure" "0: No failure occurredValue,1: Indicates a failure" rgroup.byte 0x194++0x0 line.byte 0x0 "PBIST_FSFR1,Fail status fail - port 1" bitfld.byte 0x0 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test.Value 0 = No failure occurredValue 1 = Indicates a failure" "0: No failure occurredValue,1: Indicates a failure" rgroup.byte 0x198++0x0 line.byte 0x0 "PBIST_FSRCR0,Fail Count fail - port 0 ." hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test. The PBISTcontroller stops executing the memory self-test whenever a failure occurs in any memory instance for anyof the.." rgroup.byte 0x19C++0x0 line.byte 0x0 "PBIST_FSRCR1,Fail Count fail - port 1" hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR1,Fail Status Count - Port 1These registers keep count of the number of failures observed during the memory self-test. The PBISTcontroller stops executing the memory self-test whenever a failure occurs in any memory instance for anyof the test.." group.byte 0x1C0++0x0 line.byte 0x0 "PBIST_ROM,Rom Mask ." bitfld.byte 0x0 0.--1. "PBIST_ROM,Rom Mask .This two-bit register sets appropriate ROM access modes for the PBIST controller.Value 0h= No information is used from ROMValue1h= Only RAM Group information from ROMVaule2h= Only Algorithm information from ROMValue3h= Both Algorithm.." "0,1,2,3" group.long 0x1C4++0xB line.long 0x0 "PBIST_ALGO,ROM Algorithm Mask 0" hexmask.long.byte 0x0 24.--31. 1. "ALGO3,This register is used to indicate the algorithm[s] to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." hexmask.long.byte 0x0 16.--23. 1. "ALGO2,This register is used to indicate the algorithm[s] to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." hexmask.long.byte 0x0 8.--15. 1. "ALGO1,This register is used to indicate the algorithm[s] to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." hexmask.long.byte 0x0 0.--7. 1. "ALGO0,This register is used to indicate the algorithm[s] to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." line.long 0x4 "PBIST_RINFOL,RAM Info Mask Lower 0" hexmask.long.byte 0x4 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x4 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x4 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x4 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." line.long 0x8 "PBIST_RINFOU,RAM Info Mask Upper 0" hexmask.long.byte 0x8 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x8 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x8 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x8 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." tree.end tree "R5SS" base ad:0x0 tree "R5SS0" tree "R5SS0_CCMR" base ad:0x53210000 group.long 0x0++0x17 line.long 0x0 "CCMR_CCMSR1,CPU Compare Status Register." bitfld.long 0x0 16. "CMPE1,Compare Error0 = CPU signals are identical1= CPU signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x0 8. "STC1,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x0 1. "STET1,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x0 0. "STE1,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x4 "CCMR_CCMKEYR1,CPU Compare Key Register." hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" line.long 0x8 "CCMR_CCMSR2,VIM Compare Status Register." bitfld.long 0x8 16. "CMPE2,Compare Error0 = VIM signals are identical1= VIM signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x8 8. "STC2,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x8 1. "STET2,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" bitfld.long 0x8 0. "STE2,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0xC "CCMR_CCMKEYR2,VIM Compare Key Register." hexmask.long.byte 0xC 0.--3. 1. "MKEY2,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" line.long 0x10 "CCMR_CCMSR3,Inactivity Monitor Status Register." bitfld.long 0x10 16. "CMPE3,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x10 8. "STC3,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x10 1. "STET3,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x10 0. "STE3,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x14 "CCMR_CCMKEYR3,Inactivity Monitor Key Register." hexmask.long.byte 0x14 0.--3. 1. "MKEY3,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" rgroup.long 0x18++0x3 line.long 0x0 "CCMR_CCMPOLCNTRL,CPU Compare Polarity Control Register." hexmask.long.byte 0x0 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode. User and privilege mode read = Returns current value of the POL INVPrivilege mode write = Update the values of POL INV" group.long 0x2C++0xF line.long 0x0 "CCMR_CCMSR5,TMU Compare Status Register." bitfld.long 0x0 16. "CMPE5,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x0 8. "STC5,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x0 1. "STET5,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x0 0. "STE5,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x4 "CCMR_CCMKEYR5,TMU Compare Key Register." hexmask.long.byte 0x4 0.--3. 1. "MKEY5,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" line.long 0x8 "CCMR_CCMSR6,RL2 Compare Status Register." bitfld.long 0x8 16. "CMPE6,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x8 8. "STC6,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x8 1. "STET6,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x8 0. "STE6,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0xC "CCMR_CCMKEYR6,RL2 Compare Key Register." hexmask.long.byte 0xC 0.--3. 1. "MKEY6,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" tree.end base ad:0x0 tree "R5SS0_DCACHE" tree "R5SS0_DCACHE_CORE0" base ad:0x74800000 group.long 0x0++0x3 line.long 0x0 "DCACHE_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "DCACHE_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree "R5SS0_DCACHE_CORE1" base ad:0x75800000 group.long 0x0++0x3 line.long 0x0 "DCACHE_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "DCACHE_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree.end tree "R5SS0_ECC_AGG" tree "R5SS0_ECC_AGG_CORE0" base ad:0x53000000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_CORE0_AGGR_REVISION,Revision parameters register. The Revision Register contains the major and minor revisions for the ECC aggregator module. It does notsupport byte accesses." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_CORE0_ECC_VECTOR,ECC Vector Register. ECC RAM ID to select which ECC RAM to control or read status from." rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x7 line.long 0x0 "ECC_AGG_CORE0_MISC_STATUS,Misc Statu register. It contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x4 "ECC_AGG_CORE0_ECC_WRAP_REVISION,Revision parameters." bitfld.long 0x4 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x4 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x4 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor version" group.long 0x14++0xF line.long 0x0 "ECC_AGG_CORE0_CONTROL,ECC Control Register." bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" newline bitfld.long 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" newline bitfld.long 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x4 "ECC_AGG_CORE0_ERROR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_AGG_CORE0_ERROR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" newline hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_AGG_CORE0_ERROR_STATUS1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" newline bitfld.long 0xC 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0xC 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" newline bitfld.long 0xC 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0xC 4. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_CORE0_ERROR_STATUS2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_AGG_CORE0_ERROR_STATUS3,ECC Error Status3 Register." bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" newline bitfld.long 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.long 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_CORE0_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_CORE0_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU0_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_CORE0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_CORE0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_CORE0_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_CORE0_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU0_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_CORE0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_CORE0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGG_CORE0_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGG_CORE0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGG_CORE0_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. 2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 0x0: No timeout errors have occurred 0x1: 1 timeout erro has occurred 0x2: 2 timeout error has occurred.." "0: No timeout errors have occurred,1: 1 timeout erro has occurred,2: 2 timeout error has occurred,3: 3 or more timeout errors have occurred A write.." newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3 3 or.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred 0x3 3 or more parity..,?" line.long 0xC "ECC_AGG_CORE0_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. 0x0: No timeout errors have occurred 0x1: 1 timeout error has occurred 0x2: 2 timeout error has occurred 0x3: 3 or more timeout error have occurred A write of a non-zero value to this register.." "0: No timeout errors have occurred,1: 1 timeout error has occurred,2: 2 timeout error has occurred,3: 3 or more timeout error have occurred A write of.." newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3: 3 or more parity error have occurred A write of a non-zero value to this register decrements that.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred,3: 3 or more parity error have occurred A write of.." tree.end tree "R5SS0_ECC_AGG_CORE1" base ad:0x53003000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_CORE1_AGGR_REVISION,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_CORE1_ECC_VECTOR,ECC Vector Register." rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x7 line.long 0x0 "ECC_AGG_CORE1_MISC_STATUS,Misc Status." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x4 "ECC_AGG_CORE1_ECC_WRAP_REVISION,Revision parameters." bitfld.long 0x4 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x4 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x4 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor version" group.long 0x14++0xF line.long 0x0 "ECC_AGG_CORE1_CONTROL,ECC Control Register." bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" newline bitfld.long 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" newline bitfld.long 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x4 "ECC_AGG_CORE1_ERROR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_AGG_CORE1_ERROR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" newline hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_AGG_CORE1_ERROR_STATUS1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" newline bitfld.long 0xC 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0xC 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" newline bitfld.long 0xC 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0xC 4. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_CORE1_ERROR_STATUS2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_AGG_CORE1_ERROR_STATUS3,ECC Error Status3 Register." bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" newline bitfld.long 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.long 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_CORE1_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register Write of 1 to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. The bit is self clearing and will be read as a zero." "0,1" line.long 0x4 "ECC_AGG_CORE1_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU1_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_CORE1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_CORE1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_CORE1_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register Write of 1 to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. The bit is self clearing and will be read as a zero." "0,1" line.long 0x4 "ECC_AGG_CORE1_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU1_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_CORE1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_CORE1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGG_CORE1_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGG_CORE1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGG_CORE1_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. 2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 0x0: No timeout errors have occurred 0x1: 1 timeout erro has occurred 0x2: 2 timeout error has occurred.." "0: No timeout errors have occurred,1: 1 timeout erro has occurred,2: 2 timeout error has occurred,3: 3 or more timeout errors have occurred A write.." newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3 3 or.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred 0x3 3 or more parity..,?" line.long 0xC "ECC_AGG_CORE1_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. 0x0: No timeout errors have occurred 0x1: 1 timeout error has occurred 0x2: 2 timeout error has occurred 0x3: 3 or more timeout error have occurred A write of a non-zero value to this register.." "0: No timeout errors have occurred,1: 1 timeout error has occurred,2: 2 timeout error has occurred,3: 3 or more timeout error have occurred A write of.." newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3: 3 or more parity error have occurred A write of a non-zero value to this register decrements that.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred,3: 3 or more parity error have occurred A write of.." tree.end tree.end tree "R5SS0_ICACHE" tree "R5SS0_ICACHE_CORE0" base ad:0x74000000 group.long 0x0++0x3 line.long 0x0 "ICACHE_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "ICACHE_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree "R5SS0_ICACHE_CORE1" base ad:0x75000000 group.long 0x0++0x3 line.long 0x0 "ICACHE_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "ICACHE_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree.end tree "R5SS0_STC" base ad:0x53500000 group.long 0x0++0xB line.long 0x0 "STC_STCGCR0,Self test Global control Reg0. *NOT BYTE ACCESSIBLE." hexmask.long.word 0x0 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run [RWP - Read Priviledge Mode Write only]Count of intervals that need to be covered for a specific selftest run.The selftest controller sends out complete indication once it runs all of the intervals.." newline hexmask.long.byte 0x0 11.--15. 1. "NU0,Reserved bits" newline bitfld.long 0x0 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock [RWP - Read Priviledge Mode Write only]Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock [RWP - Read Priviledge Mode Write only]. *NOT BYTE ACCESSIBLEIdle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "RS_CNT_B1,Restart/Continue or preload [RWP - Read Priviledge Mode Write only]This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval. This bit.." "0: Continue NSTC run from previous interval01 =..,?,?,?" line.long 0x4 "STC_STCGCR1,Self test Global control Reg1." hexmask.long.tbyte 0x4 12.--31. 1. "NU2,Reserved bits" newline hexmask.long.byte 0x4 8.--11. 1. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test [RWP - Read Priviledge Mode Write only]Select the Segment0 CORE for Self -Test0001= Select CORE for selftestOther = CORE not selected." newline rbitfld.long 0x4 7. "NU3,Reserved bits" "0,1" newline bitfld.long 0x4 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal [RWP - Read Priviledge Mode Write only]This bit is used to configure the codec in spread / X-OR mode.1 = Spread mode0 = XOR mode" "?,1: Spread mode0 = XOR mode" newline bitfld.long 0x4 5. "LP_SCAN_MODE,LP scan mode [RWP - Read Priviledge Mode Write only]This bit is used to decide the scan configuration:1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode." "0: Operates in Normal Scan Mode,1: Operates in Low Power Scan Mode" newline bitfld.long 0x4 4. "ROM_ACCESS_INV,Rom access inversion mode [RWP - Read Priviledge Mode Write only]- NOT SUPPORTED" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "ST_ENA_B4,Self test enable key [RWP - Read Priviledge Mode Write only]1010= Self test run enabled All values other than1010= Self test run disabled" line.long 0x8 "STC_STCTPR,Time out counter preload register." hexmask.long 0x8 0.--31. 1. "TO_PRELOAD,Self test time out preload [RWP - Read Priviledge Mode Write only]This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is a.." rgroup.long 0xC++0xF line.long 0x0 "STC_STC_CADDR,Current Address register for CORE1." hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE1This register reflects the current ROM address [for micro code load] accessed during selftest for CORE1 in of case segment0 and all the remaining segmentsn where n = 1 to 3]." line.long 0x4 "STC_STCCICR,Current Interval count register." hexmask.long.word 0x4 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well. This field is applicable only for Segment 0." newline hexmask.long.word 0x4 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1This specifies the Last executed Interval number of a self-test run." line.long 0x8 "STC_STCGSTAT,Global Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "NU4,Reserved bits" newline hexmask.long.byte 0x8 8.--11. 1. "ST_ACTIVE,Tells whether self test is currently active or not.1010 = Self test is activeOthers = SelfTest is not activeOnce the self-test completes and ST_ENA_B4 key is cleared this field will reflect the inactive value." newline hexmask.long.byte 0x8 2.--7. 1. "NU5,Reserved bits" newline bitfld.long 0x8 1. "TEST_FAIL,Test_fail flag [RCP - Read Clear on Writing in Priviledge Mode]0 = Self test run has not failed1 = SelfTest run has failed. Write Clear." "0,1" newline bitfld.long 0x8 0. "TEST_DONE,Test_done_flag [RCP - Read Clear on Writing in Priviledge Mode]0 = Not completed1 = SelfTest run Completed" "0,1" line.long 0xC "STC_STCFSTAT,Fail Status Register." hexmask.long 0xC 5.--31. 1. "NU6,Reserved bits" newline bitfld.long 0xC 3.--4. "FSEG_ID,Failed Segment ID [RCP - Read Clear on Writing in Priviledge Mode]This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur.00 = Failure on Segment 001 = Failure on Segment 110.." "0: Failure on Segment,1: Failure on Segment,?,?" newline bitfld.long 0xC 2. "TO_ER_B1,Tells whether self test failed because of time out error [RCP - Read Clear on Writing in Priviledge Mode]0 = No time out error occurred1 = SelfTest run failed due to a timeout error" "0,1" newline bitfld.long 0xC 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode [RCP - Read Clear on Writing in Priviledge Mode]0 = No MISR mismatch for CORE21 = Self test run failed due to MISR mismatch for CORE2" "0,1" newline bitfld.long 0xC 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 [RCP - Read Clear on Writing in Priviledge Mode]Applicable to all segments.0 = No MISR mismatch for CORE11 = Self test run failed due to MISR mismatch for CORE1" "0: No MISR mismatch for CORE11 = Self test run..,?" group.long 0x1C++0x3 line.long 0x0 "STC_STCSCSCR,Signature compare Self Check Register." hexmask.long 0x0 5.--31. 1. "NU7,Reserved bits" newline bitfld.long 0x0 4. "FAULT_INS_B1,Fault Insertion bit [RWP - Read Priviledge Mode Write only]0 = No fault insertion.1 = Inserts fault in the logic under test which will make signature compare fail. This feature is used as diagnostic check of the STC IP." "?,1: Inserts fault in the logic under test which will.." newline hexmask.long.byte 0x0 0.--3. 1. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable [RWP - Read Priviledge Mode Write only]1010 = Signature compare logic Self Check is enabledAll values other than1010 = Signature compare logic Self Check is disabled" rgroup.long 0x20++0x3 line.long 0x0 "STC_STC_CADDR2,Current Address register for CORE2." hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE2This register reflects the current ROM address[for micro code load] accessed during selftest for CORE2 in of case segment0." group.long 0x24++0x17 line.long 0x0 "STC_STC_CLKDIV,Clock Divider Register." hexmask.long.byte 0x0 27.--31. 1. "NU8,Reserved bits" newline bitfld.long 0x0 24.--26. "CLKDIV0,Clock division for Seg0 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "NU9,Reserved bits" newline bitfld.long 0x0 16.--18. "CLKDIV1,Clock division for Seg1 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "NU10,Reserved bits" newline bitfld.long 0x0 8.--10. "CLKDIV2,Clock division for Seg2 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "NU11,Reserved bits" newline bitfld.long 0x0 0.--2. "CLKDIV3,Clock division for Seg3 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7" line.long 0x4 "STC_STC_SEGPLR,Segment 1st interval Preload Register." hexmask.long 0x4 2.--31. 1. "NU12,Reserved bits" newline bitfld.long 0x4 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started [RWP - Read Priviledge Mode Write only]This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter. The 1st address of each.." "?,1: Preload the address of the 1st interval of..,?,?" line.long 0x8 "STC_SEG0_START_ADDR,ROM Start address for Segment0." hexmask.long.word 0x8 20.--31. 1. "NU13,Reserved bits" newline hexmask.long.tbyte 0x8 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." line.long 0xC "STC_SEG1_START_ADDR,ROM Start address for Segment1." hexmask.long.word 0xC 20.--31. 1. "NU14,Reserved bits" newline hexmask.long.tbyte 0xC 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." line.long 0x10 "STC_SEG2_START_ADDR,ROM Start address for Segment2." hexmask.long.word 0x10 20.--31. 1. "NU15,Reserved bits" newline hexmask.long.tbyte 0x10 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." line.long 0x14 "STC_SEG3_START_ADDR,ROM Start address for Segment3." hexmask.long.word 0x14 20.--31. 1. "NU16,Reserved bits" newline hexmask.long.tbyte 0x14 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." rgroup.long 0x3C++0xDF line.long 0x0 "STC_CORE1_CURMISR_0,Holds the MISR signature for CORE1." hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4 "STC_CORE1_CURMISR_1,Holds the MISR signature for CORE1." hexmask.long 0x4 0.--31. 1. "C1MISR1,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x8 "STC_CORE1_CURMISR_2,Holds the MISR signature for CORE1." hexmask.long 0x8 0.--31. 1. "C1MISR2,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0xC "STC_CORE1_CURMISR_3,Holds the MISR signature for CORE1." hexmask.long 0xC 0.--31. 1. "C1MISR3,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x10 "STC_CORE1_CURMISR_4,Holds the MISR signature for CORE1." hexmask.long 0x10 0.--31. 1. "C1MISR4,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x14 "STC_CORE1_CURMISR_5,Holds the MISR signature for CORE1." hexmask.long 0x14 0.--31. 1. "C1MISR5,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x18 "STC_CORE1_CURMISR_6,Holds the MISR signature for CORE1." hexmask.long 0x18 0.--31. 1. "C1MISR6,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x1C "STC_CORE1_CURMISR_7,Holds the MISR signature for CORE1." hexmask.long 0x1C 0.--31. 1. "C1MISR7,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x20 "STC_CORE1_CURMISR_8,Holds the MISR signature for CORE1." hexmask.long 0x20 0.--31. 1. "C1MISR8,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x24 "STC_CORE1_CURMISR_9,Holds the MISR signature for CORE1." hexmask.long 0x24 0.--31. 1. "C1MISR9,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x28 "STC_CORE1_CURMISR_10,Holds the MISR signature for CORE1." hexmask.long 0x28 0.--31. 1. "C1MISR10,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x2C "STC_CORE1_CURMISR_11,Holds the MISR signature for CORE1." hexmask.long 0x2C 0.--31. 1. "C1MISR11,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x30 "STC_CORE1_CURMISR_12,Holds the MISR signature for CORE1." hexmask.long 0x30 0.--31. 1. "C1MISR12,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x34 "STC_CORE1_CURMISR_13,Holds the MISR signature for CORE1." hexmask.long 0x34 0.--31. 1. "C1MISR13,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x38 "STC_CORE1_CURMISR_14,Holds the MISR signature for CORE1." hexmask.long 0x38 0.--31. 1. "C1MISR14,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x3C "STC_CORE1_CURMISR_15,Holds the MISR signature for CORE1." hexmask.long 0x3C 0.--31. 1. "C1MISR15,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x40 "STC_CORE1_CURMISR_16,Holds the MISR signature for CORE1." hexmask.long 0x40 0.--31. 1. "C1MISR16,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x44 "STC_CORE1_CURMISR_17,Holds the MISR signature for CORE1." hexmask.long 0x44 0.--31. 1. "C1MISR17,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x48 "STC_CORE1_CURMISR_18,Holds the MISR signature for CORE1." hexmask.long 0x48 0.--31. 1. "C1MISR18,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4C "STC_CORE1_CURMISR_19,Holds the MISR signature for CORE1." hexmask.long 0x4C 0.--31. 1. "C1MISR19,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x50 "STC_CORE1_CURMISR_20,Holds the MISR signature for CORE1." hexmask.long 0x50 0.--31. 1. "C1MISR20,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x54 "STC_CORE1_CURMISR_21,Holds the MISR signature for CORE1." hexmask.long 0x54 0.--31. 1. "C1MISR21,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x58 "STC_CORE1_CURMISR_22,Holds the MISR signature for CORE1." hexmask.long 0x58 0.--31. 1. "C1MISR22,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x5C "STC_CORE1_CURMISR_23,Holds the MISR signature for CORE1." hexmask.long 0x5C 0.--31. 1. "C1MISR23,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x60 "STC_CORE1_CURMISR_24,Holds the MISR signature for CORE1." hexmask.long 0x60 0.--31. 1. "C1MISR24,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x64 "STC_CORE1_CURMISR_25,Holds the MISR signature for CORE1." hexmask.long 0x64 0.--31. 1. "C1MISR25,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x68 "STC_CORE1_CURMISR_26,Holds the MISR signature for CORE1." hexmask.long 0x68 0.--31. 1. "C1MISR26,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x6C "STC_CORE1_CURMISR_27,Holds the MISR signature for CORE1." hexmask.long 0x6C 0.--31. 1. "C1MISR27,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x70 "STC_CORE2_CURMISR_0,Holds the MISR signature for CORE2." hexmask.long 0x70 0.--31. 1. "C2MISR0,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x74 "STC_CORE2_CURMISR_1,Holds the MISR signature for CORE2." hexmask.long 0x74 0.--31. 1. "C2MISR1,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x78 "STC_CORE2_CURMISR_2,Holds the MISR signature for CORE2." hexmask.long 0x78 0.--31. 1. "C2MISR2,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x7C "STC_CORE2_CURMISR_3,Holds the MISR signature for CORE2." hexmask.long 0x7C 0.--31. 1. "C2MISR3,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x80 "STC_CORE2_CURMISR_4,Holds the MISR signature for CORE2." hexmask.long 0x80 0.--31. 1. "C2MISR4,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x84 "STC_CORE2_CURMISR_5,Holds the MISR signature for CORE2." hexmask.long 0x84 0.--31. 1. "C2MISR5,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x88 "STC_CORE2_CURMISR_6,Holds the MISR signature for CORE2." hexmask.long 0x88 0.--31. 1. "C2MISR6,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x8C "STC_CORE2_CURMISR_7,Holds the MISR signature for CORE2." hexmask.long 0x8C 0.--31. 1. "C2MISR7,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x90 "STC_CORE2_CURMISR_8,Holds the MISR signature for CORE2." hexmask.long 0x90 0.--31. 1. "C2MISR8,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x94 "STC_CORE2_CURMISR_9,Holds the MISR signature for CORE2." hexmask.long 0x94 0.--31. 1. "C2MISR9,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x98 "STC_CORE2_CURMISR_10,Holds the MISR signature for CORE2." hexmask.long 0x98 0.--31. 1. "C2MISR10,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x9C "STC_CORE2_CURMISR_11,Holds the MISR signature for CORE2." hexmask.long 0x9C 0.--31. 1. "C2MISR11,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA0 "STC_CORE2_CURMISR_12,Holds the MISR signature for CORE2." hexmask.long 0xA0 0.--31. 1. "C2MISR12,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA4 "STC_CORE2_CURMISR_13,Holds the MISR signature for CORE2." hexmask.long 0xA4 0.--31. 1. "C2MISR13,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA8 "STC_CORE2_CURMISR_14,Holds the MISR signature for CORE2." hexmask.long 0xA8 0.--31. 1. "C2MISR14,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xAC "STC_CORE2_CURMISR_15,Holds the MISR signature for CORE2." hexmask.long 0xAC 0.--31. 1. "C2MISR15,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB0 "STC_CORE2_CURMISR_16,Holds the MISR signature for CORE2." hexmask.long 0xB0 0.--31. 1. "C2MISR16,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB4 "STC_CORE2_CURMISR_17,Holds the MISR signature for CORE2." hexmask.long 0xB4 0.--31. 1. "C2MISR17,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB8 "STC_CORE2_CURMISR_18,Holds the MISR signature for CORE2." hexmask.long 0xB8 0.--31. 1. "C2MISR18,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xBC "STC_CORE2_CURMISR_19,Holds the MISR signature for CORE2." hexmask.long 0xBC 0.--31. 1. "C2MISR19,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC0 "STC_CORE2_CURMISR_20,Holds the MISR signature for CORE2." hexmask.long 0xC0 0.--31. 1. "C2MISR20,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC4 "STC_CORE2_CURMISR_21,Holds the MISR signature for CORE2." hexmask.long 0xC4 0.--31. 1. "C2MISR21,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC8 "STC_CORE2_CURMISR_22,Holds the MISR signature for CORE2." hexmask.long 0xC8 0.--31. 1. "C2MISR22,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xCC "STC_CORE2_CURMISR_23,Holds the MISR signature for CORE2." hexmask.long 0xCC 0.--31. 1. "C2MISR23,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD0 "STC_CORE2_CURMISR_24,Holds the MISR signature for CORE2." hexmask.long 0xD0 0.--31. 1. "C2MISR24,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD4 "STC_CORE2_CURMISR_25,Holds the MISR signature for CORE2." hexmask.long 0xD4 0.--31. 1. "C2MISR25,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD8 "STC_CORE2_CURMISR_26,Holds the MISR signature for CORE2." hexmask.long 0xD8 0.--31. 1. "C2MISR26,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xDC "STC_CORE2_CURMISR_27,Holds the MISR signature for CORE2." hexmask.long 0xDC 0.--31. 1. "C2MISR27,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." tree.end base ad:0x0 tree "R5SS0_TCMA" tree "R5SS0_TCMA_CORE0" base ad:0x78000000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0x27FFC++0x3 line.long 0x0 "TCMA_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS0_TCMA_CORE0_RAM" base ad:0x20000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE0_RAM_START" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "TCMA_CORE0_RAM_END" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end base ad:0x0 tree "R5SS0_TCMA_CORE0_ROM" rgroup.long 0x0++0x3 line.long 0x0 "TCMA_CORE0_ROM_START" hexmask.long 0x0 0.--31. 1. "ROM_START,ROM start address of master sub system tcma" rgroup.long 0x1FFFC++0x3 line.long 0x0 "TCMA_CORE0_ROM_END" hexmask.long 0x0 0.--31. 1. "ROM_END,ROM end address of master sub system tcma" tree.end tree "R5SS0_TCMA_CORE1" base ad:0x78200000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0x7FFC++0x3 line.long 0x0 "TCMA_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS0_TCMA_CORE1_RAM" base ad:0x20000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE1_RAM_START" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "TCMA_CORE1_RAM_END" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end tree.end tree "R5SS0_TCMB" tree "R5SS0_TCMB_CORE0" base ad:0x78100000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x2FFFC++0x3 line.long 0x0 "TCMB_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS0_TCMB_CORE0_RAM" base ad:0x80000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE0_RAM_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x17FFC++0x3 line.long 0x0 "TCMB_CORE0_RAM_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS0_TCMB_CORE1" base ad:0x78300000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x17FFC++0x3 line.long 0x0 "TCMB_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS0_TCMB_CORE1_RAM" base ad:0x80000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE1_RAM_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x17FFC++0x3 line.long 0x0 "TCMB_CORE1_RAM_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree.end tree "R5SS0_TMU" tree "R5SS0_TMU_0" base ad:0x60000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_0_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_0_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0" group.long 0x48++0x3 line.long 0x0 "TMU_0_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_0_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_0_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_0_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_0_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_0_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_0_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_0_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_0_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_0_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_0_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_0_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_0_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_0_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_0_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_0_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_0_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_0_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_0_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_0_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_0_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_0_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_0_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_0_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_0_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_0_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_0_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_0_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_0_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_0_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_0_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_0_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_0_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_0_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_0_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_0_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_0_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_0_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_0_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_0_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_0_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_0_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_0_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_0_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_0_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_0_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_0_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_0_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_0_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_0_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_0_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_0_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_0_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_0_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" newline bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_0_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_0_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_0_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end tree "R5SS0_TMU_1" base ad:0x60000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_1_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_1_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R0" group.long 0x48++0x3 line.long 0x0 "TMU_1_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_1_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_1_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_1_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_1_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_1_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_1_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_1_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_1_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_1_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_1_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_1_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_1_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_1_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_1_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_1_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_1_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_1_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_1_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_1_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_1_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_1_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_1_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_1_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_1_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_1_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_1_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_1_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_1_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_1_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_1_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_1_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_1_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_1_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_1_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_1_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_1_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_1_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_1_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_1_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_1_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_1_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_1_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_1_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_1_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_1_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_1_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_1_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_1_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_1_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_1_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_1_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_1_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_1_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" newline bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_1_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_1_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_1_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end base ad:0x0 tree "R5SS0_TMU_EXT" tree "R5SS0_TMU_EXT_CORE0" base ad:0x78060000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_EXT_CORE0_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R0" group.long 0x48++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_EXT_CORE0_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_EXT_CORE0_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_EXT_CORE0_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" newline bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_EXT_CORE0_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_EXT_CORE0_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_EXT_CORE0_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end tree "R5SS0_TMU_EXT_CORE1" base ad:0x78260000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_EXT_CORE1_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R0" group.long 0x48++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_EXT_CORE1_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_EXT_CORE1_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_EXT_CORE1_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" newline bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_EXT_CORE1_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_EXT_CORE1_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_EXT_CORE1_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end tree.end tree "R5SS0_TMU_ROM" tree "R5SS0_TMU_ROM_CORE0" base ad:0x53020000 group.long 0x0++0x3 line.long 0x0 "TMU_ROM_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,TMU ROM start address" group.long 0x2FFC++0x3 line.long 0x0 "TMU_ROM_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,TMU ROM end address" tree.end tree "R5SS0_TMU_ROM_CORE1" base ad:0x53024000 group.long 0x0++0x3 line.long 0x0 "TMU_ROM_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,TMU ROM start address" group.long 0x2FFC++0x3 line.long 0x0 "TMU_ROM_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,TMU ROM end address" tree.end tree.end tree.end tree "R5SS0_VIM0" base ad:0x50F00000 rgroup.long 0x0++0x17 line.long 0x0 "VIM0_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIM0_INFO,The Info Register gives the configuration Inforrmation of this VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD" hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts" line.long 0x8 "VIM0_PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD" hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD" hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set." line.long 0xC "VIM0_PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD" hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set." hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD" hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set." line.long 0x10 "VIM0_IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid. This field indicates that one or more interrupts in Group M are mapped to IRQ unmasked and pending. Bit 0 corresponds to Group 0; Bit 1 corresponds to Group 1 etc. The interrupts associated with each group are.." line.long 0x14 "VIM0_FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid. This field indicates that one or more interrupts in Group M are mapped to FIQ unmasked and pending. Bit 0 corresponds to Group 0; Bit 1 corresponds to Group 1 etc. The interrupts associated with each group are.." group.long 0x18++0x7 line.long 0x0 "VIM0_IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ." hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true." rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3" line.long 0x4 "VIM0_FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ." hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true." rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3" rgroup.long 0x20++0x7 line.long 0x0 "VIM0_ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ." bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1" hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD" hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD" hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set." line.long 0x4 "VIM0_ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ." bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1" hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD" hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD" hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set." group.long 0x28++0xB line.long 0x0 "VIM0_IRQPRIMSK,The IRQ Priority Mask Register allows all IRQs of a particular priority to be enabled or disabled." hexmask.long.word 0x0 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x0 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - IRQs of this priority are enabled. 0 - IRQs of this priority are disabled." line.long 0x4 "VIM0_FIQPRIMSK,The FIQ Priority Mask Register allows all FIQs of a particular priority to be enabled or disabled." hexmask.long.word 0x4 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x4 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - FIQs of this priority are enabled. 0 - FIQs of this priority are disabled." line.long 0x8 "VIM0_DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ." hexmask.long 0x8 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address." rbitfld.long 0x8 0.--1. "RES23,RESERVE FIELD" "0,1,2,3" group.long 0x400++0x1F line.long 0x0 "VIM0_RAW_M,Group M Interrupt Raw Status/Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x4 "VIM0_STS_M,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h ." hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x8 "VIM0_INTR_EN_SET_M,Group M Interrupt Enabled Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xC "VIM0_INTER_EN_CLR_M,Group M Interrupt Enabled Clear Register (M is 0 to 7)Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x10 "VIM0_IRQSTS_M,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x14 "VIM0_FIQSTS_M,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x18 "VIM0_INTMAP_M,Group M Interrupt Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences [if enabled] for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt [default]1 FIQ Interrupt" line.long 0x1C "VIM0_INTTYPE_M,Group M Interrupt Type Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level [default] or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event [see.." group.long 0x1000++0x3 line.long 0x0 "VIM0_INTPRIORITY_Q,Interrupt Q Priority Register (where Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority [Default]" group.long 0x2000++0x3 line.long 0x0 "VIM0_INTVECTOR_Q,Interrupt Q Vector Register (Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address [Base Address + 0x18] or FIQ Vector Address [Base Address + 0x1C] and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" tree.end tree "R5SS0_VIM1" base ad:0x50F00000 rgroup.long 0x0++0x17 line.long 0x0 "VIM1_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIM1_INFO,The Info Register gives the configuration Inforrmation of this VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD" hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts" line.long 0x8 "VIM1_PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD" hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD" hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set." line.long 0xC "VIM1_PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD" hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set." hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD" hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set." line.long 0x10 "VIM1_IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid." line.long 0x14 "VIM1_FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid." group.long 0x18++0x7 line.long 0x0 "VIM1_IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ." hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true." rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3" line.long 0x4 "VIM1_FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ." hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true." rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3" rgroup.long 0x20++0x7 line.long 0x0 "VIM1_ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ." bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1" hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD" hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD" hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set." line.long 0x4 "VIM1_ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ." bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1" hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD" hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD" hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set." group.long 0x28++0xB line.long 0x0 "VIM1_IRQPRIMSK,The IRQ Priority Mask Register allows all IRQs of a particular priority to be enabled or disabled." hexmask.long.word 0x0 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x0 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - IRQs of this priority are enabled. 0 - IRQs of this priority are disabled." line.long 0x4 "VIM1_FIQPRIMSK,The FIQ Priority Mask Register allows all FIQs of a particular priority to be enabled or disabled." hexmask.long.word 0x4 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x4 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - FIQs of this priority are enabled. 0 - FIQs of this priority are disabled." line.long 0x8 "VIM1_DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ." hexmask.long 0x8 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address." rbitfld.long 0x8 0.--1. "RES23,RESERVE FIELD" "0,1,2,3" group.long 0x400++0x1F line.long 0x0 "VIM1_RAW_M,Group M Interrupt Raw Status/Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x4 "VIM1_STS_M,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h ." hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x8 "VIM1_INTR_EN_SET_M,Group M Interrupt Enabled Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xC "VIM1_INTER_EN_CLR_M,Group M Interrupt Enabled Clear Register (M is 0 to 7)Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x10 "VIM1_IRQSTS_M,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x14 "VIM1_FIQSTS_M,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x18 "VIM1_INTMAP_M,Group M Interrupt Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences [if enabled] for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt [default]1 FIQ Interrupt" line.long 0x1C "VIM1_INTTYPE_M,Group M Interrupt Type Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level [default] or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event [see.." group.long 0x1000++0x3 line.long 0x0 "VIM1_INTPRIORITY_Q,Interrupt Q Priority Register (where Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority [Default]" group.long 0x2000++0x3 line.long 0x0 "VIM1_INTVECTOR_Q,Interrupt Q Vector Register (Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address [Base Address + 0x18] or FIQ Vector Address [Base Address + 0x1C] and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" tree.end tree.end tree "R5SS1" tree "R5SS1_CCMR" base ad:0x53211000 group.long 0x0++0x17 line.long 0x0 "CCMR_CCMSR1,CPU Compare Status Register." bitfld.long 0x0 16. "CMPE1,Compare Error0 = CPU signals are identical1= CPU signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x0 8. "STC1,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x0 1. "STET1,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x0 0. "STE1,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x4 "CCMR_CCMKEYR1,CPU Compare Key Register." hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" line.long 0x8 "CCMR_CCMSR2,VIM Compare Status Register." bitfld.long 0x8 16. "CMPE2,Compare Error0 = VIM signals are identical1= VIM signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x8 8. "STC2,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x8 1. "STET2,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" bitfld.long 0x8 0. "STE2,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0xC "CCMR_CCMKEYR2,VIM Compare Key Register." hexmask.long.byte 0xC 0.--3. 1. "MKEY2,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" line.long 0x10 "CCMR_CCMSR3,Inactivity Monitor Status Register." bitfld.long 0x10 16. "CMPE3,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x10 8. "STC3,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x10 1. "STET3,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x10 0. "STE3,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x14 "CCMR_CCMKEYR3,Inactivity Monitor Key Register." hexmask.long.byte 0x14 0.--3. 1. "MKEY3,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" rgroup.long 0x18++0x3 line.long 0x0 "CCMR_CCMPOLCNTRL,CPU Compare Polarity Control Register." hexmask.long.byte 0x0 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode. User and privilege mode read = Returns current value of the POL INVPrivilege mode write = Update the values of POL INV" group.long 0x2C++0xF line.long 0x0 "CCMR_CCMSR5,TMU Compare Status Register." bitfld.long 0x0 16. "CMPE5,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x0 8. "STC5,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x0 1. "STET5,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x0 0. "STE5,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x4 "CCMR_CCMKEYR5,TMU Compare Key Register." hexmask.long.byte 0x4 0.--3. 1. "MKEY5,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" line.long 0x8 "CCMR_CCMSR6,RL2 Compare Status Register." bitfld.long 0x8 16. "CMPE6,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x8 8. "STC6,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x8 1. "STET6,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x8 0. "STE6,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0xC "CCMR_CCMKEYR6,RL2 Compare Key Register." hexmask.long.byte 0xC 0.--3. 1. "MKEY6,Mode Key0000= lock step mode0110= self test mode1001= error forcing mode1111= self test error forcing mode" tree.end base ad:0x0 tree "R5SS1_DCACHE" tree "R5SS1_DCACHE_CORE0" base ad:0x76800000 group.long 0x0++0x3 line.long 0x0 "DCACHE_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "DCACHE_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree "R5SS1_DCACHE_CORE1" base ad:0x77800000 group.long 0x0++0x3 line.long 0x0 "DCACHE_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "DCACHE_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree.end tree "R5SS1_ECC_AGG" tree "R5SS1_ECC_AGG_CORE0" base ad:0x53004000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_CORE0_AGGR_REVISION,Revision parameters register. The Revision Register contains the major and minor revisions for the ECC aggregator module. It does notsupport byte accesses." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_CORE0_ECC_VECTOR,ECC Vector Register. ECC RAM ID to select which ECC RAM to control or read status from." rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x7 line.long 0x0 "ECC_AGG_CORE0_MISC_STATUS,Misc Statu register. It contains misc status such as number of ECC RAMs serviced by the ECC aggregator." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x4 "ECC_AGG_CORE0_ECC_WRAP_REVISION,Revision parameters." bitfld.long 0x4 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x4 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x4 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor version" group.long 0x14++0xF line.long 0x0 "ECC_AGG_CORE0_CONTROL,ECC Control Register." bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" newline bitfld.long 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" newline bitfld.long 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x4 "ECC_AGG_CORE0_ERROR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_AGG_CORE0_ERROR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" newline hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_AGG_CORE0_ERROR_STATUS1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" newline bitfld.long 0xC 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0xC 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" newline bitfld.long 0xC 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0xC 4. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_CORE0_ERROR_STATUS2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_AGG_CORE0_ERROR_STATUS3,ECC Error Status3 Register." bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" newline bitfld.long 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.long 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_CORE0_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_CORE0_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU0_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_CORE0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_CORE0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_CORE0_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_CORE0_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU0_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_CORE0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_CORE0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU0_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGG_CORE0_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGG_CORE0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGG_CORE0_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. 2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 0x0: No timeout errors have occurred 0x1: 1 timeout erro has occurred 0x2: 2 timeout error has occurred.." "0: No timeout errors have occurred,1: 1 timeout erro has occurred,2: 2 timeout error has occurred,3: 3 or more timeout errors have occurred A write.." newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3 3 or.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred 0x3 3 or more parity..,?" line.long 0xC "ECC_AGG_CORE0_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. 0x0: No timeout errors have occurred 0x1: 1 timeout error has occurred 0x2: 2 timeout error has occurred 0x3: 3 or more timeout error have occurred A write of a non-zero value to this register.." "0: No timeout errors have occurred,1: 1 timeout error has occurred,2: 2 timeout error has occurred,3: 3 or more timeout error have occurred A write of.." newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3: 3 or more parity error have occurred A write of a non-zero value to this register decrements that.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred,3: 3 or more parity error have occurred A write of.." tree.end tree "R5SS1_ECC_AGG_CORE1" base ad:0x53007000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_CORE1_AGGR_REVISION,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_CORE1_ECC_VECTOR,ECC Vector Register." rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x7 line.long 0x0 "ECC_AGG_CORE1_MISC_STATUS,Misc Status." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x4 "ECC_AGG_CORE1_ECC_WRAP_REVISION,Revision parameters." bitfld.long 0x4 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x4 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x4 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor version" group.long 0x14++0xF line.long 0x0 "ECC_AGG_CORE1_CONTROL,ECC Control Register." bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" newline bitfld.long 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.long 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" newline bitfld.long 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x4 "ECC_AGG_CORE1_ERROR_CTRL1,ECC Error Control1 Register." hexmask.long 0x4 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "ECC_AGG_CORE1_ERROR_CTRL2,ECC Error Control2 Register." hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" newline hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0xC "ECC_AGG_CORE1_ERROR_STATUS1,ECC Error Status1 Register." hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" newline bitfld.long 0xC 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0xC 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" newline bitfld.long 0xC 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0xC 4. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0xC 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_CORE1_ERROR_STATUS2,ECC Error Status2 Register." hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "ECC_AGG_CORE1_ERROR_STATUS3,ECC Error Status3 Register." bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" newline bitfld.long 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.long 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_CORE1_SEC_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register Write of 1 to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. The bit is self clearing and will be read as a zero." "0,1" line.long 0x4 "ECC_AGG_CORE1_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU1_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_CORE1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_CORE1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_CORE1_DED_EOI_REG,EOI Register." bitfld.long 0x0 0. "EOI_WR,EOI Register Write of 1 to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. The bit is self clearing and will be read as a zero." "0,1" line.long 0x4 "ECC_AGG_CORE1_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 28. "CPU1_RL2_OF_RAMECC_PEND,Interrupt Pending Status for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_CORE1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_CORE1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 28. "CPU1_RL2_OF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_rl2_of_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" newline bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGG_CORE1_AGGR_ENABLE_SET,AGGR interrupt enable set Register." bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGG_CORE1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGG_CORE1_AGGR_STATUS_SET,AGGR interrupt status set Register." bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. 2-bit saturating counter of the number of timeout errors that have occurred since last cleared. 0x0: No timeout errors have occurred 0x1: 1 timeout erro has occurred 0x2: 2 timeout error has occurred.." "0: No timeout errors have occurred,1: 1 timeout erro has occurred,2: 2 timeout error has occurred,3: 3 or more timeout errors have occurred A write.." newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3 3 or.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred 0x3 3 or more parity..,?" line.long 0xC "ECC_AGG_CORE1_AGGR_STATUS_CLR,AGGR interrupt status clear Register." bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. 0x0: No timeout errors have occurred 0x1: 1 timeout error has occurred 0x2: 2 timeout error has occurred 0x3: 3 or more timeout error have occurred A write of a non-zero value to this register.." "0: No timeout errors have occurred,1: 1 timeout error has occurred,2: 2 timeout error has occurred,3: 3 or more timeout error have occurred A write of.." newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. 0x0: No parity errors have occurred 0x1: 1 parity error has occurred 0x2: 2 parity error has occurred 0x3: 3 or more parity error have occurred A write of a non-zero value to this register decrements that.." "0: No parity errors have occurred,1: 1 parity error has occurred,2: 2 parity error has occurred,3: 3 or more parity error have occurred A write of.." tree.end tree.end tree "R5SS1_ICACHE" tree "R5SS1_ICACHE_CORE0" base ad:0x76000000 group.long 0x0++0x3 line.long 0x0 "ICACHE_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "ICACHE_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree "R5SS1_ICACHE_CORE1" base ad:0x77000000 group.long 0x0++0x3 line.long 0x0 "ICACHE_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,Memory start address" group.long 0x7FFFFC++0x3 line.long 0x0 "ICACHE_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,Memory end address" tree.end tree.end tree "R5SS1_STC" base ad:0x53510000 group.long 0x0++0xB line.long 0x0 "STC_STCGCR0,Self test Global control Reg0. *NOT BYTE ACCESSIBLE." hexmask.long.word 0x0 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run [RWP - Read Priviledge Mode Write only]Count of intervals that need to be covered for a specific selftest run.The selftest controller sends out complete indication once it runs all of the intervals.." newline hexmask.long.byte 0x0 11.--15. 1. "NU0,Reserved bits" newline bitfld.long 0x0 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock [RWP - Read Priviledge Mode Write only]Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock [RWP - Read Priviledge Mode Write only]. *NOT BYTE ACCESSIBLEIdle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "RS_CNT_B1,Restart/Continue or preload [RWP - Read Priviledge Mode Write only]This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval. This bit.." "0: Continue NSTC run from previous interval01 =..,?,?,?" line.long 0x4 "STC_STCGCR1,Self test Global control Reg1." hexmask.long.tbyte 0x4 12.--31. 1. "NU2,Reserved bits" newline hexmask.long.byte 0x4 8.--11. 1. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test [RWP - Read Priviledge Mode Write only]Select the Segment0 CORE for Self -Test0001= Select CORE for selftestOther = CORE not selected." newline rbitfld.long 0x4 7. "NU3,Reserved bits" "0,1" newline bitfld.long 0x4 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal [RWP - Read Priviledge Mode Write only]This bit is used to configure the codec in spread / X-OR mode.1 = Spread mode0 = XOR mode" "?,1: Spread mode0 = XOR mode" newline bitfld.long 0x4 5. "LP_SCAN_MODE,LP scan mode [RWP - Read Priviledge Mode Write only]This bit is used to decide the scan configuration:1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode." "0: Operates in Normal Scan Mode,1: Operates in Low Power Scan Mode" newline bitfld.long 0x4 4. "ROM_ACCESS_INV,Rom access inversion mode [RWP - Read Priviledge Mode Write only]- NOT SUPPORTED" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "ST_ENA_B4,Self test enable key [RWP - Read Priviledge Mode Write only]1010= Self test run enabled All values other than1010= Self test run disabled" line.long 0x8 "STC_STCTPR,Time out counter preload register." hexmask.long 0x8 0.--31. 1. "TO_PRELOAD,Self test time out preload [RWP - Read Priviledge Mode Write only]This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is a.." rgroup.long 0xC++0xF line.long 0x0 "STC_STC_CADDR,Current Address register for CORE1." hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE1This register reflects the current ROM address [for micro code load] accessed during selftest for CORE1 in of case segment0 and all the remaining segmentsn where n = 1 to 3]." line.long 0x4 "STC_STCCICR,Current Interval count register." hexmask.long.word 0x4 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well. This field is applicable only for Segment 0." newline hexmask.long.word 0x4 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1This specifies the Last executed Interval number of a self-test run." line.long 0x8 "STC_STCGSTAT,Global Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "NU4,Reserved bits" newline hexmask.long.byte 0x8 8.--11. 1. "ST_ACTIVE,Tells whether self test is currently active or not.1010 = Self test is activeOthers = SelfTest is not activeOnce the self-test completes and ST_ENA_B4 key is cleared this field will reflect the inactive value." newline hexmask.long.byte 0x8 2.--7. 1. "NU5,Reserved bits" newline bitfld.long 0x8 1. "TEST_FAIL,Test_fail flag [RCP - Read Clear on Writing in Priviledge Mode]0 = Self test run has not failed1 = SelfTest run has failed. Write Clear." "0,1" newline bitfld.long 0x8 0. "TEST_DONE,Test_done_flag [RCP - Read Clear on Writing in Priviledge Mode]0 = Not completed1 = SelfTest run Completed" "0,1" line.long 0xC "STC_STCFSTAT,Fail Status Register." hexmask.long 0xC 5.--31. 1. "NU6,Reserved bits" newline bitfld.long 0xC 3.--4. "FSEG_ID,Failed Segment ID [RCP - Read Clear on Writing in Priviledge Mode]This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur.00 = Failure on Segment 001 = Failure on Segment 110.." "0: Failure on Segment,1: Failure on Segment,?,?" newline bitfld.long 0xC 2. "TO_ER_B1,Tells whether self test failed because of time out error [RCP - Read Clear on Writing in Priviledge Mode]0 = No time out error occurred1 = SelfTest run failed due to a timeout error" "0,1" newline bitfld.long 0xC 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode [RCP - Read Clear on Writing in Priviledge Mode]0 = No MISR mismatch for CORE21 = Self test run failed due to MISR mismatch for CORE2" "0,1" newline bitfld.long 0xC 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 [RCP - Read Clear on Writing in Priviledge Mode]Applicable to all segments.0 = No MISR mismatch for CORE11 = Self test run failed due to MISR mismatch for CORE1" "0: No MISR mismatch for CORE11 = Self test run..,?" group.long 0x1C++0x3 line.long 0x0 "STC_STCSCSCR,Signature compare Self Check Register." hexmask.long 0x0 5.--31. 1. "NU7,Reserved bits" newline bitfld.long 0x0 4. "FAULT_INS_B1,Fault Insertion bit [RWP - Read Priviledge Mode Write only]0 = No fault insertion.1 = Inserts fault in the logic under test which will make signature compare fail. This feature is used as diagnostic check of the STC IP." "?,1: Inserts fault in the logic under test which will.." newline hexmask.long.byte 0x0 0.--3. 1. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable [RWP - Read Priviledge Mode Write only]1010 = Signature compare logic Self Check is enabledAll values other than1010 = Signature compare logic Self Check is disabled" rgroup.long 0x20++0x3 line.long 0x0 "STC_STC_CADDR2,Current Address register for CORE2." hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE2This register reflects the current ROM address[for micro code load] accessed during selftest for CORE2 in of case segment0." group.long 0x24++0x17 line.long 0x0 "STC_STC_CLKDIV,Clock Divider Register." hexmask.long.byte 0x0 27.--31. 1. "NU8,Reserved bits" newline bitfld.long 0x0 24.--26. "CLKDIV0,Clock division for Seg0 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "NU9,Reserved bits" newline bitfld.long 0x0 16.--18. "CLKDIV1,Clock division for Seg1 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "NU10,Reserved bits" newline bitfld.long 0x0 8.--10. "CLKDIV2,Clock division for Seg2 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "NU11,Reserved bits" newline bitfld.long 0x0 0.--2. "CLKDIV3,Clock division for Seg3 [RWP - Read Priviledge Mode Write only]*NOT SUPPORTEDX = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7" line.long 0x4 "STC_STC_SEGPLR,Segment 1st interval Preload Register." hexmask.long 0x4 2.--31. 1. "NU12,Reserved bits" newline bitfld.long 0x4 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started [RWP - Read Priviledge Mode Write only]This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter. The 1st address of each.." "?,1: Preload the address of the 1st interval of..,?,?" line.long 0x8 "STC_SEG0_START_ADDR,ROM Start address for Segment0." hexmask.long.word 0x8 20.--31. 1. "NU13,Reserved bits" newline hexmask.long.tbyte 0x8 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." line.long 0xC "STC_SEG1_START_ADDR,ROM Start address for Segment1." hexmask.long.word 0xC 20.--31. 1. "NU14,Reserved bits" newline hexmask.long.tbyte 0xC 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." line.long 0x10 "STC_SEG2_START_ADDR,ROM Start address for Segment2." hexmask.long.word 0x10 20.--31. 1. "NU15,Reserved bits" newline hexmask.long.tbyte 0x10 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." line.long 0x14 "STC_SEG3_START_ADDR,ROM Start address for Segment3." hexmask.long.word 0x14 20.--31. 1. "NU16,Reserved bits" newline hexmask.long.tbyte 0x14 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address [RWP - Read Priviledge Mode Write only]This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option this register is used to.." rgroup.long 0x3C++0xDF line.long 0x0 "STC_CORE1_CURMISR_0,Holds the MISR signature for CORE1." hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4 "STC_CORE1_CURMISR_1,Holds the MISR signature for CORE1." hexmask.long 0x4 0.--31. 1. "C1MISR1,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x8 "STC_CORE1_CURMISR_2,Holds the MISR signature for CORE1." hexmask.long 0x8 0.--31. 1. "C1MISR2,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0xC "STC_CORE1_CURMISR_3,Holds the MISR signature for CORE1." hexmask.long 0xC 0.--31. 1. "C1MISR3,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x10 "STC_CORE1_CURMISR_4,Holds the MISR signature for CORE1." hexmask.long 0x10 0.--31. 1. "C1MISR4,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x14 "STC_CORE1_CURMISR_5,Holds the MISR signature for CORE1." hexmask.long 0x14 0.--31. 1. "C1MISR5,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x18 "STC_CORE1_CURMISR_6,Holds the MISR signature for CORE1." hexmask.long 0x18 0.--31. 1. "C1MISR6,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x1C "STC_CORE1_CURMISR_7,Holds the MISR signature for CORE1." hexmask.long 0x1C 0.--31. 1. "C1MISR7,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x20 "STC_CORE1_CURMISR_8,Holds the MISR signature for CORE1." hexmask.long 0x20 0.--31. 1. "C1MISR8,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x24 "STC_CORE1_CURMISR_9,Holds the MISR signature for CORE1." hexmask.long 0x24 0.--31. 1. "C1MISR9,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x28 "STC_CORE1_CURMISR_10,Holds the MISR signature for CORE1." hexmask.long 0x28 0.--31. 1. "C1MISR10,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x2C "STC_CORE1_CURMISR_11,Holds the MISR signature for CORE1." hexmask.long 0x2C 0.--31. 1. "C1MISR11,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x30 "STC_CORE1_CURMISR_12,Holds the MISR signature for CORE1." hexmask.long 0x30 0.--31. 1. "C1MISR12,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x34 "STC_CORE1_CURMISR_13,Holds the MISR signature for CORE1." hexmask.long 0x34 0.--31. 1. "C1MISR13,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x38 "STC_CORE1_CURMISR_14,Holds the MISR signature for CORE1." hexmask.long 0x38 0.--31. 1. "C1MISR14,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x3C "STC_CORE1_CURMISR_15,Holds the MISR signature for CORE1." hexmask.long 0x3C 0.--31. 1. "C1MISR15,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x40 "STC_CORE1_CURMISR_16,Holds the MISR signature for CORE1." hexmask.long 0x40 0.--31. 1. "C1MISR16,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x44 "STC_CORE1_CURMISR_17,Holds the MISR signature for CORE1." hexmask.long 0x44 0.--31. 1. "C1MISR17,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x48 "STC_CORE1_CURMISR_18,Holds the MISR signature for CORE1." hexmask.long 0x48 0.--31. 1. "C1MISR18,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4C "STC_CORE1_CURMISR_19,Holds the MISR signature for CORE1." hexmask.long 0x4C 0.--31. 1. "C1MISR19,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x50 "STC_CORE1_CURMISR_20,Holds the MISR signature for CORE1." hexmask.long 0x50 0.--31. 1. "C1MISR20,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x54 "STC_CORE1_CURMISR_21,Holds the MISR signature for CORE1." hexmask.long 0x54 0.--31. 1. "C1MISR21,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x58 "STC_CORE1_CURMISR_22,Holds the MISR signature for CORE1." hexmask.long 0x58 0.--31. 1. "C1MISR22,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x5C "STC_CORE1_CURMISR_23,Holds the MISR signature for CORE1." hexmask.long 0x5C 0.--31. 1. "C1MISR23,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x60 "STC_CORE1_CURMISR_24,Holds the MISR signature for CORE1." hexmask.long 0x60 0.--31. 1. "C1MISR24,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x64 "STC_CORE1_CURMISR_25,Holds the MISR signature for CORE1." hexmask.long 0x64 0.--31. 1. "C1MISR25,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x68 "STC_CORE1_CURMISR_26,Holds the MISR signature for CORE1." hexmask.long 0x68 0.--31. 1. "C1MISR26,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x6C "STC_CORE1_CURMISR_27,Holds the MISR signature for CORE1." hexmask.long 0x6C 0.--31. 1. "C1MISR27,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x70 "STC_CORE2_CURMISR_0,Holds the MISR signature for CORE2." hexmask.long 0x70 0.--31. 1. "C2MISR0,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x74 "STC_CORE2_CURMISR_1,Holds the MISR signature for CORE2." hexmask.long 0x74 0.--31. 1. "C2MISR1,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x78 "STC_CORE2_CURMISR_2,Holds the MISR signature for CORE2." hexmask.long 0x78 0.--31. 1. "C2MISR2,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x7C "STC_CORE2_CURMISR_3,Holds the MISR signature for CORE2." hexmask.long 0x7C 0.--31. 1. "C2MISR3,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x80 "STC_CORE2_CURMISR_4,Holds the MISR signature for CORE2." hexmask.long 0x80 0.--31. 1. "C2MISR4,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x84 "STC_CORE2_CURMISR_5,Holds the MISR signature for CORE2." hexmask.long 0x84 0.--31. 1. "C2MISR5,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x88 "STC_CORE2_CURMISR_6,Holds the MISR signature for CORE2." hexmask.long 0x88 0.--31. 1. "C2MISR6,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x8C "STC_CORE2_CURMISR_7,Holds the MISR signature for CORE2." hexmask.long 0x8C 0.--31. 1. "C2MISR7,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x90 "STC_CORE2_CURMISR_8,Holds the MISR signature for CORE2." hexmask.long 0x90 0.--31. 1. "C2MISR8,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x94 "STC_CORE2_CURMISR_9,Holds the MISR signature for CORE2." hexmask.long 0x94 0.--31. 1. "C2MISR9,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x98 "STC_CORE2_CURMISR_10,Holds the MISR signature for CORE2." hexmask.long 0x98 0.--31. 1. "C2MISR10,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x9C "STC_CORE2_CURMISR_11,Holds the MISR signature for CORE2." hexmask.long 0x9C 0.--31. 1. "C2MISR11,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA0 "STC_CORE2_CURMISR_12,Holds the MISR signature for CORE2." hexmask.long 0xA0 0.--31. 1. "C2MISR12,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA4 "STC_CORE2_CURMISR_13,Holds the MISR signature for CORE2." hexmask.long 0xA4 0.--31. 1. "C2MISR13,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA8 "STC_CORE2_CURMISR_14,Holds the MISR signature for CORE2." hexmask.long 0xA8 0.--31. 1. "C2MISR14,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xAC "STC_CORE2_CURMISR_15,Holds the MISR signature for CORE2." hexmask.long 0xAC 0.--31. 1. "C2MISR15,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB0 "STC_CORE2_CURMISR_16,Holds the MISR signature for CORE2." hexmask.long 0xB0 0.--31. 1. "C2MISR16,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB4 "STC_CORE2_CURMISR_17,Holds the MISR signature for CORE2." hexmask.long 0xB4 0.--31. 1. "C2MISR17,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB8 "STC_CORE2_CURMISR_18,Holds the MISR signature for CORE2." hexmask.long 0xB8 0.--31. 1. "C2MISR18,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xBC "STC_CORE2_CURMISR_19,Holds the MISR signature for CORE2." hexmask.long 0xBC 0.--31. 1. "C2MISR19,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC0 "STC_CORE2_CURMISR_20,Holds the MISR signature for CORE2." hexmask.long 0xC0 0.--31. 1. "C2MISR20,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC4 "STC_CORE2_CURMISR_21,Holds the MISR signature for CORE2." hexmask.long 0xC4 0.--31. 1. "C2MISR21,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC8 "STC_CORE2_CURMISR_22,Holds the MISR signature for CORE2." hexmask.long 0xC8 0.--31. 1. "C2MISR22,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xCC "STC_CORE2_CURMISR_23,Holds the MISR signature for CORE2." hexmask.long 0xCC 0.--31. 1. "C2MISR23,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD0 "STC_CORE2_CURMISR_24,Holds the MISR signature for CORE2." hexmask.long 0xD0 0.--31. 1. "C2MISR24,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD4 "STC_CORE2_CURMISR_25,Holds the MISR signature for CORE2." hexmask.long 0xD4 0.--31. 1. "C2MISR25,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD8 "STC_CORE2_CURMISR_26,Holds the MISR signature for CORE2." hexmask.long 0xD8 0.--31. 1. "C2MISR26,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xDC "STC_CORE2_CURMISR_27,Holds the MISR signature for CORE2." hexmask.long 0xDC 0.--31. 1. "C2MISR27,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." tree.end base ad:0x0 tree "R5SS1_TCMA" tree "R5SS1_TCMA_CORE0" base ad:0x78400000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0x27FFC++0x3 line.long 0x0 "TCMA_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS1_TCMA_CORE0_RAM" base ad:0x20000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE0_RAM_START" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "TCMA_CORE0_RAM_END" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end tree "R5SS1_TCMA_CORE1" base ad:0x78600000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0x7FFC++0x3 line.long 0x0 "TCMA_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS1_TCMA_CORE1_RAM" base ad:0x20000 group.long 0x0++0x3 line.long 0x0 "TCMA_CORE1_RAM_START" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "TCMA_CORE1_RAM_END" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end tree.end tree "R5SS1_TCMB" tree "R5SS1_TCMB_CORE0" base ad:0x78500000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x2FFFC++0x3 line.long 0x0 "TCMB_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS1_TCMB_CORE0_RAM" base ad:0x80000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE0_RAM_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x17FFC++0x3 line.long 0x0 "TCMB_CORE0_RAM_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS1_TCMB_CORE1" base ad:0x78700000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x17FFC++0x3 line.long 0x0 "TCMB_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS1_TCMB_CORE1_RAM" base ad:0x80000 group.long 0x0++0x3 line.long 0x0 "TCMB_CORE1_RAM_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x17FFC++0x3 line.long 0x0 "TCMB_CORE1_RAM_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree.end tree "R5SS1_TMU" tree "R5SS1_TMU_0" base ad:0x60000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_0_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_0_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0" group.long 0x48++0x3 line.long 0x0 "TMU_0_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_0_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_0_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_0_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_0_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_0_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_0_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_0_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_0_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_0_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_0_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_0_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_0_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_0_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_0_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_0_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_0_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_0_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_0_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_0_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_0_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_0_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_0_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_0_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_0_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_0_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_0_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_0_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_0_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_0_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_0_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_0_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_0_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_0_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_0_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_0_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_0_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_0_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_0_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_0_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_0_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_0_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_0_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_0_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_0_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_0_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_0_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_0_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_0_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_0_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_0_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_0_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_0_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_0_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_0_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_0_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_0_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" newline bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_0_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_0_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_0_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end tree "R5SS1_TMU_1" base ad:0x60000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_1_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_1_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R0" group.long 0x48++0x3 line.long 0x0 "TMU_1_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_1_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_1_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_1_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_1_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_1_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_1_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_1_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_1_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_1_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_1_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_1_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_1_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_1_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_1_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_1_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_1_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_1_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_1_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_1_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_1_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_1_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_1_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_1_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_1_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_1_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_1_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_1_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_1_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_1_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_1_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_1_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_1_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_1_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_1_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_1_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_1_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_1_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_1_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_1_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_1_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_1_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_1_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_1_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_1_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_1_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_1_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_1_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_1_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_1_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_1_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_1_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_1_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_1_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_1_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_1_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_1_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" newline bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_1_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_1_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_1_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end base ad:0x0 tree "R5SS1_TMU_EXT" tree "R5SS1_TMU_EXT_CORE0" base ad:0x78460000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_EXT_CORE0_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R0" group.long 0x48++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_EXT_CORE0_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_EXT_CORE0_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_EXT_CORE0_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_EXT_CORE0_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_EXT_CORE0_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_EXT_CORE0_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_EXT_CORE0_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_EXT_CORE0_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_EXT_CORE0_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_EXT_CORE0_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_EXT_CORE0_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" newline bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_EXT_CORE0_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_EXT_CORE0_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_EXT_CORE0_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end tree "R5SS1_TMU_EXT_CORE1" base ad:0x78660000 rgroup.long 0x0++0x3 line.long 0x0 "TMU_EXT_CORE1_REVISION,IP revision id register." bitfld.long 0x0 30.--31. "SCHEME,This identifies the scheme revision ID register type implemented for this module" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional Release Number Reflects software-compatability. If there is no software compatability a unique func number is assigned; for compatible modules the same number is maintained." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number Represents major changes to the module [e.g. entirely new features are added/changed]. The major revision number for this module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom Module Number Indicates a special version of the module. May not be supported by standard software." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision Number Represents minor changes to the module [e.g. enhancements to existing features]. The minor revision number for this module." group.long 0x40++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R0,Updates operand 1 for SINPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "SINPUF32_R0,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R0" group.long 0x48++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R1,Updates operand 1 for SINPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "SINPUF32_R1,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R1" group.long 0x50++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R2,Updates operand 1 for SINPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "SINPUF32_R2,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R2" group.long 0x58++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R3,Updates operand 1 for SINPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "SINPUF32_R3,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R3" group.long 0x60++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R4,Updates operand 1 for SINPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "SINPUF32_R4,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R4" group.long 0x68++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R5,Updates operand 1 for SINPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "SINPUF32_R5,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R5" group.long 0x70++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R6,Updates operand 1 for SINPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "SINPUF32_R6,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R6" group.long 0x78++0x3 line.long 0x0 "TMU_EXT_CORE1_SINPUF32_R7,Updates operand 1 for SINPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "SINPUF32_R7,Write to this register will update Operand 1 Update will trigger SINPUF32 operation Result will be saved to R7" group.long 0x80++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R0,Updates operand 1 for COSPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "COSPUF32_R0,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R0" group.long 0x88++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R1,Updates operand 1 for COSPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "COSPUF32_R1,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R1" group.long 0x90++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R2,Updates operand 1 for COSPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "COSPUF32_R2,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R2" group.long 0x98++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R3,Updates operand 1 for COSPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "COSPUF32_R3,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R3" group.long 0xA0++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R4,Updates operand 1 for COSPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "COSPUF32_R4,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R4" group.long 0xA8++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R5,Updates operand 1 for COSPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "COSPUF32_R5,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R5" group.long 0xB0++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R6,Updates operand 1 for COSPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "COSPUF32_R6,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R6" group.long 0xB8++0x3 line.long 0x0 "TMU_EXT_CORE1_COSPUF32_R7,Updates operand 1 for COSPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "COSPUF32_R7,Write to this register will update Operand 1 Update will trigger COSPUF32 operation Result will be saved to R7" group.long 0xC0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R0,Updates operand 1 for ATANPUF32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R0,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R0" group.long 0xC8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R1,Updates operand 1 for ATANPUF32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R1,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R1" group.long 0xD0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R2,Updates operand 1 for ATANPUF32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R2,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R2" group.long 0xD8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R3,Updates operand 1 for ATANPUF32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R3,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R3" group.long 0xE0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R4,Updates operand 1 for ATANPUF32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R4,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R4" group.long 0xE8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R5,Updates operand 1 for ATANPUF32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R5,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R5" group.long 0xF0++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R6,Updates operand 1 for ATANPUF32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R6,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R6" group.long 0xF8++0x3 line.long 0x0 "TMU_EXT_CORE1_ATANPUF32_R7,Updates operand 1 for ATANPUF32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "ATANPUF32_R7,Write to this register will update Operand 1 Update will trigger ATANPUF32 operation Result will be saved to R7" group.long 0x140++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R0,Updates operand 1 for IEXP2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R0,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R0" group.long 0x148++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R1,Updates operand 1 for IEXP2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R1,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R1" group.long 0x150++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R2,Updates operand 1 for IEXP2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R2,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R2" group.long 0x158++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R3,Updates operand 1 for IEXP2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R3,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R3" group.long 0x160++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R4,Updates operand 1 for IEXP2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R4,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R4" group.long 0x168++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R5,Updates operand 1 for IEXP2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R5,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R5" group.long 0x170++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R6,Updates operand 1 for IEXP2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R6,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R6" group.long 0x178++0x3 line.long 0x0 "TMU_EXT_CORE1_IEXP2F32_R7,Updates operand 1 for IEXP2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "IEXP2F32_R7,Write to this register will update Operand 1 Update will trigger IEXP2F32 operation Result will be saved to R7" group.long 0x180++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R0,Updates operand 1 for LOG2F32 operation. Result will be saved to R0." hexmask.long 0x0 0.--31. 1. "LOG2F32_R0,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R0" group.long 0x188++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R1,Updates operand 1 for LOG2F32 operation. Result will be saved to R1." hexmask.long 0x0 0.--31. 1. "LOG2F32_R1,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R1" group.long 0x190++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R2,Updates operand 1 for LOG2F32 operation. Result will be saved to R2." hexmask.long 0x0 0.--31. 1. "LOG2F32_R2,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R2" group.long 0x198++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R3,Updates operand 1 for LOG2F32 operation. Result will be saved to R3." hexmask.long 0x0 0.--31. 1. "LOG2F32_R3,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R3" group.long 0x1A0++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R4,Updates operand 1 for LOG2F32 operation. Result will be saved to R4." hexmask.long 0x0 0.--31. 1. "LOG2F32_R4,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R4" group.long 0x1A8++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R5,Updates operand 1 for LOG2F32 operation. Result will be saved to R5." hexmask.long 0x0 0.--31. 1. "LOG2F32_R5,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R5" group.long 0x1B0++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R6,Updates operand 1 for LOG2F32 operation. Result will be saved to R6." hexmask.long 0x0 0.--31. 1. "LOG2F32_R6,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R6" group.long 0x1B8++0x3 line.long 0x0 "TMU_EXT_CORE1_LOG2F32_R7,Updates operand 1 for LOG2F32 operation. Result will be saved to R7." hexmask.long 0x0 0.--31. 1. "LOG2F32_R7,Write to this register will update Operand 1 Update will trigger LOG2F32 operation Result will be saved to R7" group.long 0x1C0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R0_R1,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R0 and R1." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R0_R1,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R0 and R1" group.long 0x1C8++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R1_R2,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R1 and R2." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R1_R2,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R1 and R2" group.long 0x1D0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R2_R3,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R2 and R3." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R2_R3,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R2 and R3" group.long 0x1D8++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R3_R4,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R3 and R4." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R3_R4,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R3 and R4" group.long 0x1E0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R4_R5,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R4 and R5." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R4_R5,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R4 and R5" group.long 0x1E8++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R5SS0_R6,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R5 and R6." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R5_R6,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R5 and R6" group.long 0x1F0++0x3 line.long 0x0 "TMU_EXT_CORE1_QUADF32_X_R6_R7,Updates operand 1 (X) for QUADF32 operation. Result will be saved to R6 and R7." hexmask.long 0x0 0.--31. 1. "QUADF32_X_R6_R7,Write to this register will update Operand 1 Operand 2 must be written first by Writing to register QUADF32_Y Update will trigger QUADF32 operation Result will be saved to R6 and R7" rgroup.long 0x280++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R0,R0 result register." hexmask.long 0x0 0.--31. 1. "R0,R0 result register" rgroup.long 0x288++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R1,R1 result register." hexmask.long 0x0 0.--31. 1. "R1,R1 result register" rgroup.long 0x290++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R2,R2 result register." hexmask.long 0x0 0.--31. 1. "R2,R2 result register" rgroup.long 0x298++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R3,R3 result register." hexmask.long 0x0 0.--31. 1. "R3,R3 result register" rgroup.long 0x2A0++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R4,R4 result register." hexmask.long 0x0 0.--31. 1. "R4,R4 result register" rgroup.long 0x2A8++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R5,R5 result register." hexmask.long 0x0 0.--31. 1. "R5,R5 result register" rgroup.long 0x2B0++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R6,R6 result register." hexmask.long 0x0 0.--31. 1. "R6,R6 result register" rgroup.long 0x2B8++0x3 line.long 0x0 "TMU_EXT_CORE1_RESULT_R7,R7 result register." hexmask.long 0x0 0.--31. 1. "R7,R7 result register" rgroup.long 0x2C0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R0,Context save of R0 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R0,Context save of R0 result register" rgroup.long 0x2C8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R1,Context save of R1 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R1,Context save of R1 result register" rgroup.long 0x2D0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R2,Context save of R2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R2,Context save of R2 result register" rgroup.long 0x2D8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R3,Context save of R3 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R3,Context save of R3 result register" rgroup.long 0x2E0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R4,Context save of R4 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R4,Context save of R4 result register" rgroup.long 0x2E8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R5,Context save of R5 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R5,Context save of R5 result register" rgroup.long 0x2F0++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R6,Context save of R6 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R6,Context save of R6 result register" rgroup.long 0x2F8++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_R7,Context save of R7 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_R7,Context save of R7 result register" rgroup.long 0x300++0x3 line.long 0x0 "TMU_EXT_CORE1_CSAVE_OP2,Context save of Operarand2 result register." hexmask.long 0x0 0.--31. 1. "CSAVE_OP2,Context save of operand 2 [OP2] result register" group.long 0x308++0x3 line.long 0x0 "TMU_EXT_CORE1_CONTEXT_SAVE,Register to initiate context save of result registers." bitfld.long 0x0 0. "SAVE,Writing one will initiate context save. Context save will be done only after completion all operations initiated by master before context save was issued. Results registers R0 to R3 and Operand2 will be saved. Note: Contex is saved within IP not to.." "0,1" group.long 0x310++0x3 line.long 0x0 "TMU_EXT_CORE1_CONTEXT_RESTORE,Register to initiate context restore of result registers." bitfld.long 0x0 0. "RESTORE,Writing one will initiate context restore. Results registers R0 to R3 and Operand2 will be restored." "0,1" group.long 0x348++0x3 line.long 0x0 "TMU_EXT_CORE1_STF,TMU status Register." rbitfld.long 0x0 9. "LUF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LUF 1:Enables write to LUF" "?,1: Enables write to LUF" rbitfld.long 0x0 8. "LVF_WR_EN,Always read as zero Value is written to this bit either enables/disables write to LVF [[br]0:Disbles write to LVF 1:Enables write to LVF" "?,1: Enables write to LVF" newline bitfld.long 0x0 1. "LUF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LUF_WR_EN Is written with '1'" "0,1" bitfld.long 0x0 0. "LVF,Is set to '1' when a TMU operation results in LVF. It is sticky bit once set it remains set until it is cleared with write. It can be written only when LVF_WR_EN Is written with '1'" "0,1" group.long 0x380++0x3 line.long 0x0 "TMU_EXT_CORE1_PARITY_TEST,Enabling the parity test feature." hexmask.long.byte 0x0 0.--3. 1. "TESTEN,1010: Parity test feature is enabled All other values: Parity test feature is disabled Note: When the parity test feature is enabled acutal registers are not accessible in the memory map. Instead the parity values are accessible. Parity is.." group.long 0x390++0x3 line.long 0x0 "TMU_EXT_CORE1_LCM_LOCK,LCM lock configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register configuration is not locked. [[br]1:Register configuration is locked." "0: Register configuration is not locked,?" group.long 0x3A0++0x3 line.long 0x0 "TMU_EXT_CORE1_LCM_COMMIT,LCM commit configuration." bitfld.long 0x0 0. "PARITY_TEST,0: Register lock configuration is not committed. [[br]1:Register lock configuration is committed. Once configuration is committed only reset can change the configuration." "0: Register lock configuration is not committed,?" tree.end tree.end tree "R5SS1_TMU_ROM" tree "R5SS1_TMU_ROM_CORE0" base ad:0x53028000 group.long 0x0++0x3 line.long 0x0 "TMU_ROM_CORE0_START" hexmask.long 0x0 0.--31. 1. "START,TMU ROM start address" group.long 0x2FFC++0x3 line.long 0x0 "TMU_ROM_CORE0_END" hexmask.long 0x0 0.--31. 1. "END,TMU ROM end address" tree.end tree "R5SS1_TMU_ROM_CORE1" base ad:0x5302C000 group.long 0x0++0x3 line.long 0x0 "TMU_ROM_CORE1_START" hexmask.long 0x0 0.--31. 1. "START,TMU ROM start address" group.long 0x2FFC++0x3 line.long 0x0 "TMU_ROM_CORE1_END" hexmask.long 0x0 0.--31. 1. "END,TMU ROM end address" tree.end tree.end tree.end tree "R5SS1_VIM0" base ad:0x50F00000 rgroup.long 0x0++0x17 line.long 0x0 "VIM0_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIM0_INFO,The Info Register gives the configuration Inforrmation of this VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD" hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts" line.long 0x8 "VIM0_PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD" hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD" hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set." line.long 0xC "VIM0_PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD" hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set." hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD" hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set." line.long 0x10 "VIM0_IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid. This field indicates that one or more interrupts in Group M are mapped to IRQ unmasked and pending. Bit 0 corresponds to Group 0; Bit 1 corresponds to Group 1 etc. The interrupts associated with each group are.." line.long 0x14 "VIM0_FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid. This field indicates that one or more interrupts in Group M are mapped to FIQ unmasked and pending. Bit 0 corresponds to Group 0; Bit 1 corresponds to Group 1 etc. The interrupts associated with each group are.." group.long 0x18++0x7 line.long 0x0 "VIM0_IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ." hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true." rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3" line.long 0x4 "VIM0_FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ." hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true." rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3" rgroup.long 0x20++0x7 line.long 0x0 "VIM0_ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ." bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1" hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD" hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD" hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set." line.long 0x4 "VIM0_ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ." bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1" hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD" hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD" hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set." group.long 0x28++0xB line.long 0x0 "VIM0_IRQPRIMSK,The IRQ Priority Mask Register allows all IRQs of a particular priority to be enabled or disabled." hexmask.long.word 0x0 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x0 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - IRQs of this priority are enabled. 0 - IRQs of this priority are disabled." line.long 0x4 "VIM0_FIQPRIMSK,The FIQ Priority Mask Register allows all FIQs of a particular priority to be enabled or disabled." hexmask.long.word 0x4 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x4 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - FIQs of this priority are enabled. 0 - FIQs of this priority are disabled." line.long 0x8 "VIM0_DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ." hexmask.long 0x8 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address." rbitfld.long 0x8 0.--1. "RES23,RESERVE FIELD" "0,1,2,3" group.long 0x400++0x1F line.long 0x0 "VIM0_RAW_M,Group M Interrupt Raw Status/Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x4 "VIM0_STS_M,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h ." hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x8 "VIM0_INTR_EN_SET_M,Group M Interrupt Enabled Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xC "VIM0_INTER_EN_CLR_M,Group M Interrupt Enabled Clear Register (M is 0 to 7)Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x10 "VIM0_IRQSTS_M,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x14 "VIM0_FIQSTS_M,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x18 "VIM0_INTMAP_M,Group M Interrupt Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences [if enabled] for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt [default]1 FIQ Interrupt" line.long 0x1C "VIM0_INTTYPE_M,Group M Interrupt Type Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level [default] or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event [see.." group.long 0x1000++0x3 line.long 0x0 "VIM0_INTPRIORITY_Q,Interrupt Q Priority Register (where Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority [Default]" group.long 0x2000++0x3 line.long 0x0 "VIM0_INTVECTOR_Q,Interrupt Q Vector Register (Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address [Base Address + 0x18] or FIQ Vector Address [Base Address + 0x1C] and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" tree.end tree "R5SS1_VIM1" base ad:0x50F00000 rgroup.long 0x0++0x17 line.long 0x0 "VIM1_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIM1_INFO,The Info Register gives the configuration Inforrmation of this VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD" hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts" line.long 0x8 "VIM1_PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD" hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD" hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set." line.long 0xC "VIM1_PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD" hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set." hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD" hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set." line.long 0x10 "VIM1_IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid." line.long 0x14 "VIM1_FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid." group.long 0x18++0x7 line.long 0x0 "VIM1_IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ." hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true." rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3" line.long 0x4 "VIM1_FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ." hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true." rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3" rgroup.long 0x20++0x7 line.long 0x0 "VIM1_ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ." bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1" hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD" hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD" hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set." line.long 0x4 "VIM1_ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ." bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1" hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD" hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD" hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set." group.long 0x28++0xB line.long 0x0 "VIM1_IRQPRIMSK,The IRQ Priority Mask Register allows all IRQs of a particular priority to be enabled or disabled." hexmask.long.word 0x0 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x0 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - IRQs of this priority are enabled. 0 - IRQs of this priority are disabled." line.long 0x4 "VIM1_FIQPRIMSK,The FIQ Priority Mask Register allows all FIQs of a particular priority to be enabled or disabled." hexmask.long.word 0x4 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x4 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - FIQs of this priority are enabled. 0 - FIQs of this priority are disabled." line.long 0x8 "VIM1_DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ." hexmask.long 0x8 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address." rbitfld.long 0x8 0.--1. "RES23,RESERVE FIELD" "0,1,2,3" group.long 0x400++0x1F line.long 0x0 "VIM1_RAW_M,Group M Interrupt Raw Status/Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x4 "VIM1_STS_M,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h ." hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x8 "VIM1_INTR_EN_SET_M,Group M Interrupt Enabled Set Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xC "VIM1_INTER_EN_CLR_M,Group M Interrupt Enabled Clear Register (M is 0 to 7)Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x10 "VIM1_IRQSTS_M,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x14 "VIM1_FIQSTS_M,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x18 "VIM1_INTMAP_M,Group M Interrupt Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences [if enabled] for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt [default]1 FIQ Interrupt" line.long 0x1C "VIM1_INTTYPE_M,Group M Interrupt Type Map Register (M is 0 to 7) Address formula = 50F00000h + Offset + M x 20h." hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level [default] or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event [see.." group.long 0x1000++0x3 line.long 0x0 "VIM1_INTPRIORITY_Q,Interrupt Q Priority Register (where Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority [Default]" group.long 0x2000++0x3 line.long 0x0 "VIM1_INTVECTOR_Q,Interrupt Q Vector Register (Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h." hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address [Base Address + 0x18] or FIQ Vector Address [Base Address + 0x1C] and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" tree.end tree.end tree.end tree "RESOLVER" base ad:0x502CB000 rgroup.long 0x0++0x3 line.long 0x0 "RESOLVER_REGS_REVID,The Module and Version Register identifies the module identifier and revision of the RTL module." hexmask.long.word 0x0 16.--31. 1. "REG_MODULE_ID,Resolver module ID" hexmask.long.byte 0x0 11.--15. 1. "REG_RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "REG_MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REG_CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REG_MINOR_REVISION,Minor Revision." group.long 0x4++0x23 line.long 0x0 "RESOLVER_REGS_GLOBAL_CFG,Global Configuration." hexmask.long.byte 0x0 24.--31. 1. "SOC_WIDTH,Extension of Start Of Conversion(SOC) pulse width. Width = 40ns + 20ns*soc_width" hexmask.long.byte 0x0 16.--23. 1. "BURST_CNT,This defines the number of burst per sample 1 is no burst 2 is 2 samples which will get avg ect.. only valid values are 1 2 4 8 16 and 32" newline bitfld.long 0x0 12. "SINGLE_EN,1 single adc mode 0 diff adc mode" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MODE,This defines the mode of the resolver the user has 6 options to configure" newline bitfld.long 0x0 0. "MASTER_EN,Master Enable must leave disabled when cfg is updated0:Disabled1:Enabled When 0 it reset all counters SM SEQ ect.." "0,1" line.long 0x4 "RESOLVER_REGS_EXCIT_SAMPLE_CFG1,Excitation and Sample Configuration1." hexmask.long.word 0x4 16.--28. 1. "EXC_FREQ_PHASE_CFG,Defines when to start the8000counter to the SIN LUT this is one time per master_en 0 -> 1" hexmask.long.byte 0x4 8.--15. 1. "ADC_SAMPLE_RATE,ADC Over Sample Rate ( * 2) 0 = Reserved 1 = OSR2 .. 16 = OSR32 > 16 = Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "EXC_FREQ_SEL,Exciter Frequency select ( * 10) only 200-20k 100-10k and 50-5k is valid" line.long 0x8 "RESOLVER_REGS_EXCIT_SAMPLE_CFG2,Excitation and Sample Configuration2." bitfld.long 0x8 31. "PWM_SYNC_IN_EVENT,This tells SW we had a pwm_sync_in event after master_en is set w1tc but new start you must de-assert mater_en to re-arm" "0,1" bitfld.long 0x8 29. "PWM_SYNC_IN_EN,0 disable 1 enable the pwm_sync_in dep to start soc is" "0,1" newline hexmask.long.word 0x8 16.--28. 1. "PWM_TO_SOC_DLY_START,This delay start of SEQ SOC in steps of 800KHz this is a one time event per master_en 0 -> 1 first power up needs to be 500uS so reset state of 400 will hit this" hexmask.long.word 0x8 0.--12. 1. "PWM_PHASE_INFO,This is the latched value of the last pwm_sync_in risge event" line.long 0xC "RESOLVER_REGS_EXCIT_SAMPLE_CFG3,Excitation and Sample Configuration2." hexmask.long.byte 0xC 0.--7. 1. "EXC_AMP_CTRL,Defines the amplitude scale 249 is 100% > 250 is res" line.long 0x10 "RESOLVER_REGS_IRQSTATUS_RAW_SYS,Interrupt Raw Status Register For Resolver." bitfld.long 0x10 0. "SEQ_ERR,Raw status of error interrupt for seq_cmp_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" line.long 0x14 "RESOLVER_REGS_IRQSTATUS_SYS,Interrupt Status Register For Resolver." bitfld.long 0x14 0. "SEQ_ERR,Enabled status of error interrupt for seq_cmp_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" line.long 0x18 "RESOLVER_REGS_IRQENABLE_SET_SYS,Interrupt Enable Set Register For Resolver." bitfld.long 0x18 0. "SEQ_ERR,Enable set for seq_cmp_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x1C "RESOLVER_REGS_IRQENABLE_CLR_SYS,Interrupt Enable Clear Register For Resolver." bitfld.long 0x1C 0. "SEQ_ERR,Enable clr for seq_cmp_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" line.long 0x20 "RESOLVER_REGS_CAL_CFG,CAL Config." bitfld.long 0x20 8. "CAL_DONE,This tells SW CAL data is updated it will not do a new CAL sample until this is cleared" "0,1" hexmask.long.byte 0x20 4.--7. 1. "CAL_CHSEL,This defines the ADC channel for ADC0 and ADC1 For 263P bit 4 is reserved To determine correct value per SOC refer to the ADC Spec for that SOC" newline bitfld.long 0x20 0. "CAL_EN,Enable CAL each wrt of one will start cal can not start new one until the other is done and done is cleared to start a new cal just wrt a new one to this mmr" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "RESOLVER_REGS_CAL_OBS,CAL ADC0 and ADC1 Data." hexmask.long.word 0x0 16.--31. 1. "CAL_ADC1_DATA,Signed ADC1 Data from CAL channel sample if mode enables ie not mode 1 and mode 2" hexmask.long.word 0x0 0.--15. 1. "CAL_ADC0_DATA,Signed ADC0 Data from CAL channel sample" group.long 0x30++0x17 line.long 0x0 "RESOLVER_REGS_IRQSTATUS_RAW_SYS_0,Interrupt Raw Status Register for Core0." bitfld.long 0x0 24. "TRACK_LOCK_ERR0,Raw status of error interrupt for track_lock_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 23. "OFFSETDRIFT_COS_HI_ERR0,Raw status of error interrupt for offsetdrift_cos_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 22. "OFFSETDRIFT_COS_LO_ERR0,Raw status of error interrupt for offsetdrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 21. "OFFSETDRIFT_SIN_HI_ERR0,Raw status of error interrupt for offsetdrift_sin_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 20. "OFFSETDRIFT_SIN_LO_ERR0,Raw status of error interrupt for offsetdrift_sin_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 19. "GAINDRIFT_COS_HI_ERR0,Raw status of error interrupt for gaindrift_cos_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 18. "GAINDRIFT_COS_LO_ERR0,Raw status of error interrupt for gaindrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 17. "GAINDRIFT_SIN_HI_ERR0,Raw status of error interrupt for gaindrift_sin_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 16. "GAINDRIFT_SIN_LO_ERR0,Raw status of error interrupt for gaindrift_sin_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 15. "PHASEDRIFT_COS_HI_ERR0,Raw status of error interrupt for phasedrift_cos_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 14. "PHASEDRIFT_COS_LO_ERR0,Raw status of error interrupt for phasedrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 13. "EXCFREQDRIFT_HI_ERR0,Raw status of error interrupt for excfreqdrift_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 12. "EXCFREQDRIFT_COS_LO_ERR0,Raw status of error interrupt for excfreqdrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 11. "EXCFREQDRIFT_SIN_LO_ERR0,Raw status of error interrupt for excfreqdrift_sin_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR0,Raw status of error interrupt for sin_pos_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR0,Raw status of error interrupt for sin_neg_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 8. "COS_POS_ZC_PEAK_MISMATCH_ERR0,Raw status of error interrupt for cos_pos_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR0,Raw status of error interrupt for cos_neg_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 6. "SIN_MULTI_ZC_ERROR_ERR0,Raw status of error interrupt for sin_multi_zc_error_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. "COS_MULTI_ZC_ERROR_ERR0,Raw status of error interrupt for cos_multi_zc_error_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 4. "SINSQCOSSQ_HI_ERR0,Raw status of error interrupt for sinsqcossq_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. "SINSQCOSSQ_LO_ERR0,Raw status of error interrupt for sinsqcossq_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 2. "HIGHAMPLITUDE_SIN_FAULT_ERR0,Raw status of error interrupt for highamplitude_sin_fault_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. "HIGHAMPLITUDE_COS_FAULT_ERR0,Raw status of error interrupt for highamplitude_cos_fault_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 0. "LOWAMPLITUDE_ERR0,Raw status of error interrupt for lowamplitude_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" line.long 0x4 "RESOLVER_REGS_IRQSTATUS_SYS_0,Interrupt Status Register for Core0." bitfld.long 0x4 24. "TRACK_LOCK_ERR0,Enabled status of error interrupt for track_lock_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 23. "OFFSETDRIFT_COS_HI_ERR0,Enabled status of error interrupt for offsetdrift_cos_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 22. "OFFSETDRIFT_COS_LO_ERR0,Enabled status of error interrupt for offsetdrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 21. "OFFSETDRIFT_SIN_HI_ERR0,Enabled status of error interrupt for offsetdrift_sin_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 20. "OFFSETDRIFT_SIN_LO_ERR0,Enabled status of error interrupt for offsetdrift_sin_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 19. "GAINDRIFT_COS_HI_ERR0,Enabled status of error interrupt for gaindrift_cos_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 18. "GAINDRIFT_COS_LO_ERR0,Enabled status of error interrupt for gaindrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 17. "GAINDRIFT_SIN_HI_ERR0,Enabled status of error interrupt for gaindrift_sin_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 16. "GAINDRIFT_SIN_LO_ERR0,Enabled status of error interrupt for gaindrift_sin_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 15. "PHASEDRIFT_COS_HI_ERR0,Enabled status of error interrupt for phasedrift_cos_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 14. "PHASEDRIFT_COS_LO_ERR0,Enabled status of error interrupt for phasedrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 13. "EXCFREQDRIFT_HI_ERR0,Enabled status of error interrupt for excfreqdrift_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 12. "EXCFREQDRIFT_COS_LO_ERR0,Enabled status of error interrupt for excfreqdrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 11. "EXCFREQDRIFT_SIN_LO_ERR0,Enabled status of error interrupt for excfreqdrift_sin_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR0,Enabled status of error interrupt for sin_pos_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR0,Enabled status of error interrupt for sin_neg_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 8. "COS_POS_ZC_PEAK_MISMATCH_ERR0,Enabled status of error interrupt for cos_pos_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR0,Enabled status of error interrupt for cos_neg_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 6. "SIN_MULTI_ZC_ERROR_ERR0,Enabled status of error interrupt for sin_multi_zc_error_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 5. "COS_MULTI_ZC_ERROR_ERR0,Enabled status of error interrupt for cos_multi_zc_error_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 4. "SINSQCOSSQ_HI_ERR0,Enabled status of error interrupt for sinsqcossq_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 3. "SINSQCOSSQ_LO_ERR0,Enabled status of error interrupt for sinsqcossq_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 2. "HIGHAMPLITUDE_SIN_FAULT_ERR0,Enabled status of error interrupt for highamplitude_sin_fault_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 1. "HIGHAMPLITUDE_COS_FAULT_ERR0,Enabled status of error interrupt for highamplitude_cos_fault_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 0. "LOWAMPLITUDE_ERR0,Enabled status of error interrupt for lowamplitude_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" line.long 0x8 "RESOLVER_REGS_IRQENABLE_SET_SYS_0,Interrupt Enable Set Register for Core0." bitfld.long 0x8 24. "TRACK_LOCK_ERR0,Enable set for track_lock_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 23. "OFFSETDRIFT_COS_HI_ERR0,Enable set for offsetdrift_cos_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 22. "OFFSETDRIFT_COS_LO_ERR0,Enable set for offsetdrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 21. "OFFSETDRIFT_SIN_HI_ERR0,Enable set for offsetdrift_sin_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 20. "OFFSETDRIFT_SIN_LO_ERR0,Enable set for offsetdrift_sin_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 19. "GAINDRIFT_COS_HI_ERR0,Enable set for gaindrift_cos_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 18. "GAINDRIFT_COS_LO_ERR0,Enable set for gaindrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 17. "GAINDRIFT_SIN_HI_ERR0,Enable set for gaindrift_sin_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 16. "GAINDRIFT_SIN_LO_ERR0,Enable set for gaindrift_sin_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 15. "PHASEDRIFT_COS_HI_ERR0,Enable set for phasedrift_cos_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 14. "PHASEDRIFT_COS_LO_ERR0,Enable set for phasedrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 13. "EXCFREQDRIFT_HI_ERR0,Enable set for excfreqdrift_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 12. "EXCFREQDRIFT_COS_LO_ERR0,Enable set for excfreqdrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 11. "EXCFREQDRIFT_SIN_LO_ERR0,Enable set for excfreqdrift_sin_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR0,Enable set for sin_pos_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR0,Enable set for sin_neg_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 8. "COS_POS_ZC_PEAK_MISMATCH_ERR0,Enable set for cos_pos_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR0,Enable set for cos_neg_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 6. "SIN_MULTI_ZC_ERROR_ERR0,Enable set for sin_multi_zc_error_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 5. "COS_MULTI_ZC_ERROR_ERR0,Enable set for cos_multi_zc_error_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 4. "SINSQCOSSQ_HI_ERR0,Enable set for sinsqcossq_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 3. "SINSQCOSSQ_LO_ERR0,Enable set for sinsqcossq_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "HIGHAMPLITUDE_SIN_FAULT_ERR0,Enable set for highamplitude_sin_fault_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "HIGHAMPLITUDE_COS_FAULT_ERR0,Enable set for highamplitude_cos_fault_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "LOWAMPLITUDE_ERR0,Enable set for lowamplitude_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0xC "RESOLVER_REGS_IRQENABLE_CLR_SYS_0,Interrupt Enable Clear Register for Core0." bitfld.long 0xC 24. "TRACK_LOCK_ERR0,Enable clr for track_lock_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 23. "OFFSETDRIFT_COS_HI_ERR0,Enable clr for offsetdrift_cos_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 22. "OFFSETDRIFT_COS_LO_ERR0,Enable clr for offsetdrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 21. "OFFSETDRIFT_SIN_HI_ERR0,Enable clr for offsetdrift_sin_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 20. "OFFSETDRIFT_SIN_LO_ERR0,Enable clr for offsetdrift_sin_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 19. "GAINDRIFT_COS_HI_ERR0,Enable clr for gaindrift_cos_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 18. "GAINDRIFT_COS_LO_ERR0,Enable clr for gaindrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 17. "GAINDRIFT_SIN_HI_ERR0,Enable clr for gaindrift_sin_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 16. "GAINDRIFT_SIN_LO_ERR0,Enable clr for gaindrift_sin_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 15. "PHASEDRIFT_COS_HI_ERR0,Enable clr for phasedrift_cos_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 14. "PHASEDRIFT_COS_LO_ERR0,Enable clr for phasedrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 13. "EXCFREQDRIFT_HI_ERR0,Enable clr for excfreqdrift_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 12. "EXCFREQDRIFT_COS_LO_ERR0,Enable clr for excfreqdrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 11. "EXCFREQDRIFT_SIN_LO_ERR0,Enable clr for excfreqdrift_sin_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR0,Enable clr for sin_pos_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR0,Enable clr for sin_neg_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 8. "COS_POS_ZC_PEAK_MISMATCH_ERR0,Enable clr for cos_pos_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR0,Enable clr for cos_neg_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 6. "SIN_MULTI_ZC_ERROR_ERR0,Enable clr for sin_multi_zc_error_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 5. "COS_MULTI_ZC_ERROR_ERR0,Enable clr for cos_multi_zc_error_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 4. "SINSQCOSSQ_HI_ERR0,Enable clr for sinsqcossq_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 3. "SINSQCOSSQ_LO_ERR0,Enable clr for sinsqcossq_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "HIGHAMPLITUDE_SIN_FAULT_ERR0,Enable clr for highamplitude_sin_fault_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 1. "HIGHAMPLITUDE_COS_FAULT_ERR0,Enable clr for highamplitude_cos_fault_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "LOWAMPLITUDE_ERR0,Enable clr for lowamplitude_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" line.long 0x10 "RESOLVER_REGS_DC_OFF_CFG1_0,DC Offset Config1." hexmask.long.byte 0x10 28.--31. 1. "OFF_CAL_COEF2,Offset calibration coefficient2 dc offset" hexmask.long.byte 0x10 24.--27. 1. "OFF_CAL_COEF1,Offset calibration coefficient1 dc offset" newline hexmask.long.byte 0x10 12.--15. 1. "FILTORDER,NOT USED" bitfld.long 0x10 8. "BANDPASSFILTER_ON,To enable the bandpass filter before DC offset logix" "0,1" newline hexmask.long.byte 0x10 4.--7. 1. "OFFSET_HYSTERESIS,unsigned. Absolute hysteresis limit.4b(no decimal points) with the16bLSB ADC data coming16bto the resolver" bitfld.long 0x10 3. "OFFSET_CORR_ON,DC Offset Correction On" "0,1" newline bitfld.long 0x10 1. "COS_AUTO_OFFSET_EN,NOT_USED" "0,1" bitfld.long 0x10 0. "SIN_AUTO_OFFSET_EN,NOT USED" "0,1" line.long 0x14 "RESOLVER_REGS_DC_OFF_CFG2_0,DC Offset Config2." hexmask.long.word 0x14 16.--31. 1. "COS_MAN_OFF_ADJ,Signed Cos manual dc offset" hexmask.long.word 0x14 0.--15. 1. "SIN_MAN_OFF_ADJ,Signed Sin manual dc offset" rgroup.long 0x48++0x3 line.long 0x0 "RESOLVER_REGS_DC_OFF0,DC Offset." hexmask.long.word 0x0 16.--31. 1. "COS_OFFSET,Signed Cos auto dc offset" hexmask.long.word 0x0 0.--15. 1. "SIN_OFFSET,Signed Sin auto dc offset" group.long 0x4C++0x1B line.long 0x0 "RESOLVER_REGS_SAMPLE_CFG1_0,Ideal Sample Config1." hexmask.long.byte 0x0 24.--31. 1. "IDEAL_SAMPLE_TIME_OVR,Ideal sample count Override" hexmask.long.byte 0x0 16.--23. 1. "IDEAL_SAMPLE_TIME,Current Ideal sample count round down" newline bitfld.long 0x0 13.--15. "PEAK_AVG_LIMIT,2^n peakaveragelimit is how many times to average the ideal peak point: 0 to 7" "0,1,2,3,4,5,6,7" line.long 0x4 "RESOLVER_REGS_SAMPLE_CFG2_0,Ideal Sample Config2." hexmask.long.word 0x4 16.--31. 1. "SAMPLE_DET_THRESHOLD,Abs value the sig needs to be above to trigger the peak detect" hexmask.long.byte 0x4 8.--12. 1. "BANDPASSFILTERSAMPLEADJUST,Offset compensate the ideal phase time selection if bpass filter enabled note when you are in manual mode this value is not longer added" newline bitfld.long 0x4 0. "PEAK_AVG_LIMIT_DONE,Ideal sample count training completed Wrt 1 to Clr" "0,1" line.long 0x8 "RESOLVER_REGS_DEC_GF_CFG0,Dec GF Config." bitfld.long 0x8 25.--26. "IDEAL_SAMPLE_MODE,Ideal sample time detection: 0 autodetect 1 detect on sin channel 2 on cos channel 3 manual" "0,1,2,3" bitfld.long 0x8 24. "ENABLE_BOTTOM,This enables bottom wave to get used in the avg" "0,1" newline hexmask.long.word 0x8 0.--11. 1. "NOISE_THRESHOLD,Abs value if above use the current moving avg drop the new data" line.long 0xC "RESOLVER_REGS_PG_EST_CFG1_0,Phase and Gain Est for correction block Config1." hexmask.long.byte 0xC 28.--31. 1. "AGC_FILTER_COEF2,NOT USED" hexmask.long.byte 0xC 24.--27. 1. "AGC_FILTER_COEF1,NOT USED" newline bitfld.long 0xC 16. "AUTOPHASEGAINREADYDONE,Status of Auto Gain and Phase Est set when ready for each cycle wrt 1 to clear this has no effect to the correction logic" "0,1" hexmask.long.byte 0xC 4.--7. 1. "PHASEFILTCOEFF,NOT USED" newline hexmask.long.byte 0xC 0.--3. 1. "PG_TRAIN_LIMIT,^n pg_train_limit : 0 to 15" line.long 0x10 "RESOLVER_REGS_PG_EST_CFG2_0,Phase and Gain Est for correction block Config2." hexmask.long.word 0x10 16.--31. 1. "PHASECOSBYP0,Manual Phase Cos correction value" bitfld.long 0x10 3. "BYPASSPHASEGAINCORR0,Enables phase and gain est" "0,1" newline bitfld.long 0x10 2. "AUTOPHASECONTROL0,Enable Auto Phase correction" "0,1" bitfld.long 0x10 1. "AUTOGAINCONTROL0,Enable Auto Gain correction" "0,1" line.long 0x14 "RESOLVER_REGS_PG_EST_CFG3_0,Phase and Gain Est for correction block Config3." hexmask.long.word 0x14 16.--31. 1. "GAINCOSBYP0,Manual Gain Cos correction value" hexmask.long.word 0x14 0.--15. 1. "GAINSINBYP0,Manual Gain Sin correction value always pos" line.long 0x18 "RESOLVER_REGS_PG_EST_CFG4_0,Phase and Gain Est for correction block Config4." hexmask.long.word 0x18 16.--31. 1. "PHASEESTIMATEFINAL,Cos Auto Cal Phase correction value cal by est" hexmask.long.word 0x18 0.--15. 1. "PG_GLITCHTHRESHOLD,glitch threshold to estimate new rotation start in degrees" rgroup.long 0x68++0x7 line.long 0x0 "RESOLVER_REGS_PG_EST_CFG5_0,Phase and Gain Est for correction block Config5." hexmask.long 0x0 0.--31. 1. "COSSQACCFINAL0,Cos Auto Cal Gain correction value cal by est" line.long 0x4 "RESOLVER_REGS_PG_EST_CFG6_0,Phase and Gain Est for correction block Config6." hexmask.long 0x4 0.--31. 1. "SINSQACCFINAL0,Sin Auto Cal Gain correction value cal by est" group.long 0x70++0xB line.long 0x0 "RESOLVER_REGS_TRACK2_CFG1_0,Track2 Kp. Ki. Kd. Kvelfilt. Kffw. Boost Cfg1 ." hexmask.long.byte 0x0 24.--31. 1. "KVELFILT,Kvelfilt" hexmask.long.byte 0x0 16.--23. 1. "KD,NOT USED" newline hexmask.long.byte 0x0 8.--15. 1. "KI,Ki" line.long 0x4 "RESOLVER_REGS_TRACK2_CFG2_0,Track2 Feed Fwd Boost Kffw Cfg2." hexmask.long.byte 0x4 4.--11. 1. "KFFW,Kffw" bitfld.long 0x4 2. "EARLYESTIMATE,NOT USED" "0,1" newline bitfld.long 0x4 1. "BOOST,Boost Enable" "0,1" bitfld.long 0x4 0. "FEED_FWD_CORR,NOT USED" "0,1" line.long 0x8 "RESOLVER_REGS_TRACK2_CFG3_0,Track2 Cfg3." bitfld.long 0x8 24. "BOOSTVEL,0 disables and 1 enables accel/decel compensation for velocity calculation. boost also needs to be 1" "0,1" hexmask.long.byte 0x8 8.--15. 1. "KPDIV,Kp proportional path gain" newline hexmask.long.byte 0x8 0.--7. 1. "VBOOSTCOEFF,unsigned velocity accel/decel comp coefficient" rgroup.long 0x7C++0xB line.long 0x0 "RESOLVER_REGS_ANGLE_ARCTAN_0,Angle and Velocity from acrtan ." hexmask.long.word 0x0 0.--15. 1. "ANGLE,Signed(2s complement) Angle from arctan -180 to 0 to +180 scaled" line.long 0x4 "RESOLVER_REGS_ANGLE_TRACK2_0,Angle and Velocity from track2." hexmask.long.word 0x4 0.--15. 1. "ANGLE,Signed(2s complement) Angle from track2 -180 to 0 to +180 scaled" line.long 0x8 "RESOLVER_REGS_VELOCITY_TRACK2_0,Angle and Velocity from track2." hexmask.long 0x8 0.--31. 1. "VELOCITY,This register gives rotation frequency as a function of exc freq and double/single sample mode. Formula on matlab comment. (rotation frequency in Hz signed based on direction) = (velocity) * (1/Ts) * 1/2^32 Note: if it's top/bottom sampling .." group.long 0x88++0x3 line.long 0x0 "RESOLVER_REGS_OFFSET_0,SIN and COS Offset." group.long 0x98++0x3 line.long 0x0 "RESOLVER_REGS_DIAG1_0,Diag1 0" hexmask.long.word 0x0 16.--31. 1. "OFFSETDRIFT_THRESHOLD_LO,Signed Lo threshold to detect offset drift" hexmask.long.word 0x0 0.--15. 1. "OFFSETDRIFT_THRESHOLD_HI,Signed Hi threshold to detect offsetdrift" rgroup.long 0x9C++0x3 line.long 0x0 "RESOLVER_REGS_DIAG2_0,Diag2 0" hexmask.long.word 0x0 16.--31. 1. "EXCFREQDETECTED_COS,SW OBS Counts detected between zcs for cos excitation frequency" hexmask.long.word 0x0 0.--15. 1. "EXCFREQDETECTED_SIN,SW OBS Counts detected between zcs for sin excitation frequency" group.long 0xA0++0xB line.long 0x0 "RESOLVER_REGS_DIAG3_0,Diag3 0" hexmask.long.word 0x0 16.--31. 1. "EXCFREQDRIFT_THRESHOLD_LO,Lo threshold to detect excfreqdrift" hexmask.long.word 0x0 0.--15. 1. "EXCFREQDRIFT_THRESHOLD_HI,Hi threshold to detect excfreqdrift" line.long 0x4 "RESOLVER_REGS_DIAG4_0,Diag4 0" hexmask.long.byte 0x4 16.--23. 1. "EXCFREQDRIFT_GLITCHCOUNT,Counter limit how many times before issuing error" hexmask.long.word 0x4 0.--15. 1. "EXCFREQ_LEVEL,Threshold on ADC value to detect sin or cos zero crossings" line.long 0x8 "RESOLVER_REGS_DIAG5_0,Diag5 0" hexmask.long.byte 0x8 16.--23. 1. "LOWAMPLITUDE_GLITCHCOUNT,Counter limit how many times before issuing error" hexmask.long.word 0x8 0.--15. 1. "LOWAMPLITUDE_THRESHOLD,Hi threshold to detect lowamplitude. Both sin and cos need to be lower than this at the same time" rgroup.long 0xAC++0x3 line.long 0x0 "RESOLVER_REGS_DIAG6_0,Diag6 0" hexmask.long.word 0x0 16.--31. 1. "LOWAMPLITUDE_COS,Value of cos channel at the error trigger instant" hexmask.long.word 0x0 0.--15. 1. "LOWAMPLITUDE_SIN,Value of sin channel at the error trigger instant" group.long 0xB0++0x3 line.long 0x0 "RESOLVER_REGS_DIAG7_0,Diag7 0" hexmask.long.byte 0x0 16.--23. 1. "HIGHAMPLITUDE_GLITCHCOUNT,Counter limit how many times before issuing error" hexmask.long.word 0x0 0.--15. 1. "HIGHAMPLITUDE_THRESHOLD,Hi threshold to detect highamplitude. Both sin and cos need to be higher than this at the same time" rgroup.long 0xB4++0x3 line.long 0x0 "RESOLVER_REGS_DIAG8_0,Diag8 0" hexmask.long.word 0x0 16.--31. 1. "HIGHAMPLITUDE_COS,Value of cos channel at the error trigger instant" hexmask.long.word 0x0 0.--15. 1. "HIGHAMPLITUDE_SIN,Value of sin channel at the error trigger instant" group.long 0xB8++0x3 line.long 0x0 "RESOLVER_REGS_DIAG9_0,Diag9 0" hexmask.long.word 0x0 16.--31. 1. "SINSQCOSSQ_THRESHOLD_HI,High threshold to detect sinsqcossq. Sin^2+Cos^2 s needs to be lower than this" hexmask.long.word 0x0 0.--15. 1. "SINSQCOSSQ_THRESHOLD_LO,Low threshold to detect sinsqcossq. Sin^2+Cos^2 s needs to be lower than this" rgroup.long 0xBC++0x3 line.long 0x0 "RESOLVER_REGS_DIAG10_0,Diag10 0" hexmask.long.word 0x0 16.--31. 1. "SINSQCOSSQ_COSSQ,Actual cossq value on error trigger ether lo or hi triggered first event" hexmask.long.word 0x0 0.--15. 1. "SINSQCOSSQ_SINSQ,Actual sinsq value on error trigger ether lo or hi triggered first event" group.long 0xC0++0x7 line.long 0x0 "RESOLVER_REGS_DIAG11_0,Diag11 0" hexmask.long.byte 0x0 0.--7. 1. "SINSQCOSSQ_GLITCHCOUNT,Counter limit how many times before issuing error" line.long 0x4 "RESOLVER_REGS_DIAG12_0,Diag12 0" hexmask.long.word 0x4 16.--31. 1. "ROTPEAK_LEVEL,Peak level of rotational sin/cos when other signal is zero crossing" hexmask.long.word 0x4 0.--15. 1. "ROTFREQ_LEVEL,Zero crossing detection level of rotational sin/cos" rgroup.long 0xC8++0x3 line.long 0x0 "RESOLVER_REGS_DIAG13_0,Diag13 0" hexmask.long.byte 0x0 24.--31. 1. "COS_MULTI_ZC_ERROR_COUNT,Status of cos Capture number of faulty zcs" hexmask.long.byte 0x0 16.--23. 1. "SIN_MULTI_ZC_ERROR_COUNT,Status of sin Capture number of faulty zcs" newline bitfld.long 0x0 3. "COS_NEG_ZC_PEAK_MISMATCH_ERR,During negative cos zero-crossing cos is not + or - peak" "0,1" bitfld.long 0x0 2. "COS_POS_ZC_PEAK_MISMATCH_ERR,During positive cos zero-croscosg cos is not + or - peak" "0,1" newline bitfld.long 0x0 1. "SIN_NEG_ZC_PEAK_MISMATCH_ERR,During negative sin zero-crossing cos is not + or - peak" "0,1" bitfld.long 0x0 0. "SIN_POS_ZC_PEAK_MISMATCH_ERR,During positive sin zero-crossing cos is not + or - peak" "0,1" group.long 0xCC++0x13 line.long 0x0 "RESOLVER_REGS_DIAG14_0,Diag14 0" hexmask.long.word 0x0 16.--31. 1. "GAINDRIFT_THRESHOLD_LO,Lo threshold to detect cos_gain drift" hexmask.long.word 0x0 0.--15. 1. "GAINDRIFT_THRESHOLD_HI,Hi threshold to detect cos_gain drift" line.long 0x4 "RESOLVER_REGS_DIAG15_0,Diag15 0" hexmask.long.byte 0x4 0.--7. 1. "GAINDRIFT_GLITCHCOUNT,Counter limit how many times before issuing error" line.long 0x8 "RESOLVER_REGS_DIAG16_0,Diag16 0" hexmask.long.word 0x8 16.--31. 1. "PHASEDRIFT_THRESHOLD_LO,Lo threshold to detect cos phase drift" hexmask.long.word 0x8 0.--15. 1. "PHASEDRIFT_THRESHOLD_HI,Hi threshold to detect cos phase drift" line.long 0xC "RESOLVER_REGS_DIAG17_0,Diag17 0" hexmask.long.byte 0xC 0.--7. 1. "PHASEDRIFT_GLITCHCOUNT,Counter limit how many times before issuing error" line.long 0x10 "RESOLVER_REGS_DIAG18_0,Diag18 0" hexmask.long.byte 0x10 16.--23. 1. "TRACK_ERR_GLITCH_TIME,NOT USED" hexmask.long.word 0x10 0.--15. 1. "TRACK_ERR_THRESHOLD,Tracking error treshold" rgroup.long 0xEC++0xF line.long 0x0 "RESOLVER_REGS_OBS_ADC_0,Sw Obs adc data post latch and avg if enabled" hexmask.long.word 0x0 16.--31. 1. "COS_ADC,Signed SW Obs adc data post latch and avg if enabled" hexmask.long.word 0x0 0.--15. 1. "SIN_ADC,Signed SW Obs adc data post latch and avg if enabled" line.long 0x4 "RESOLVER_REGS_OBS_ADC_REC_0,Sw Obs adc data post recovered data. so post dec" hexmask.long.word 0x4 16.--31. 1. "COS_REC,Signed SW Ob sadc data post recovered data so post dec" hexmask.long.word 0x4 0.--15. 1. "SIN_REC,Signed SW Obs adc data post recovered data so post dec" line.long 0x8 "RESOLVER_REGS_OBS_ADC_DC_0,Sw Obs adc data post dc offset." hexmask.long.word 0x8 16.--31. 1. "COS_DC,Signed SW Obs adc data post dc offset" hexmask.long.word 0x8 0.--15. 1. "SIN_DC,Signed SW Obs adc data post dc offset" line.long 0xC "RESOLVER_REGS_OBS_ADC_PGC_0,Sw Obs post phase and gain correction ." hexmask.long.word 0xC 16.--31. 1. "COS_PGC,Signed SW Obs adc data post phase and gain correction" hexmask.long.word 0xC 0.--15. 1. "SIN_PGC,Signed SW Obs adc data post phase and gain correction" rgroup.long 0x100++0x13 line.long 0x0 "RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0,SW obs peak histogram buckets." hexmask.long.byte 0x0 24.--31. 1. "PEAKHISTOGRAM3_0,Ideal sample bucket3" hexmask.long.byte 0x0 16.--23. 1. "PEAKHISTOGRAM2_0,Ideal sample bucket2" newline hexmask.long.byte 0x0 8.--15. 1. "PEAKHISTOGRAM1_0,Ideal sample bucket1" hexmask.long.byte 0x0 0.--7. 1. "PEAKHISTOGRAM0_0,Ideal sample bucket0" line.long 0x4 "RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0,SW obs peak histogram buckets ." hexmask.long.byte 0x4 24.--31. 1. "PEAKHISTOGRAM7_0,Ideal sample bucket7" hexmask.long.byte 0x4 16.--23. 1. "PEAKHISTOGRAM6_0,Ideal sample bucket6" newline hexmask.long.byte 0x4 8.--15. 1. "PEAKHISTOGRAM5_0,Ideal sample bucket5" hexmask.long.byte 0x4 0.--7. 1. "PEAKHISTOGRAM4_0,Ideal sample bucket4" line.long 0x8 "RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0,SW obs peak histogram buckets ." hexmask.long.byte 0x8 24.--31. 1. "PEAKHISTOGRAM11_0,Ideal sample bucket11" hexmask.long.byte 0x8 16.--23. 1. "PEAKHISTOGRAM10_0,Ideal sample bucket10" newline hexmask.long.byte 0x8 8.--15. 1. "PEAKHISTOGRAM9_0,Ideal sample bucket9" hexmask.long.byte 0x8 0.--7. 1. "PEAKHISTOGRAM8_0,Ideal sample bucket8" line.long 0xC "RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0,SW obs peak histogram buckets ." hexmask.long.byte 0xC 24.--31. 1. "PEAKHISTOGRAM15_0,Ideal sample bucket15" hexmask.long.byte 0xC 16.--23. 1. "PEAKHISTOGRAM14_0,Ideal sample bucket14" newline hexmask.long.byte 0xC 8.--15. 1. "PEAKHISTOGRAM13_0,Ideal sample bucket13" hexmask.long.byte 0xC 0.--7. 1. "PEAKHISTOGRAM12_0,Ideal sample bucket12" line.long 0x10 "RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0,SW obs peak histogram buckets ." hexmask.long.byte 0x10 24.--31. 1. "PEAKHISTOGRAM19_0,Ideal sample bucket19" hexmask.long.byte 0x10 16.--23. 1. "PEAKHISTOGRAM18_0,Ideal sample bucket18" newline hexmask.long.byte 0x10 8.--15. 1. "PEAKHISTOGRAM17_0,Ideal sample bucket17" hexmask.long.byte 0x10 0.--7. 1. "PEAKHISTOGRAM16_0,Ideal sample bucket16" group.long 0x200++0x17 line.long 0x0 "RESOLVER_REGS_IRQSTATUS_RAW_SYS_1,Interrupt Raw Status Register for Core1." bitfld.long 0x0 24. "TRACK_LOCK_ERR1,Raw status of error interrupt for track_lock_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 23. "OFFSETDRIFT_COS_HI_ERR1,Raw status of error interrupt for offsetdrift_cos_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 22. "OFFSETDRIFT_COS_LO_ERR1,Raw status of error interrupt for offsetdrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 21. "OFFSETDRIFT_SIN_HI_ERR1,Raw status of error interrupt for offsetdrift_sin_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 20. "OFFSETDRIFT_SIN_LO_ERR1,Raw status of error interrupt for offsetdrift_sin_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 19. "GAINDRIFT_COS_HI_ERR1,Raw status of error interrupt for gaindrift_cos_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 18. "GAINDRIFT_COS_LO_ERR1,Raw status of error interrupt for gaindrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 17. "GAINDRIFT_SIN_HI_ERR1,Raw status of error interrupt for gaindrift_sin_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 16. "GAINDRIFT_SIN_LO_ERR1,Raw status of error interrupt for gaindrift_sin_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 15. "PHASEDRIFT_COS_HI_ERR1,Raw status of error interrupt for phasedrift_cos_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 14. "PHASEDRIFT_COS_LO_ERR1,Raw status of error interrupt for phasedrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 13. "EXCFREQDRIFT_HI_ERR1,Raw status of error interrupt for excfreqdrift_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 12. "EXCFREQDRIFT_COS_LO_ERR1,Raw status of error interrupt for excfreqdrift_cos_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 11. "EXCFREQDRIFT_SIN_LO_ERR1,Raw status of error interrupt for excfreqdrift_sin_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR1,Raw status of error interrupt for sin_pos_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR1,Raw status of error interrupt for sin_neg_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 8. "COS_POS_ZC_PEAK_MISMATCH_ERR1,Raw status of error interrupt for cos_pos_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR1,Raw status of error interrupt for cos_neg_zc_peak_mismatch_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 6. "SIN_MULTI_ZC_ERROR_ERR1,Raw status of error interrupt for sin_multi_zc_error_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. "COS_MULTI_ZC_ERROR_ERR1,Raw status of error interrupt for cos_multi_zc_error_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 4. "SINSQCOSSQ_HI_ERR1,Raw status of error interrupt for sinsqcossq_hi_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. "SINSQCOSSQ_LO_ERR1,Raw status of error interrupt for sinsqcossq_lo_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 2. "HIGHAMPLITUDE_SIN_FAULT_ERR1,Raw status of error interrupt for highamplitude_sin_fault_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. "HIGHAMPLITUDE_COS_FAULT_ERR1,Raw status of error interrupt for highamplitude_cos_fault_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x0 0. "LOWAMPLITUDE_ERR1,Raw status of error interrupt for lowamplitude_err Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" line.long 0x4 "RESOLVER_REGS_IRQSTATUS_SYS_1,Interrupt Status Register for Core1." bitfld.long 0x4 24. "TRACK_LOCK_ERR1,Enabled status of error interrupt for track_lock_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 23. "OFFSETDRIFT_COS_HI_ERR1,Enabled status of error interrupt for offsetdrift_cos_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 22. "OFFSETDRIFT_COS_LO_ERR1,Enabled status of error interrupt for offsetdrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 21. "OFFSETDRIFT_SIN_HI_ERR1,Enabled status of error interrupt for offsetdrift_sin_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 20. "OFFSETDRIFT_SIN_LO_ERR1,Enabled status of error interrupt for offsetdrift_sin_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 19. "GAINDRIFT_COS_HI_ERR1,Enabled status of error interrupt for gaindrift_cos_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 18. "GAINDRIFT_COS_LO_ERR1,Enabled status of error interrupt for gaindrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 17. "GAINDRIFT_SIN_HI_ERR1,Enabled status of error interrupt for gaindrift_sin_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 16. "GAINDRIFT_SIN_LO_ERR1,Enabled status of error interrupt for gaindrift_sin_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 15. "PHASEDRIFT_COS_HI_ERR1,Enabled status of error interrupt for phasedrift_cos_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 14. "PHASEDRIFT_COS_LO_ERR1,Enabled status of error interrupt for phasedrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 13. "EXCFREQDRIFT_HI_ERR1,Enabled status of error interrupt for excfreqdrift_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 12. "EXCFREQDRIFT_COS_LO_ERR1,Enabled status of error interrupt for excfreqdrift_cos_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 11. "EXCFREQDRIFT_SIN_LO_ERR1,Enabled status of error interrupt for excfreqdrift_sin_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR1,Enabled status of error interrupt for sin_pos_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR1,Enabled status of error interrupt for sin_neg_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 8. "COS_POS_ZC_PEAK_MISMATCH_ERR1,Enabled status of error interrupt for cos_pos_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR1,Enabled status of error interrupt for cos_neg_zc_peak_mismatch_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 6. "SIN_MULTI_ZC_ERROR_ERR1,Enabled status of error interrupt for sin_multi_zc_error_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 5. "COS_MULTI_ZC_ERROR_ERR1,Enabled status of error interrupt for cos_multi_zc_error_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 4. "SINSQCOSSQ_HI_ERR1,Enabled status of error interrupt for sinsqcossq_hi_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 3. "SINSQCOSSQ_LO_ERR1,Enabled status of error interrupt for sinsqcossq_lo_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 2. "HIGHAMPLITUDE_SIN_FAULT_ERR1,Enabled status of error interrupt for highamplitude_sin_fault_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x4 1. "HIGHAMPLITUDE_COS_FAULT_ERR1,Enabled status of error interrupt for highamplitude_cos_fault_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 0. "LOWAMPLITUDE_ERR1,Enabled status of error interrupt for lowamplitude_err Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" line.long 0x8 "RESOLVER_REGS_IRQENABLE_SET_SYS_1,Interrupt Enable Set Register for Core1." bitfld.long 0x8 24. "TRACK_LOCK_ERR1,Enable set for track_lock_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 23. "OFFSETDRIFT_COS_HI_ERR1,Enable set for offsetdrift_cos_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 22. "OFFSETDRIFT_COS_LO_ERR1,Enable set for offsetdrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 21. "OFFSETDRIFT_SIN_HI_ERR1,Enable set for offsetdrift_sin_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 20. "OFFSETDRIFT_SIN_LO_ERR1,Enable set for offsetdrift_sin_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 19. "GAINDRIFT_COS_HI_ERR1,Enable set for gaindrift_cos_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 18. "GAINDRIFT_COS_LO_ERR1,Enable set for gaindrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 17. "GAINDRIFT_SIN_HI_ERR1,Enable set for gaindrift_sin_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 16. "GAINDRIFT_SIN_LO_ERR1,Enable set for gaindrift_sin_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 15. "PHASEDRIFT_COS_HI_ERR1,Enable set for phasedrift_cos_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 14. "PHASEDRIFT_COS_LO_ERR1,Enable set for phasedrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 13. "EXCFREQDRIFT_HI_ERR1,Enable set for excfreqdrift_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 12. "EXCFREQDRIFT_COS_LO_ERR1,Enable set for excfreqdrift_cos_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 11. "EXCFREQDRIFT_SIN_LO_ERR1,Enable set for excfreqdrift_sin_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR1,Enable set for sin_pos_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR1,Enable set for sin_neg_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 8. "COS_POS_ZC_PEAK_MISMATCH_ERR1,Enable set for cos_pos_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR1,Enable set for cos_neg_zc_peak_mismatch_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 6. "SIN_MULTI_ZC_ERROR_ERR1,Enable set for sin_multi_zc_error_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 5. "COS_MULTI_ZC_ERROR_ERR1,Enable set for cos_multi_zc_error_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 4. "SINSQCOSSQ_HI_ERR1,Enable set for sinsqcossq_hi_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 3. "SINSQCOSSQ_LO_ERR1,Enable set for sinsqcossq_lo_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "HIGHAMPLITUDE_SIN_FAULT_ERR1,Enable set for highamplitude_sin_fault_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "HIGHAMPLITUDE_COS_FAULT_ERR1,Enable set for highamplitude_cos_fault_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "LOWAMPLITUDE_ERR1,Enable set for lowamplitude_err . Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0xC "RESOLVER_REGS_IRQENABLE_CLR_SYS_1,Interrupt Enable Clear Register for Core1." bitfld.long 0xC 24. "TRACK_LOCK_ERR1,Enable clr for track_lock_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 23. "OFFSETDRIFT_COS_HI_ERR1,Enable clr for offsetdrift_cos_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 22. "OFFSETDRIFT_COS_LO_ERR1,Enable clr for offsetdrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 21. "OFFSETDRIFT_SIN_HI_ERR1,Enable clr for offsetdrift_sin_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 20. "OFFSETDRIFT_SIN_LO_ERR1,Enable clr for offsetdrift_sin_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 19. "GAINDRIFT_COS_HI_ERR1,Enable clr for gaindrift_cos_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 18. "GAINDRIFT_COS_LO_ERR1,Enable clr for gaindrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 17. "GAINDRIFT_SIN_HI_ERR1,Enable clr for gaindrift_sin_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 16. "GAINDRIFT_SIN_LO_ERR1,Enable clr for gaindrift_sin_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 15. "PHASEDRIFT_COS_HI_ERR1,Enable clr for phasedrift_cos_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 14. "PHASEDRIFT_COS_LO_ERR1,Enable clr for phasedrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 13. "EXCFREQDRIFT_HI_ERR1,Enable clr for excfreqdrift_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 12. "EXCFREQDRIFT_COS_LO_ERR1,Enable clr for excfreqdrift_cos_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 11. "EXCFREQDRIFT_SIN_LO_ERR1,Enable clr for excfreqdrift_sin_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 10. "SIN_POS_ZC_PEAK_MISMATCH_ERR1,Enable clr for sin_pos_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 9. "SIN_NEG_ZC_PEAK_MISMATCH_ERR1,Enable clr for sin_neg_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 8. "COS_POS_ZC_PEAK_MISMATCH_ERR1,Enable clr for cos_pos_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 7. "COS_NEG_ZC_PEAK_MISMATCH_ERR1,Enable clr for cos_neg_zc_peak_mismatch_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 6. "SIN_MULTI_ZC_ERROR_ERR1,Enable clr for sin_multi_zc_error_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 5. "COS_MULTI_ZC_ERROR_ERR1,Enable clr for cos_multi_zc_error_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 4. "SINSQCOSSQ_HI_ERR1,Enable clr for sinsqcossq_hi_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 3. "SINSQCOSSQ_LO_ERR1,Enable clr for sinsqcossq_lo_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "HIGHAMPLITUDE_SIN_FAULT_ERR1,Enable clr for highamplitude_sin_fault_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 1. "HIGHAMPLITUDE_COS_FAULT_ERR1,Enable clr for highamplitude_cos_fault_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "LOWAMPLITUDE_ERR1,Enable clr for lowamplitude_err. Writing a 1 will disable the interrupt and set this bit as well as the corresponding Interrupt Enable set Register. Writing a 0 has no effect." "0,1" line.long 0x10 "RESOLVER_REGS_DC_OFF_CFG1_1,DC Offset Config1." hexmask.long.byte 0x10 28.--31. 1. "OFF_CAL_COEF2,Offset calibration coefficient2 dc offset" hexmask.long.byte 0x10 24.--27. 1. "OFF_CAL_COEF1,Offset calibration coefficient1 dc offset" newline hexmask.long.byte 0x10 12.--15. 1. "FILTORDER,NOT USED" bitfld.long 0x10 8. "BANDPASSFILTER_ON,To enable the bandpass filter before DC offset logix" "0,1" newline hexmask.long.byte 0x10 4.--7. 1. "OFFSET_HYSTERESIS,unsigned. Absolute hysteresis limit.4b(no decimal points) with the16bLSB ADC data coming16bto the resolver" bitfld.long 0x10 3. "OFFSET_CORR_ON,DC Offset Correction On" "0,1" newline bitfld.long 0x10 1. "COS_AUTO_OFFSET_EN,NOT_USED" "0,1" bitfld.long 0x10 0. "SIN_AUTO_OFFSET_EN,NOT USED" "0,1" line.long 0x14 "RESOLVER_REGS_DC_OFF_CFG2_1,DC Offset Config2." hexmask.long.word 0x14 16.--31. 1. "COS_MAN_OFF_ADJ,Signed Cos manual dc offset" hexmask.long.word 0x14 0.--15. 1. "SIN_MAN_OFF_ADJ,Signed Sin manual dc offset" rgroup.long 0x218++0x3 line.long 0x0 "RESOLVER_REGS_DC_OFF1,DC Offset." hexmask.long.word 0x0 16.--31. 1. "COS_OFFSET,Signed Cos auto dc offset" hexmask.long.word 0x0 0.--15. 1. "SIN_OFFSET,Signed Sin auto dc offset" group.long 0x21C++0x1B line.long 0x0 "RESOLVER_REGS_SAMPLE_CFG1_1,Ideal Sample Config1." hexmask.long.byte 0x0 24.--31. 1. "IDEAL_SAMPLE_TIME_OVR,Ideal sample count Overide" hexmask.long.byte 0x0 16.--23. 1. "IDEAL_SAMPLE_TIME,Current Ideal sample count round down" newline bitfld.long 0x0 13.--15. "PEAK_AVG_LIMIT,2^n peakaveragelimit is how many times to average the ideal peak point: 0 to 7" "0,1,2,3,4,5,6,7" line.long 0x4 "RESOLVER_REGS_SAMPLE_CFG2_1,Ideal Sample Config2." hexmask.long.word 0x4 16.--31. 1. "SAMPLE_DET_THRESHOLD,Abs value the sig needs to be above to trigger the peak detect" hexmask.long.byte 0x4 8.--12. 1. "BANDPASSFILTERSAMPLEADJUST,Offset compensate the ideal phase time selection if bpass filter enabled note when you are in manual mode this value is not longer added" newline bitfld.long 0x4 0. "PEAK_AVG_LIMIT_DONE,Ideal sample count training completed Wrt 1 to Clr" "0,1" line.long 0x8 "RESOLVER_REGS_DEC_GF_CFG1,Dec GF Config." bitfld.long 0x8 25.--26. "IDEAL_SAMPLE_MODE,Ideal sample time detection: 0 autodetect 1 detect on sin channel 2 on cos channel 3 manual" "0,1,2,3" bitfld.long 0x8 24. "ENABLE_BOTTOM,This enables bottom wave to get used in the avg" "0,1" newline hexmask.long.word 0x8 0.--11. 1. "NOISE_THRESHOLD,Abs value if above use the current moving avg drop the new data" line.long 0xC "RESOLVER_REGS_PG_EST_CFG1_1,Phase and Gain Est for correction block Config1." hexmask.long.byte 0xC 28.--31. 1. "AGC_FILTER_COEF2,NOT USED" hexmask.long.byte 0xC 24.--27. 1. "AGC_FILTER_COEF1,NOT USED" newline bitfld.long 0xC 16. "AUTOPHASEGAINREADYDONE,Status of Auto Gain and Phase Est set when ready for each cycle wrt 1 to clear this has no effect to the correction logic" "0,1" hexmask.long.byte 0xC 4.--7. 1. "PHASEFILTCOEFF,NOT USED" newline hexmask.long.byte 0xC 0.--3. 1. "PG_TRAIN_LIMIT,^n pg_train_limit : 0 to 15" line.long 0x10 "RESOLVER_REGS_PG_EST_CFG2_1,Phase and Gain Est for correction block Config2." hexmask.long.word 0x10 16.--31. 1. "PHASECOSBYP1,Manual Phase Cos correction value" bitfld.long 0x10 3. "BYPASSPHASEGAINCORR1,Enables phase and gain est" "0,1" newline bitfld.long 0x10 2. "AUTOPHASECONTROL1,Enable Auto Phase correction" "0,1" bitfld.long 0x10 1. "AUTOGAINCONTROL1,Enable Auto Gain correction" "0,1" line.long 0x14 "RESOLVER_REGS_PG_EST_CFG3_1,Phase and Gain Est for correction block Config3." hexmask.long.word 0x14 16.--31. 1. "GAINCOSBYP1,Manual Gain Cos correction value" hexmask.long.word 0x14 0.--15. 1. "GAINSINBYP1,Manual Gain Sin correction value always pos" line.long 0x18 "RESOLVER_REGS_PG_EST_CFG4_1,Phase and Gain Est for correction block Config4." hexmask.long.word 0x18 16.--31. 1. "PHASEESTIMATEFINAL,Cos Auto Cal Phase correction value cal by est" hexmask.long.word 0x18 0.--15. 1. "PG_GLITCHTHRESHOLD,glitch threshold to estimate new rotation start in degrees" rgroup.long 0x238++0x7 line.long 0x0 "RESOLVER_REGS_PG_EST_CFG5_1,Phase and Gain Est for correction block Config5." hexmask.long 0x0 0.--31. 1. "COSSQACCFINAL1,Cos Auto Cal Gain correction value cal by est" line.long 0x4 "RESOLVER_REGS_PG_EST_CFG6_1,Phase and Gain Est for correction block Config6." hexmask.long 0x4 0.--31. 1. "SINSQACCFINAL1,Sin Auto Cal Gain correction value cal by est" group.long 0x240++0xB line.long 0x0 "RESOLVER_REGS_TRACK2_CFG1_1,Track2 Kp. Ki. Kd. Kvelfilt. Kffw. Boost Cfg1 ." hexmask.long.byte 0x0 24.--31. 1. "KVELFILT,Kvelfilt" hexmask.long.byte 0x0 16.--23. 1. "KD,NOT USED" newline hexmask.long.byte 0x0 8.--15. 1. "KI,Ki" line.long 0x4 "RESOLVER_REGS_TRACK2_CFG2_1,Track2 Feed Fwd Boost Kffw Cfg2." hexmask.long.byte 0x4 4.--11. 1. "KFFW,Kffw" bitfld.long 0x4 2. "EARLYESTIMATE,NOT USED" "0,1" newline bitfld.long 0x4 1. "BOOST,Boost Enable" "0,1" bitfld.long 0x4 0. "FEED_FWD_CORR,NOT USED" "0,1" line.long 0x8 "RESOLVER_REGS_TRACK2_CFG3_1,Track2 Cfg3." bitfld.long 0x8 24. "BOOSTVEL,0 disables and 1 enables accel/decel compensation for velocity calculation. boost also needs to be 1" "0,1" hexmask.long.byte 0x8 8.--15. 1. "KPDIV,Kp proportional path gain" newline hexmask.long.byte 0x8 0.--7. 1. "VBOOSTCOEFF,unsigned velocity accel/decel comp coefficient" rgroup.long 0x24C++0xB line.long 0x0 "RESOLVER_REGS_ANGLE_ARCTAN_1,Angle and Velocity from acrtan ." hexmask.long.word 0x0 0.--15. 1. "ANGLE,Signed(2s complement) Angle from arctan -180 to 0 to +180 scaled" line.long 0x4 "RESOLVER_REGS_ANGLE_TRACK2_1,Angle and Velocity from track2." hexmask.long.word 0x4 0.--15. 1. "ANGLE,Signed(2s complement) Angle from track2 -180 to 0 to +180 scaled" line.long 0x8 "RESOLVER_REGS_VELOCITY_TRACK2_1,Angle and Velocity from track2." hexmask.long 0x8 0.--31. 1. "VELOCITY,This register gives rotation frequency as a function of exc freq and double/single sample mode. Formula on matlab comment. (rotation frequency in Hz signed based on direction) = (velocity) * (1/Ts) * 1/2^32 Note: if it's top/bottom sampling .." group.long 0x258++0x3 line.long 0x0 "RESOLVER_REGS_OFFSET_1,SIN and COS Offset." group.long 0x268++0x3 line.long 0x0 "RESOLVER_REGS_DIAG1_1,Diag1 1" hexmask.long.word 0x0 16.--31. 1. "OFFSETDRIFT_THRESHOLD_LO,Signed Lo threshold to detect offset drift" hexmask.long.word 0x0 0.--15. 1. "OFFSETDRIFT_THRESHOLD_HI,Signed Hi threshold to detect offsetdrift" rgroup.long 0x26C++0x3 line.long 0x0 "RESOLVER_REGS_DIAG2_1,Diag2 1" hexmask.long.word 0x0 16.--31. 1. "EXCFREQDETECTED_COS,SW OBS Counts detected between zcs for cos excitation frequency" hexmask.long.word 0x0 0.--15. 1. "EXCFREQDETECTED_SIN,SW OBS Counts detected between zcs for sin excitation frequency" group.long 0x270++0xB line.long 0x0 "RESOLVER_REGS_DIAG3_1,Diag3 1" hexmask.long.word 0x0 16.--31. 1. "EXCFREQDRIFT_THRESHOLD_LO,Lo threshold to detect excfreqdrift" hexmask.long.word 0x0 0.--15. 1. "EXCFREQDRIFT_THRESHOLD_HI,Hi threshold to detect excfreqdrift" line.long 0x4 "RESOLVER_REGS_DIAG4_1,Diag4 1" hexmask.long.byte 0x4 16.--23. 1. "EXCFREQDRIFT_GLITCHCOUNT,Counter limit how many times before issuing error" hexmask.long.word 0x4 0.--15. 1. "EXCFREQ_LEVEL,Threshold on ADC value to detect sin or cos zero crossings" line.long 0x8 "RESOLVER_REGS_DIAG5_1,Diag5 1" hexmask.long.byte 0x8 16.--23. 1. "LOWAMPLITUDE_GLITCHCOUNT,Counter limit how many times before issuing error" hexmask.long.word 0x8 0.--15. 1. "LOWAMPLITUDE_THRESHOLD,Hi threshold to detect lowamplitude. Both sin and cos need to be lower than this at the same time" rgroup.long 0x27C++0x3 line.long 0x0 "RESOLVER_REGS_DIAG6_1,Diag6 1" hexmask.long.word 0x0 16.--31. 1. "LOWAMPLITUDE_COS,Value of cos channel at the error trigger instant" hexmask.long.word 0x0 0.--15. 1. "LOWAMPLITUDE_SIN,Value of sin channel at the error trigger instant" group.long 0x280++0x3 line.long 0x0 "RESOLVER_REGS_DIAG7_1,Diag7 1" hexmask.long.byte 0x0 16.--23. 1. "HIGHAMPLITUDE_GLITCHCOUNT,Counter limit how many times before issuing error" hexmask.long.word 0x0 0.--15. 1. "HIGHAMPLITUDE_THRESHOLD,Hi threshold to detect highamplitude. Both sin and cos need to be higher than this at the same time" rgroup.long 0x284++0x3 line.long 0x0 "RESOLVER_REGS_DIAG8_1,Diag8 1" hexmask.long.word 0x0 16.--31. 1. "HIGHAMPLITUDE_COS,Value of cos channel at the error trigger instant" hexmask.long.word 0x0 0.--15. 1. "HIGHAMPLITUDE_SIN,Value of sin channel at the error trigger instant" group.long 0x288++0x3 line.long 0x0 "RESOLVER_REGS_DIAG9_1,Diag9 1" hexmask.long.word 0x0 16.--31. 1. "SINSQCOSSQ_THRESHOLD_HI,High threshold to detect sinsqcossq. Sin^2+Cos^2 s needs to be lower than this" hexmask.long.word 0x0 0.--15. 1. "SINSQCOSSQ_THRESHOLD_LO,Low threshold to detect sinsqcossq. Sin^2+Cos^2 s needs to be lower than this" rgroup.long 0x28C++0x3 line.long 0x0 "RESOLVER_REGS_DIAG10_1,Diag10 1" hexmask.long.word 0x0 16.--31. 1. "SINSQCOSSQ_COSSQ,Actual cossq value on error trigger ether lo or hi triggered first event" hexmask.long.word 0x0 0.--15. 1. "SINSQCOSSQ_SINSQ,Actual sinsq value on error trigger ether lo or hi triggered first event" group.long 0x290++0x7 line.long 0x0 "RESOLVER_REGS_DIAG11_1,Diag11 1" hexmask.long.byte 0x0 0.--7. 1. "SINSQCOSSQ_GLITCHCOUNT,Counter limit how many times before issuing error" line.long 0x4 "RESOLVER_REGS_DIAG12_1,Diag12 1" hexmask.long.word 0x4 16.--31. 1. "ROTPEAK_LEVEL,Peak level of rotational sin/cos when other signal is zero crossing" hexmask.long.word 0x4 0.--15. 1. "ROTFREQ_LEVEL,Zero crossing detection level of rotational sin/cos" rgroup.long 0x298++0x3 line.long 0x0 "RESOLVER_REGS_DIAG13_1,Diag13 1" hexmask.long.byte 0x0 24.--31. 1. "COS_MULTI_ZC_ERROR_COUNT,Status of cos Capture number of faulty zcs" hexmask.long.byte 0x0 16.--23. 1. "SIN_MULTI_ZC_ERROR_COUNT,Status of sin Capture number of faulty zcs" newline bitfld.long 0x0 3. "COS_NEG_ZC_PEAK_MISMATCH_ERR,During negative cos zero-crossing cos is not + or - peak" "0,1" bitfld.long 0x0 2. "COS_POS_ZC_PEAK_MISMATCH_ERR,During positive cos zero-croscosg cos is not + or - peak" "0,1" newline bitfld.long 0x0 1. "SIN_NEG_ZC_PEAK_MISMATCH_ERR,During negative sin zero-crossing cos is not + or - peak" "0,1" bitfld.long 0x0 0. "SIN_POS_ZC_PEAK_MISMATCH_ERR,During positive sin zero-crossing cos is not + or - peak" "0,1" group.long 0x29C++0x13 line.long 0x0 "RESOLVER_REGS_DIAG14_1,Diag14 1" hexmask.long.word 0x0 16.--31. 1. "GAINDRIFT_THRESHOLD_LO,Lo threshold to detect cos_gain drift" hexmask.long.word 0x0 0.--15. 1. "GAINDRIFT_THRESHOLD_HI,Hi threshold to detect cos_gain drift" line.long 0x4 "RESOLVER_REGS_DIAG15_1,Diag15 1" hexmask.long.byte 0x4 0.--7. 1. "GAINDRIFT_GLITCHCOUNT,Counter limit how many times before issuing error" line.long 0x8 "RESOLVER_REGS_DIAG16_1,Diag16 1" hexmask.long.word 0x8 16.--31. 1. "PHASEDRIFT_THRESHOLD_LO,Lo threshold to detect cos phase drift" hexmask.long.word 0x8 0.--15. 1. "PHASEDRIFT_THRESHOLD_HI,Hi threshold to detect cos phase drift" line.long 0xC "RESOLVER_REGS_DIAG17_1,Diag17 1" hexmask.long.byte 0xC 0.--7. 1. "PHASEDRIFT_GLITCHCOUNT,Counter limit how many times before issuing error" line.long 0x10 "RESOLVER_REGS_DIAG18_1,Diag18 1" hexmask.long.byte 0x10 16.--23. 1. "TRACK_ERR_GLITCH_TIME,NOT USED" hexmask.long.word 0x10 0.--15. 1. "TRACK_ERR_THRESHOLD,Tracking error treshold" rgroup.long 0x2BC++0xF line.long 0x0 "RESOLVER_REGS_OBS_ADC_1,Sw Obs adc data post latch and avg if enabled" hexmask.long.word 0x0 16.--31. 1. "COS_ADC,Signed SW Obs adc data post latch and avg if enabled" hexmask.long.word 0x0 0.--15. 1. "SIN_ADC,Signed SW Obs adc data post latch and avg if enabled" line.long 0x4 "RESOLVER_REGS_OBS_ADC_REC_1,Sw Obs adc data post recovered data. so post dec" hexmask.long.word 0x4 16.--31. 1. "COS_REC,Signed SW Ob sadc data post recovered data so post dec" hexmask.long.word 0x4 0.--15. 1. "SIN_REC,Signed SW Obs adc data post recovered data so post dec" line.long 0x8 "RESOLVER_REGS_OBS_ADC_DC_1,Sw Obs adc data post dc offset." hexmask.long.word 0x8 16.--31. 1. "COS_DC,Signed SW Obs adc data post dc offset" hexmask.long.word 0x8 0.--15. 1. "SIN_DC,Signed SW Obs adc data post dc offset" line.long 0xC "RESOLVER_REGS_OBS_ADC_PGC_1,Sw Obs post phase and gain correction ." hexmask.long.word 0xC 16.--31. 1. "COS_PGC,Signed SW Obs adc data post phase and gain correction" hexmask.long.word 0xC 0.--15. 1. "SIN_PGC,Signed SW Obs adc data post phase and gain correction" rgroup.long 0x2D0++0x13 line.long 0x0 "RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_1,SW obs peak histogram buckets." hexmask.long.byte 0x0 24.--31. 1. "PEAKHISTOGRAM3_1,Ideal sample bucket3" hexmask.long.byte 0x0 16.--23. 1. "PEAKHISTOGRAM2_1,Ideal sample bucket2" newline hexmask.long.byte 0x0 8.--15. 1. "PEAKHISTOGRAM1_1,Ideal sample bucket1" hexmask.long.byte 0x0 0.--7. 1. "PEAKHISTOGRAM0_1,Ideal sample bucket0" line.long 0x4 "RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_1,SW obs peak histogram buckets ." hexmask.long.byte 0x4 24.--31. 1. "PEAKHISTOGRAM7_1,Ideal sample bucket7" hexmask.long.byte 0x4 16.--23. 1. "PEAKHISTOGRAM6_1,Ideal sample bucket6" newline hexmask.long.byte 0x4 8.--15. 1. "PEAKHISTOGRAM5_1,Ideal sample bucket5" hexmask.long.byte 0x4 0.--7. 1. "PEAKHISTOGRAM4_1,Ideal sample bucket4" line.long 0x8 "RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_1,SW obs peak histogram buckets ." hexmask.long.byte 0x8 24.--31. 1. "PEAKHISTOGRAM11_1,Ideal sample bucket11" hexmask.long.byte 0x8 16.--23. 1. "PEAKHISTOGRAM10_1,Ideal sample bucket10" newline hexmask.long.byte 0x8 8.--15. 1. "PEAKHISTOGRAM9_1,Ideal sample bucket9" hexmask.long.byte 0x8 0.--7. 1. "PEAKHISTOGRAM8_1,Ideal sample bucket8" line.long 0xC "RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_1,SW obs peak histogram buckets ." hexmask.long.byte 0xC 24.--31. 1. "PEAKHISTOGRAM15_1,Ideal sample bucket15" hexmask.long.byte 0xC 16.--23. 1. "PEAKHISTOGRAM14_1,Ideal sample bucket14" newline hexmask.long.byte 0xC 8.--15. 1. "PEAKHISTOGRAM13_1,Ideal sample bucket13" hexmask.long.byte 0xC 0.--7. 1. "PEAKHISTOGRAM12_1,Ideal sample bucket12" line.long 0x10 "RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_1,SW obs peak histogram buckets ." hexmask.long.byte 0x10 24.--31. 1. "PEAKHISTOGRAM19_1,Ideal sample bucket19" hexmask.long.byte 0x10 16.--23. 1. "PEAKHISTOGRAM18_1,Ideal sample bucket18" newline hexmask.long.byte 0x10 8.--15. 1. "PEAKHISTOGRAM17_1,Ideal sample bucket17" hexmask.long.byte 0x10 0.--7. 1. "PEAKHISTOGRAM16_1,Ideal sample bucket16" tree.end tree "RL2" base ad:0x0 tree "RL2_R5SS0" tree "RL2_R5SS0_CORE0" base ad:0x53212000 rgroup.long 0x0++0x3 line.long 0x0 "RL2_MOD_VER,The Module and Version Register identifies the module identifier and revision of the RL2 module." bitfld.long 0x0 30.--31. "SCHEME,Module Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Module Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,RL2 module ID." hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." group.long 0x4++0x3 line.long 0x0 "RL2_L2_CTRL,The control register defines the size of the remote cache data storage memory to use and whether the L2 is enabled." bitfld.long 0x0 31. "ENABLE,The enable field determines whether the L2 is enabled or not. Setting the enable from a 0 to 1 restarts the cache0:Disabled1:Enabled" "0,1" bitfld.long 0x0 0.--2. "SIZE,The size field determines the size of the remote cache data storage memory that is currently active. This field can be change dynamically but will cause the entire cache to be invalidated when inflight transactions have completed. Changing the size.." "0: 8KB1:16KB2:32KB3:64KB4:128KB5:256KB,?,?,?,?,?,?,?" rgroup.long 0x8++0x3 line.long 0x0 "RL2_L2_STS,The Status register displays the state of the RL2 module." bitfld.long 0x0 31. "OK_TO_GO,The ok_to_go status bit indicates the Tag/LRU Ram has been initialized and the cache is in an operable state." "0,1" group.long 0x10++0x3 line.long 0x0 "RL2_L2_LO,The L2 Low address Least Significant word defines the least significant portion of the low cache address. The RL2 cache can cache a range of 1 to 16MB of cache as defined by L2_LO>=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_LO_LSW,The address_lo_lsw defines the L2 low address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be zero." group.long 0x18++0x3 line.long 0x0 "RL2_L2_HI,The L2 High address Least Significant word defines the least significant portion of the high cache address. The RL2 cache can cache a range of 1 to 16MB of cache as defined by L2_LO>=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_HI_LSW,The address_hi_lsw defines the high address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be ones." group.long 0x78++0x17 line.long 0x0 "RL2_L2HC,The L2 HIT Counter register holds the number of L2 Hits to the Remote data storage memory." hexmask.long 0x0 0.--31. 1. "HIT,The hit Counts the number of hits to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x4 "RL2_L2MC,The L2 MISS Counter register holds the number of L2 Misses to the Remote data storage memory." hexmask.long 0x4 0.--31. 1. "MISS,The miss Counts the number of misses to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x8 "RL2_IRQSTATUS_RAW,The Interrupt Raw Status Register holds the raw status of the FLC/RL2 status/error interrupts." bitfld.long 0x8 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to set the flc_don status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC remote range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_wrerr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_rderr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_hit status for diagnostic purposes. Writing a 0 has no.." "0,1" newline bitfld.long 0x8 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_err status for diagnostic purposes. Writing a 0 has no effect." "0,1" line.long 0xC "RL2_IRQSTATUS_MSK,The Interrupt Masked Status Register holds the masked status for the FLC/RL2 status/error interrupts. Writing to this register will EOI the interrupt. that is if another interrupt is pending. a new pulse interrupt will be generated." bitfld.long 0xC 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to clear the flc_don status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect to this field." "0,1" bitfld.long 0xC 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_wrerr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_rderr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_hit status after interrupt has been serviced (raw status.." "0,1" newline bitfld.long 0xC 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_err status after interrupt has been serviced (raw status gets cleared .." "0,1" line.long 0x10 "RL2_IRQENABLE_SET,The Interrupt Enable Set Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x10 4. "EN_FLC_DON,Interrupt Enable Set for en_flc_don status bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 3. "EN_FLC_WRERR,Interrupt Enable Set for en_flc_wrerr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "EN_FLC_RDERR,Interrupt Enable Set for en_flc_rderr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 1. "EN_WR_HIT,Interrupt Enable Set for wr_hit error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "EN_WR_ERR,Interrupt Enable Set for wr_err error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x14 "RL2_IRQENABLE_CLR,The Interrupt Enable Clear Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x14 4. "EN_FLC_DON,Interrupt Enable Clear for flc_don status bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 3. "EN_FLC_WRERR,Interrupt Enable Clear for flc_wrerr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "EN_FLC_RDERR,Interrupt Enable Clear for flc_rderr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 1. "EN_WR_HIT,Interrupt Enable Clear for wr_hit error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "EN_WR_ERR,Interrupt Enable Clear for wr_err error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" group.long 0x104++0x3 line.long 0x0 "RL2_FLC_CFG,The FLC Config Register contains the configuration values for the FLC." bitfld.long 0x0 31. "FIFO_BYPASS,Setting this bit will cause the write to remote memory for a cache miss or FLC return to forces stalls on the read returns if any other data phase for a cache miss or FLC return is received. This can cause stalls on the write to force stalls.." "0,1" bitfld.long 0x0 24.--26. "FLC_EXCNT,The number of extra requests the FLC can send. The maximum value is 4 anything greater will default to 4. This value + 1 is the number of Reassembly Buffers used for FLC so if cache misses needed to be supported this value should be set to 4 or.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "ASMNUM,Number of Reassembly Buffer supported" hexmask.long.byte 0x0 0.--7. 1. "RANGES,Number of FLC ranges supported" rgroup.long 0x108++0x3 line.long 0x0 "RL2_FLC_STS,The FLC Status Register will indicate the state of the FLC completion." hexmask.long.byte 0x0 0.--3. 1. "CPYCMP,The cpycmp indicates which FLC range is complete. Each bit index indicates the FLC range is complete." rgroup.long 0x110++0x7 line.long 0x0 "RL2_FLC_DBG0,The FLC Debug 0 Register holds the debug state of the FLC." bitfld.long 0x0 31. "FLCIF,The flcif indicates a FLC operation is in flight." "0,1" bitfld.long 0x0 24.--26. "FLC_OUT_CNT,The number of read requests the FLC operation has in flight." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--1. "CURFLC,The curflc indicates which FLC range is in flight." "0,1,2,3" line.long 0x4 "RL2_FLC_DBG1,The FLC Debug 1 Register holds the debug address of the FLC." hexmask.long 0x4 0.--31. 1. "FLCADR,The flcadr indicates the next FLC address to be processed if still in flight. That is all addresses less than this address have been transferred. This address is used for FLC hit when the particular FLC range is in flight. That is.." rgroup.long 0x204++0x3 line.long 0x0 "RL2_RAT_CFG,The RAT Config Register contains the configuration values for the RAT." hexmask.long.byte 0x0 16.--23. 1. "ADDR_WIDTH,Number of address bits" hexmask.long.byte 0x0 0.--7. 1. "REGIONS,Number of regions" group.long 0x20++0x3 line.long 0x0 "RL2_REM_ADR_j,The REMote 'n' Address Least Significant word defines the least significant portion of the Remote address for remote cache data storage memory 0. The RL2 cache use up to three remote cache data storage memory ranges to place the L2 data.." hexmask.long.tbyte 0x0 11.--31. 1. "ADR_LSW,The rem0_adr_lsw defines the LSW of the remote cache data storage memory address[31:11] range 'n' for the RL2 to use for the cache. The remaining bits 10:0 are assumed to be zero." group.long 0x28++0x3 line.long 0x0 "RL2_REM_LEN_j,The Remote 'n' length defines the amount of remote cache data storage memory in 64 byte aligned quanta used starting from the REMote 'n' Address. The RL2 consumes remote cache data storage memory ranges in numeric order. Range 0 is consumed.." hexmask.long.word 0x0 6.--18. 1. "LEN,The rem0_len field specifies the length of the remote cache data storage memory 'n' to use for the RL2 cache in 64 byte quanta That is the number of bytes specified in the remote cache data storage memory range 'n' is (rem0_len X 64). Note: Any.." group.long 0x120++0x3 line.long 0x0 "RL2_FLC_LO_j,The FLC Low 'n' address defines the FLC lo address for FLC range 0. The FLC range is defined by FLC_LO0>=FLCrange=FLCrange=FLCrange=FLCrange=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_LO_LSW,The address_lo_lsw defines the L2 low address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be zero." group.long 0x18++0x3 line.long 0x0 "RL2_L2_HI,The L2 High address Least Significant word defines the least significant portion of the high cache address. The RL2 cache can cache a range of 1 to 16MB of cache as defined by L2_LO>=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_HI_LSW,The address_hi_lsw defines the high address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be ones." group.long 0x78++0x17 line.long 0x0 "RL2_L2HC,The L2 HIT Counter register holds the number of L2 Hits to the Remote data storage memory." hexmask.long 0x0 0.--31. 1. "HIT,The hit Counts the number of hits to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x4 "RL2_L2MC,The L2 MISS Counter register holds the number of L2 Misses to the Remote data storage memory." hexmask.long 0x4 0.--31. 1. "MISS,The miss Counts the number of misses to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x8 "RL2_IRQSTATUS_RAW,The Interrupt Raw Status Register holds the raw status of the FLC/RL2 status/error interrupts." bitfld.long 0x8 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to set the flc_don status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC remote range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_wrerr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_rderr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_hit status for diagnostic purposes. Writing a 0 has no.." "0,1" newline bitfld.long 0x8 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_err status for diagnostic purposes. Writing a 0 has no effect." "0,1" line.long 0xC "RL2_IRQSTATUS_MSK,The Interrupt Masked Status Register holds the masked status for the FLC/RL2 status/error interrupts. Writing to this register will EOI the interrupt. that is if another interrupt is pending. a new pulse interrupt will be generated." bitfld.long 0xC 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to clear the flc_don status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect to this field." "0,1" bitfld.long 0xC 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_wrerr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_rderr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_hit status after interrupt has been serviced (raw status.." "0,1" newline bitfld.long 0xC 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_err status after interrupt has been serviced (raw status gets cleared .." "0,1" line.long 0x10 "RL2_IRQENABLE_SET,The Interrupt Enable Set Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x10 4. "EN_FLC_DON,Interrupt Enable Set for en_flc_don status bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 3. "EN_FLC_WRERR,Interrupt Enable Set for en_flc_wrerr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "EN_FLC_RDERR,Interrupt Enable Set for en_flc_rderr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 1. "EN_WR_HIT,Interrupt Enable Set for wr_hit error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "EN_WR_ERR,Interrupt Enable Set for wr_err error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x14 "RL2_IRQENABLE_CLR,The Interrupt Enable Clear Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x14 4. "EN_FLC_DON,Interrupt Enable Clear for flc_don status bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 3. "EN_FLC_WRERR,Interrupt Enable Clear for flc_wrerr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "EN_FLC_RDERR,Interrupt Enable Clear for flc_rderr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 1. "EN_WR_HIT,Interrupt Enable Clear for wr_hit error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "EN_WR_ERR,Interrupt Enable Clear for wr_err error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" group.long 0x104++0x3 line.long 0x0 "RL2_FLC_CFG,The FLC Config Register contains the configuration values for the FLC." bitfld.long 0x0 31. "FIFO_BYPASS,Setting this bit will cause the write to remote memory for a cache miss or FLC return to forces stalls on the read returns if any other data phase for a cache miss or FLC return is received. This can cause stalls on the write to force stalls.." "0,1" bitfld.long 0x0 24.--26. "FLC_EXCNT,The number of extra requests the FLC can send. The maximum value is 4 anything greater will default to 4. This value + 1 is the number of Reassembly Buffers used for FLC so if cache misses needed to be supported this value should be set to 4 or.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "ASMNUM,Number of Reassembly Buffer supported" hexmask.long.byte 0x0 0.--7. 1. "RANGES,Number of FLC ranges supported" rgroup.long 0x108++0x3 line.long 0x0 "RL2_FLC_STS,The FLC Status Register will indicate the state of the FLC completion." hexmask.long.byte 0x0 0.--3. 1. "CPYCMP,The cpycmp indicates which FLC range is complete. Each bit index indicates the FLC range is complete." rgroup.long 0x110++0x7 line.long 0x0 "RL2_FLC_DBG0,The FLC Debug 0 Register holds the debug state of the FLC." bitfld.long 0x0 31. "FLCIF,The flcif indicates a FLC operation is in flight." "0,1" bitfld.long 0x0 24.--26. "FLC_OUT_CNT,The number of read requests the FLC operation has in flight." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--1. "CURFLC,The curflc indicates which FLC range is in flight." "0,1,2,3" line.long 0x4 "RL2_FLC_DBG1,The FLC Debug 1 Register holds the debug address of the FLC." hexmask.long 0x4 0.--31. 1. "FLCADR,The flcadr indicates the next FLC address to be processed if still in flight. That is all addresses less than this address have been transferred. This address is used for FLC hit when the particular FLC range is in flight. That is.." rgroup.long 0x204++0x3 line.long 0x0 "RL2_RAT_CFG,The RAT Config Register contains the configuration values for the RAT." hexmask.long.byte 0x0 16.--23. 1. "ADDR_WIDTH,Number of address bits" hexmask.long.byte 0x0 0.--7. 1. "REGIONS,Number of regions" group.long 0x20++0x3 line.long 0x0 "RL2_REM_ADR_j,The REMote 'n' Address Least Significant word defines the least significant portion of the Remote address for remote cache data storage memory 0. The RL2 cache use up to three remote cache data storage memory ranges to place the L2 data.." hexmask.long.tbyte 0x0 11.--31. 1. "ADR_LSW,The rem0_adr_lsw defines the LSW of the remote cache data storage memory address[31:11] range 'n' for the RL2 to use for the cache. The remaining bits 10:0 are assumed to be zero." group.long 0x28++0x3 line.long 0x0 "RL2_REM_LEN_j,The Remote 'n' length defines the amount of remote cache data storage memory in 64 byte aligned quanta used starting from the REMote 'n' Address. The RL2 consumes remote cache data storage memory ranges in numeric order. Range 0 is consumed.." hexmask.long.word 0x0 6.--18. 1. "LEN,The rem0_len field specifies the length of the remote cache data storage memory 'n' to use for the RL2 cache in 64 byte quanta That is the number of bytes specified in the remote cache data storage memory range 'n' is (rem0_len X 64). Note: Any.." group.long 0x120++0x3 line.long 0x0 "RL2_FLC_LO_j,The FLC Low 'n' address defines the FLC lo address for FLC range 0. The FLC range is defined by FLC_LO0>=FLCrange=FLCrange=FLCrange=FLCrange=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_LO_LSW,The address_lo_lsw defines the L2 low address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be zero." group.long 0x18++0x3 line.long 0x0 "RL2_L2_HI,The L2 High address Least Significant word defines the least significant portion of the high cache address. The RL2 cache can cache a range of 1 to 16MB of cache as defined by L2_LO>=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_HI_LSW,The address_hi_lsw defines the high address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be ones." group.long 0x78++0x17 line.long 0x0 "RL2_L2HC,The L2 HIT Counter register holds the number of L2 Hits to the Remote data storage memory." hexmask.long 0x0 0.--31. 1. "HIT,The hit Counts the number of hits to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x4 "RL2_L2MC,The L2 MISS Counter register holds the number of L2 Misses to the Remote data storage memory." hexmask.long 0x4 0.--31. 1. "MISS,The miss Counts the number of misses to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x8 "RL2_IRQSTATUS_RAW,The Interrupt Raw Status Register holds the raw status of the FLC/RL2 status/error interrupts." bitfld.long 0x8 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to set the flc_don status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC remote range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_wrerr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_rderr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_hit status for diagnostic purposes. Writing a 0 has no.." "0,1" newline bitfld.long 0x8 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_err status for diagnostic purposes. Writing a 0 has no effect." "0,1" line.long 0xC "RL2_IRQSTATUS_MSK,The Interrupt Masked Status Register holds the masked status for the FLC/RL2 status/error interrupts. Writing to this register will EOI the interrupt. that is if another interrupt is pending. a new pulse interrupt will be generated." bitfld.long 0xC 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to clear the flc_don status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect to this field." "0,1" bitfld.long 0xC 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_wrerr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_rderr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_hit status after interrupt has been serviced (raw status.." "0,1" newline bitfld.long 0xC 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_err status after interrupt has been serviced (raw status gets cleared .." "0,1" line.long 0x10 "RL2_IRQENABLE_SET,The Interrupt Enable Set Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x10 4. "EN_FLC_DON,Interrupt Enable Set for en_flc_don status bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 3. "EN_FLC_WRERR,Interrupt Enable Set for en_flc_wrerr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "EN_FLC_RDERR,Interrupt Enable Set for en_flc_rderr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 1. "EN_WR_HIT,Interrupt Enable Set for wr_hit error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "EN_WR_ERR,Interrupt Enable Set for wr_err error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x14 "RL2_IRQENABLE_CLR,The Interrupt Enable Clear Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x14 4. "EN_FLC_DON,Interrupt Enable Clear for flc_don status bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 3. "EN_FLC_WRERR,Interrupt Enable Clear for flc_wrerr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "EN_FLC_RDERR,Interrupt Enable Clear for flc_rderr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 1. "EN_WR_HIT,Interrupt Enable Clear for wr_hit error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "EN_WR_ERR,Interrupt Enable Clear for wr_err error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" group.long 0x104++0x3 line.long 0x0 "RL2_FLC_CFG,The FLC Config Register contains the configuration values for the FLC." bitfld.long 0x0 31. "FIFO_BYPASS,Setting this bit will cause the write to remote memory for a cache miss or FLC return to forces stalls on the read returns if any other data phase for a cache miss or FLC return is received. This can cause stalls on the write to force stalls.." "0,1" bitfld.long 0x0 24.--26. "FLC_EXCNT,The number of extra requests the FLC can send. The maximum value is 4 anything greater will default to 4. This value + 1 is the number of Reassembly Buffers used for FLC so if cache misses needed to be supported this value should be set to 4 or.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "ASMNUM,Number of Reassembly Buffer supported" hexmask.long.byte 0x0 0.--7. 1. "RANGES,Number of FLC ranges supported" rgroup.long 0x108++0x3 line.long 0x0 "RL2_FLC_STS,The FLC Status Register will indicate the state of the FLC completion." hexmask.long.byte 0x0 0.--3. 1. "CPYCMP,The cpycmp indicates which FLC range is complete. Each bit index indicates the FLC range is complete." rgroup.long 0x110++0x7 line.long 0x0 "RL2_FLC_DBG0,The FLC Debug 0 Register holds the debug state of the FLC." bitfld.long 0x0 31. "FLCIF,The flcif indicates a FLC operation is in flight." "0,1" bitfld.long 0x0 24.--26. "FLC_OUT_CNT,The number of read requests the FLC operation has in flight." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--1. "CURFLC,The curflc indicates which FLC range is in flight." "0,1,2,3" line.long 0x4 "RL2_FLC_DBG1,The FLC Debug 1 Register holds the debug address of the FLC." hexmask.long 0x4 0.--31. 1. "FLCADR,The flcadr indicates the next FLC address to be processed if still in flight. That is all addresses less than this address have been transferred. This address is used for FLC hit when the particular FLC range is in flight. That is.." rgroup.long 0x204++0x3 line.long 0x0 "RL2_RAT_CFG,The RAT Config Register contains the configuration values for the RAT." hexmask.long.byte 0x0 16.--23. 1. "ADDR_WIDTH,Number of address bits" hexmask.long.byte 0x0 0.--7. 1. "REGIONS,Number of regions" group.long 0x20++0x3 line.long 0x0 "RL2_REM_ADR_j,The REMote 'n' Address Least Significant word defines the least significant portion of the Remote address for remote cache data storage memory 0. The RL2 cache use up to three remote cache data storage memory ranges to place the L2 data.." hexmask.long.tbyte 0x0 11.--31. 1. "ADR_LSW,The rem0_adr_lsw defines the LSW of the remote cache data storage memory address[31:11] range 'n' for the RL2 to use for the cache. The remaining bits 10:0 are assumed to be zero." group.long 0x28++0x3 line.long 0x0 "RL2_REM_LEN_j,The Remote 'n' length defines the amount of remote cache data storage memory in 64 byte aligned quanta used starting from the REMote 'n' Address. The RL2 consumes remote cache data storage memory ranges in numeric order. Range 0 is consumed.." hexmask.long.word 0x0 6.--18. 1. "LEN,The rem0_len field specifies the length of the remote cache data storage memory 'n' to use for the RL2 cache in 64 byte quanta That is the number of bytes specified in the remote cache data storage memory range 'n' is (rem0_len X 64). Note: Any.." group.long 0x120++0x3 line.long 0x0 "RL2_FLC_LO_j,The FLC Low 'n' address defines the FLC lo address for FLC range 0. The FLC range is defined by FLC_LO0>=FLCrange=FLCrange=FLCrange=FLCrange=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_LO_LSW,The address_lo_lsw defines the L2 low address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be zero." group.long 0x18++0x3 line.long 0x0 "RL2_L2_HI,The L2 High address Least Significant word defines the least significant portion of the high cache address. The RL2 cache can cache a range of 1 to 16MB of cache as defined by L2_LO>=CachedRange<=L2_HI. This register is write protected when.." hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS_HI_LSW,The address_hi_lsw defines the high address[31:11] for the RL2 to cache. The remaining bits 10:0 are assumed to be ones." group.long 0x78++0x17 line.long 0x0 "RL2_L2HC,The L2 HIT Counter register holds the number of L2 Hits to the Remote data storage memory." hexmask.long 0x0 0.--31. 1. "HIT,The hit Counts the number of hits to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x4 "RL2_L2MC,The L2 MISS Counter register holds the number of L2 Misses to the Remote data storage memory." hexmask.long 0x4 0.--31. 1. "MISS,The miss Counts the number of misses to the L2 cache. Writing to this register will set the value written or restarting the cache will clear its contents. This field does not roll over it will stop counting at all ones." line.long 0x8 "RL2_IRQSTATUS_RAW,The Interrupt Raw Status Register holds the raw status of the FLC/RL2 status/error interrupts." bitfld.long 0x8 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to set the flc_don status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC remote range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_wrerr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to set the flc_rderr status for diagnostic purposes. Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_hit status for diagnostic purposes. Writing a 0 has no.." "0,1" newline bitfld.long 0x8 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to set the wr_err status for diagnostic purposes. Writing a 0 has no effect." "0,1" line.long 0xC "RL2_IRQSTATUS_MSK,The Interrupt Masked Status Register holds the masked status for the FLC/RL2 status/error interrupts. Writing to this register will EOI the interrupt. that is if another interrupt is pending. a new pulse interrupt will be generated." bitfld.long 0xC 4. "FLC_DON,The flc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to clear the flc_don status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect to this field." "0,1" bitfld.long 0xC 3. "FLC_WRERR,The flc_wrerr bit indicates a write error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_wrerr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 2. "FLC_RDERR,The flc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the flc_rderr status after interrupt has been serviced (raw status gets cleared i.e. even if not.." "0,1" bitfld.long 0xC 1. "WR_HIT,The wr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_hit status after interrupt has been serviced (raw status.." "0,1" newline bitfld.long 0xC 0. "WR_ERR,The wr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the wr_err status after interrupt has been serviced (raw status gets cleared .." "0,1" line.long 0x10 "RL2_IRQENABLE_SET,The Interrupt Enable Set Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x10 4. "EN_FLC_DON,Interrupt Enable Set for en_flc_don status bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 3. "EN_FLC_WRERR,Interrupt Enable Set for en_flc_wrerr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "EN_FLC_RDERR,Interrupt Enable Set for en_flc_rderr error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 1. "EN_WR_HIT,Interrupt Enable Set for wr_hit error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "EN_WR_ERR,Interrupt Enable Set for wr_err error bit. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x14 "RL2_IRQENABLE_CLR,The Interrupt Enable Clear Register holds the interrupt enable status of the FLC/RL2 status/error interrupts." bitfld.long 0x14 4. "EN_FLC_DON,Interrupt Enable Clear for flc_don status bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 3. "EN_FLC_WRERR,Interrupt Enable Clear for flc_wrerr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "EN_FLC_RDERR,Interrupt Enable Clear for flc_rderr error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x14 1. "EN_WR_HIT,Interrupt Enable Clear for wr_hit error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "EN_WR_ERR,Interrupt Enable Clear for wr_err error bit. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" group.long 0x104++0x3 line.long 0x0 "RL2_FLC_CFG,The FLC Config Register contains the configuration values for the FLC." bitfld.long 0x0 31. "FIFO_BYPASS,Setting this bit will cause the write to remote memory for a cache miss or FLC return to forces stalls on the read returns if any other data phase for a cache miss or FLC return is received. This can cause stalls on the write to force stalls.." "0,1" bitfld.long 0x0 24.--26. "FLC_EXCNT,The number of extra requests the FLC can send. The maximum value is 4 anything greater will default to 4. This value + 1 is the number of Reassembly Buffers used for FLC so if cache misses needed to be supported this value should be set to 4 or.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "ASMNUM,Number of Reassembly Buffer supported" hexmask.long.byte 0x0 0.--7. 1. "RANGES,Number of FLC ranges supported" rgroup.long 0x108++0x3 line.long 0x0 "RL2_FLC_STS,The FLC Status Register will indicate the state of the FLC completion." hexmask.long.byte 0x0 0.--3. 1. "CPYCMP,The cpycmp indicates which FLC range is complete. Each bit index indicates the FLC range is complete." rgroup.long 0x110++0x7 line.long 0x0 "RL2_FLC_DBG0,The FLC Debug 0 Register holds the debug state of the FLC." bitfld.long 0x0 31. "FLCIF,The flcif indicates a FLC operation is in flight." "0,1" bitfld.long 0x0 24.--26. "FLC_OUT_CNT,The number of read requests the FLC operation has in flight." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--1. "CURFLC,The curflc indicates which FLC range is in flight." "0,1,2,3" line.long 0x4 "RL2_FLC_DBG1,The FLC Debug 1 Register holds the debug address of the FLC." hexmask.long 0x4 0.--31. 1. "FLCADR,The flcadr indicates the next FLC address to be processed if still in flight. That is all addresses less than this address have been transferred. This address is used for FLC hit when the particular FLC range is in flight. That is.." rgroup.long 0x204++0x3 line.long 0x0 "RL2_RAT_CFG,The RAT Config Register contains the configuration values for the RAT." hexmask.long.byte 0x0 16.--23. 1. "ADDR_WIDTH,Number of address bits" hexmask.long.byte 0x0 0.--7. 1. "REGIONS,Number of regions" group.long 0x20++0x3 line.long 0x0 "RL2_REM_ADR_j,The REMote 'n' Address Least Significant word defines the least significant portion of the Remote address for remote cache data storage memory 0. The RL2 cache use up to three remote cache data storage memory ranges to place the L2 data.." hexmask.long.tbyte 0x0 11.--31. 1. "ADR_LSW,The rem0_adr_lsw defines the LSW of the remote cache data storage memory address[31:11] range 'n' for the RL2 to use for the cache. The remaining bits 10:0 are assumed to be zero." group.long 0x28++0x3 line.long 0x0 "RL2_REM_LEN_j,The Remote 'n' length defines the amount of remote cache data storage memory in 64 byte aligned quanta used starting from the REMote 'n' Address. The RL2 consumes remote cache data storage memory ranges in numeric order. Range 0 is consumed.." hexmask.long.word 0x0 6.--18. 1. "LEN,The rem0_len field specifies the length of the remote cache data storage memory 'n' to use for the RL2 cache in 64 byte quanta That is the number of bytes specified in the remote cache data storage memory range 'n' is (rem0_len X 64). Note: Any.." group.long 0x120++0x3 line.long 0x0 "RL2_FLC_LO_j,The FLC Low 'n' address defines the FLC lo address for FLC range 0. The FLC range is defined by FLC_LO0>=FLCrange=FLCrange=FLCrange=FLCrange 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI1" base ad:0x52181000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI2" base ad:0x52182000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI3" base ad:0x52183000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI4" base ad:0x52184000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI5" base ad:0x52185000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI6" base ad:0x52186000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI7" base ad:0x52187000 group.long 0x0++0x1B line.long 0x0 "RTI_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "RTI_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "RTI_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "RTI_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "RTI_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "RTI_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "RTI_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "RTI_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "RTI_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree.end tree "SDFM0" base ad:0x50268000 rgroup.long 0x0++0x3 line.long 0x0 "SDFM_SDIFLG,SD Interrupt Flag Register." bitfld.long 0x0 31. "MIF,Set whenever any 'error' interrupt [MF1-4 IFL1-4 IFH1-4 SDFFOVF1-4] is active" "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready interrupt for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready interrupt for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready interrupt for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready interrupt for Ch1 0: SDFIFO data ready interrupt has NOT occurred 1: SDFIFO data ready interrupt has occurred" "0: SDFIFO data ready interrupt has NOT occurred,1: SDFIFO data ready interrupt has occurred" newline bitfld.long 0x0 19. "SDFFOVF4,FIFO Overflow Flag for Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,FIFO Overflow Flag for Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,FIFO Overflow Flag for Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,FIFO Overflow Flag for Ch1 0 - FIFO has not overflowed 1 - FIFO overflowed. # words received in FIFO ' FIFO depth [16] NEW word is lost" "0,1" newline bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,CEVT2 Interrupt flag for filter4 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,CEVT1 Interrupt flag for filter4 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,CEVT2 Interrupt flag for filter3 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,CEVT1 Interrupt flag for filter3 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,CEVT2 Interrupt flag for filter2 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,CEVT1 Interrupt flag for filter2 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,CEVT2 Interrupt flag for filter1 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,CEVT1 Interrupt flag for filter1 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" group.long 0x4++0x3 line.long 0x0 "SDFM_SDIFLGCLR,SD Module Interrupt Flag Clear Bits: Writing a '1' will clear the respective flag bit in the SDIFLG register. Writes of '0' are ignored. Note: If user writes a '1' to clear a bit on the same cycle that the hardware is trying to set the.." bitfld.long 0x0 31. "MIF,Flag-clear bit for SDFM Master Interrupt flag. Writing a 1 to clear MIF flag in SDIFLG register Writes of '0' are ignored. Note: If the MIF flag is cleared and other Interrupts are still pending MIF will again be set to 1 on the following.." "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready Interrupt flag-clear bit for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready Interrupt flag-clear bit for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready Interrupt flag-clear bit for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready Interrupt flag-clear bit for Ch1" "0,1" newline bitfld.long 0x0 19. "SDFFOVF4,SDFIFO overflow clear Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,SDFIFO overflow clear Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,SDFIFO overflow clear Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,SDFIFO overflow clear Ch1" "0,1" newline bitfld.long 0x0 15. "AF4,Flag-clear bit for Acknowledge flag for Filter 4" "0,1" newline bitfld.long 0x0 14. "AF3,Flag Clear bit for AF3" "0,1" newline bitfld.long 0x0 13. "AF2,Flag Clear bit for AF2" "0,1" newline bitfld.long 0x0 12. "AF1,Flag Clear bit for AF1" "0,1" newline bitfld.long 0x0 11. "MF4,Flag Clear bit for MF4" "0,1" newline bitfld.long 0x0 10. "MF3,Flag Clear bit for MF3" "0,1" newline bitfld.long 0x0 9. "MF2,Flag Clear bit for MF2" "0,1" newline bitfld.long 0x0 8. "MF1,Flag Clear bit for MF1" "0,1" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Flag Clear bit for FLT4_FLG_CEVT2" "0,1" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,Flag Clear bit for FLT4_FLG_CEVT1" "0,1" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Flag Clear bit for FLT3_FLG_CEVT2" "0,1" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,Flag Clear bit for FLT3_FLG_CEVT1" "0,1" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Flag Clear bit for FLT2_FLG_CEVT2" "0,1" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,Flag Clear bit for FLT2_FLG_CEVT1" "0,1" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Flag Clear bit for FLT1_FLG_CEVT2" "0,1" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,Flag Clear bit for FLT1_FLG_CEVT1" "0,1" group.word 0x8++0x1 line.word 0x0 "SDFM_SDCTL,SD Control Register." bitfld.word 0x0 13. "MIE,Master SDy_ERR interrupt enable 0:SDy_ERR Interrupt and interrupt flags are disabled 1:SDy_ERR Interrupt and interrupt flags are enabled" "0: SDy_ERR Interrupt and interrupt flags are disabled,1: SDy_ERR Interrupt and interrupt flags are enabled" newline bitfld.word 0x0 3. "HZ4,Flag Clear bit for HZ4" "0,1" newline bitfld.word 0x0 2. "HZ3,Flag Clear bit for HZ3" "0,1" newline bitfld.word 0x0 1. "HZ2,Flag Clear bit for HZ2" "0,1" newline bitfld.word 0x0 0. "HZ1,Flag Clear bit for HZ1" "0,1" group.word 0xC++0x1 line.word 0x0 "SDFM_SDMFILEN,SD Master Filter Enable." bitfld.word 0x0 11. "MFE,Master Filter Enable 0:All the four data filter units of SDFM module are disabled. All FIFOs are cleared 1:Data filter units can be enabled if bit FEN is '1'." "0: All the four data filter units of SDFM module..,1: Data filter units can be enabled if bit FEN is '1'" rgroup.word 0xE++0x1 line.word 0x0 "SDFM_SDSTATUS,SD Status Register." bitfld.word 0x0 3. "HZ4,High-level Threshold crossing [Z] flag Ch4 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ4.HLTZ.." "0: Comparator filter output ' SDCMPHZ4,1: Comparator filter output '= SDCMPHZ4" newline bitfld.word 0x0 2. "HZ3,High-level Threshold crossing [Z] flag Ch3 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ3.HLTZ.." "0: Comparator filter output ' SDCMPHZ3,1: Comparator filter output '= SDCMPHZ3" newline bitfld.word 0x0 1. "HZ2,High-level Threshold crossing [Z] flag Ch2 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ2.HLTZ.." "0: Comparator filter output ' SDCMPHZ2,1: Comparator filter output '= SDCMPHZ2" newline bitfld.word 0x0 0. "HZ1,High-level Threshold crossing [Z] flag Ch1 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ1.HLTZ.." "0: Comparator filter output ' SDCMPHZ1,1: Comparator filter output '= SDCMPHZ1" group.word 0x10++0x1 line.word 0x0 "SDFM_SDINTMODE,SD Interrupt Mode register." bitfld.word 0x0 0. "SDINTMODESEL,CompxH/L events interrupt mode select 0 CompxH/L events are treated as edge signals rise-edge detect will be done to qualify the event for interrupt generation 1 CompxH/L events are treated as level signals. Rise-edge detect will not.." "0,1" group.word 0x20++0xB line.word 0x0 "SDFM_SDCTLPARM1,Control Parameter Register for Ch1." bitfld.word 0x0 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0x0 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0x0 3. "SDCLKSEL,SD1 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0x0 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0x2 "SDFM_SDDFPARM1,Data Filter Parameter Register for Ch1." bitfld.word 0x2 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0x2 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x2 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0x2 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0x2 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0x4 "SDFM_SDDPARM1,Data Parameter Register for Ch1." hexmask.word.byte 0x4 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0x4 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x6 "SDFM_SDFLT1CMPH1,High-level Threshold Register for Ch1." hexmask.word 0x6 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x8 "SDFM_SDFLT1CMPL1,Low-level Threshold Register for Ch1." hexmask.word 0x8 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCPARM1,Comparator Filter Parameter Register for Ch1." bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0xA 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xA 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0xA 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x2C++0x7 line.long 0x0 "SDFM_SDDATA1,Data Filter Data Register (16 or 32bit) for Ch1." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO1,Filter Data FIFO Output(32b) for Ch1." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x34++0x1 line.word 0x0 "SDFM_SDCDATA1,Comparator Filter Data Register (16b) for Ch1." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x36++0x15 line.word 0x0 "SDFM_SDFLT1CMPH2,Second high level threhold for CH1." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT1CMPHZ,High-level (Z) Threshold Register for Ch1." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL1,FIFO Control Register for Ch1." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC1,SD Filter Sync control for Ch1." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT1CMPL2,Second low level threhold for CH1." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCTLPARM2,Control Parameter Register for Ch2." bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD2 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "SDFM_SDDFPARM2,Data Filter Parameter Register for Ch2." bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "SDFM_SDDPARM2,Data Parameter Register for Ch2." hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x10 "SDFM_SDFLT2CMPH1,High-level Threshold Register for Ch2." hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "SDFM_SDFLT2CMPL1,Low-level Threshold Register for Ch2." hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "SDFM_SDCPARM2,Comparator Filter Parameter Register for Ch2." bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x4C++0x7 line.long 0x0 "SDFM_SDDATA2,Data Filter Data Register (16 or 32bit) for Ch2." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO2,Filter Data FIFO Output(32b) for Ch2." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x54++0x1 line.word 0x0 "SDFM_SDCDATA2,Comparator Filter Data Register (16b) for Ch2." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x56++0x15 line.word 0x0 "SDFM_SDFLT2CMPH2,Second high level threhold for CH2." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT2CMPHZ,High-level (Z) Threshold Register for Ch2." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL2,FIFO Control Register for Ch2." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC2,SD Filter Sync control for Ch2." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT2CMPL2,Second low level threhold for CH2." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCTLPARM3,Control Parameter Register for Ch3." bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD3 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "SDFM_SDDFPARM3,Data Filter Parameter Register for Ch3." bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "SDFM_SDDPARM3,Data Parameter Register for Ch3." hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x10 "SDFM_SDFLT3CMPH1,High-level Threshold Register for Ch3." hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "SDFM_SDFLT3CMPL1,Low-level Threshold Register for Ch3." hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "SDFM_SDCPARM3,Comparator Filter Parameter Register for Ch3." bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x6C++0x7 line.long 0x0 "SDFM_SDDATA3,Data Filter Data Register (16 or 32bit) for Ch3." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO3,Filter Data FIFO Output(32b) for Ch3." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x74++0x1 line.word 0x0 "SDFM_SDCDATA3,Comparator Filter Data Register (16b) for Ch3." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x76++0x15 line.word 0x0 "SDFM_SDFLT3CMPH2,Second high level threhold for CH3." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT3CMPHZ,High-level (Z) Threshold Register for Ch3." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL3,FIFO Control Register for Ch3." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC3,SD Filter Sync control for Ch3." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT3CMPL2,Second low level threhold for CH3." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCTLPARM4,Control Parameter Register for Ch4." bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD4 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "SDFM_SDDFPARM4,Data Filter Parameter Register for Ch4." bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "SDFM_SDDPARM4,Data Parameter Register for Ch4." hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x10 "SDFM_SDFLT4CMPH1,High-level Threshold Register for Ch4." hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "SDFM_SDFLT4CMPL1,Low-level Threshold Register for Ch4." hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "SDFM_SDCPARM4,Comparator Filter Parameter Register for Ch4." bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x8C++0x7 line.long 0x0 "SDFM_SDDATA4,Data Filter Data Register (16 or 32bit) for Ch4." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO4,Filter Data FIFO Output(32b) for Ch4." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x94++0x1 line.word 0x0 "SDFM_SDCDATA4,Comparator Filter Data Register (16b) for Ch4." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x96++0x9 line.word 0x0 "SDFM_SDFLT4CMPH2,Second high level threhold for CH4." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT4CMPHZ,High-level (Z) Threshold Register for Ch4." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL4,FIFO Control Register for Ch4." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC4,SD Filter Sync control for Ch4." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT4CMPL2,Second low level threhold for CH4." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." group.word 0xC0++0x9 line.word 0x0 "SDFM_SDCOMP1CTL,SD Comparator event filter1 Control Register." bitfld.word 0x0 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x0 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x2 "SDFM_SDCOMP1EVT2FLTCTL,COMPL/CEVT2 Digital filter1 Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "SDFM_SDCOMP1EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter1 Clock Control Register." hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x6 "SDFM_SDCOMP1EVT1FLTCTL,COMPH/CEVT1 Digital filter1 Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "SDFM_SDCOMP1EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter1 Clock Control Register." hexmask.word 0x8 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xCE++0xB line.word 0x0 "SDFM_SDCOMP1LOCK,SD compartor event filter1 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP1EVT1/2FLTTCTL and COMP1FILCLKCTL registers. 0 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP1CTL,Lock write-access to the SDCOMP1CTL register. 0 SDCOMP1CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP1CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "SDFM_SDCOMP2CTL,SD Comparator event filter2 Control Register." bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "SDFM_SDCOMP2EVT2FLTCTL,COMPL/CEVT2 Digital filter2 Control Register." bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "SDFM_SDCOMP2EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter2 Clock Control Register." hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "SDFM_SDCOMP2EVT1FLTCTL,COMPH/CEVT1 Digital filter2 Control Register." bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "SDFM_SDCOMP2EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter2 Clock Control Register." hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xDE++0xB line.word 0x0 "SDFM_SDCOMP2LOCK,SD compartor event filter2 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP2EVT1/2FLTTCTL and COMP2FILCLKCTL registers. 0 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP2CTL,Lock write-access to the SDCOMP2CTL register. 0 SDCOMP2CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP2CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "SDFM_SDCOMP3CTL,SD Comparator event filter3 Control Register." bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "SDFM_SDCOMP3EVT2FLTCTL,COMPL/CEVT2 Digital filter3 Control Register." bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "SDFM_SDCOMP3EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter3 Clock Control Register." hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "SDFM_SDCOMP3EVT1FLTCTL,COMPH/CEVT1 Digital filter3 Control Register." bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "SDFM_SDCOMP3EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter3 Clock Control Register." hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xEE++0xB line.word 0x0 "SDFM_SDCOMP3LOCK,SD compartor event filter3 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP3EVT1/2FLTTCTL and COMP3FILCLKCTL registers. 0 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP3CTL,Lock write-access to the SDCOMP3CTL register. 0 SDCOMP3CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP3CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "SDFM_SDCOMP4CTL,SD Comparator event filter4 Control Register." bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "SDFM_SDCOMP4EVT2FLTCTL,COMPL/CEVT2 Digital filter4 Control Register." bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "SDFM_SDCOMP4EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter4 Clock Control Register." hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "SDFM_SDCOMP4EVT1FLTCTL,COMPH/CEVT1 Digital filter4 Control Register." bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "SDFM_SDCOMP4EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter4 Clock Control Register." hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xFE++0x1 line.word 0x0 "SDFM_SDCOMP4LOCK,SD compartor event filter4 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP4EVT1/2FLTTCTL and COMP4FILCLKCTL registers. 0 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP4CTL,Lock write-access to the SDCOMP4CTL register. 0 SDCOMP4CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP4CTL register is locked. Only a system reset can clear this bit." "0,1" tree.end tree "SDFM1" base ad:0x50269000 rgroup.long 0x0++0x3 line.long 0x0 "SDFM_SDIFLG,SD Interrupt Flag Register." bitfld.long 0x0 31. "MIF,Set whenever any 'error' interrupt [MF1-4 IFL1-4 IFH1-4 SDFFOVF1-4] is active" "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready interrupt for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready interrupt for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready interrupt for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready interrupt for Ch1 0: SDFIFO data ready interrupt has NOT occurred 1: SDFIFO data ready interrupt has occurred" "0: SDFIFO data ready interrupt has NOT occurred,1: SDFIFO data ready interrupt has occurred" newline bitfld.long 0x0 19. "SDFFOVF4,FIFO Overflow Flag for Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,FIFO Overflow Flag for Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,FIFO Overflow Flag for Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,FIFO Overflow Flag for Ch1 0 - FIFO has not overflowed 1 - FIFO overflowed. # words received in FIFO ' FIFO depth [16] NEW word is lost" "0,1" newline bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1 0:No new data available for Filter [in non-FIFO mode] 1:New data available for Filter [in non-FIFO mode]" "0: No new data available for Filter [in non-FIFO..,1: New data available for Filter [in non-FIFO mode]" newline bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1 0:Modulator is operating normally for Filter 1:Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,CEVT2 Interrupt flag for filter4 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,CEVT1 Interrupt flag for filter4 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,CEVT2 Interrupt flag for filter3 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,CEVT1 Interrupt flag for filter3 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,CEVT2 Interrupt flag for filter2 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,CEVT1 Interrupt flag for filter2 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,CEVT2 Interrupt flag for filter1 0:CEVT2 event has not occured 1:CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,CEVT1 Interrupt flag for filter1 0:CEVT1 event has not occured 1:CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" group.long 0x4++0x3 line.long 0x0 "SDFM_SDIFLGCLR,SD Module Interrupt Flag Clear Bits: Writing a '1' will clear the respective flag bit in the SDIFLG register. Writes of '0' are ignored. Note: If user writes a '1' to clear a bit on the same cycle that the hardware is trying to set the.." bitfld.long 0x0 31. "MIF,Flag-clear bit for SDFM Master Interrupt flag. Writing a 1 to clear MIF flag in SDIFLG register Writes of '0' are ignored. Note: If the MIF flag is cleared and other Interrupts are still pending MIF will again be set to 1 on the following.." "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready Interrupt flag-clear bit for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready Interrupt flag-clear bit for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready Interrupt flag-clear bit for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready Interrupt flag-clear bit for Ch1" "0,1" newline bitfld.long 0x0 19. "SDFFOVF4,SDFIFO overflow clear Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,SDFIFO overflow clear Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,SDFIFO overflow clear Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,SDFIFO overflow clear Ch1" "0,1" newline bitfld.long 0x0 15. "AF4,Flag-clear bit for Acknowledge flag for Filter 4" "0,1" newline bitfld.long 0x0 14. "AF3,Flag Clear bit for AF3" "0,1" newline bitfld.long 0x0 13. "AF2,Flag Clear bit for AF2" "0,1" newline bitfld.long 0x0 12. "AF1,Flag Clear bit for AF1" "0,1" newline bitfld.long 0x0 11. "MF4,Flag Clear bit for MF4" "0,1" newline bitfld.long 0x0 10. "MF3,Flag Clear bit for MF3" "0,1" newline bitfld.long 0x0 9. "MF2,Flag Clear bit for MF2" "0,1" newline bitfld.long 0x0 8. "MF1,Flag Clear bit for MF1" "0,1" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Flag Clear bit for FLT4_FLG_CEVT2" "0,1" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,Flag Clear bit for FLT4_FLG_CEVT1" "0,1" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Flag Clear bit for FLT3_FLG_CEVT2" "0,1" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,Flag Clear bit for FLT3_FLG_CEVT1" "0,1" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Flag Clear bit for FLT2_FLG_CEVT2" "0,1" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,Flag Clear bit for FLT2_FLG_CEVT1" "0,1" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Flag Clear bit for FLT1_FLG_CEVT2" "0,1" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,Flag Clear bit for FLT1_FLG_CEVT1" "0,1" group.word 0x8++0x1 line.word 0x0 "SDFM_SDCTL,SD Control Register." bitfld.word 0x0 13. "MIE,Master SDy_ERR interrupt enable 0:SDy_ERR Interrupt and interrupt flags are disabled 1:SDy_ERR Interrupt and interrupt flags are enabled" "0: SDy_ERR Interrupt and interrupt flags are disabled,1: SDy_ERR Interrupt and interrupt flags are enabled" newline bitfld.word 0x0 3. "HZ4,Flag Clear bit for HZ4" "0,1" newline bitfld.word 0x0 2. "HZ3,Flag Clear bit for HZ3" "0,1" newline bitfld.word 0x0 1. "HZ2,Flag Clear bit for HZ2" "0,1" newline bitfld.word 0x0 0. "HZ1,Flag Clear bit for HZ1" "0,1" group.word 0xC++0x1 line.word 0x0 "SDFM_SDMFILEN,SD Master Filter Enable." bitfld.word 0x0 11. "MFE,Master Filter Enable 0:All the four data filter units of SDFM module are disabled. All FIFOs are cleared 1:Data filter units can be enabled if bit FEN is '1'." "0: All the four data filter units of SDFM module..,1: Data filter units can be enabled if bit FEN is '1'" rgroup.word 0xE++0x1 line.word 0x0 "SDFM_SDSTATUS,SD Status Register." bitfld.word 0x0 3. "HZ4,High-level Threshold crossing [Z] flag Ch4 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ4.HLTZ.." "0: Comparator filter output ' SDCMPHZ4,1: Comparator filter output '= SDCMPHZ4" newline bitfld.word 0x0 2. "HZ3,High-level Threshold crossing [Z] flag Ch3 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ3.HLTZ.." "0: Comparator filter output ' SDCMPHZ3,1: Comparator filter output '= SDCMPHZ3" newline bitfld.word 0x0 1. "HZ2,High-level Threshold crossing [Z] flag Ch2 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ2.HLTZ.." "0: Comparator filter output ' SDCMPHZ2,1: Comparator filter output '= SDCMPHZ2" newline bitfld.word 0x0 0. "HZ1,High-level Threshold crossing [Z] flag Ch1 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0:Comparator filter output ' SDCMPHZ1.HLTZ.." "0: Comparator filter output ' SDCMPHZ1,1: Comparator filter output '= SDCMPHZ1" group.word 0x10++0x1 line.word 0x0 "SDFM_SDINTMODE,SD Interrupt Mode register." bitfld.word 0x0 0. "SDINTMODESEL,CompxH/L events interrupt mode select 0 CompxH/L events are treated as edge signals rise-edge detect will be done to qualify the event for interrupt generation 1 CompxH/L events are treated as level signals. Rise-edge detect will not.." "0,1" group.word 0x20++0xB line.word 0x0 "SDFM_SDCTLPARM1,Control Parameter Register for Ch1." bitfld.word 0x0 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0x0 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0x0 3. "SDCLKSEL,SD1 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0x0 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0x2 "SDFM_SDDFPARM1,Data Filter Parameter Register for Ch1." bitfld.word 0x2 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0x2 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x2 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0x2 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0x2 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0x4 "SDFM_SDDPARM1,Data Parameter Register for Ch1." hexmask.word.byte 0x4 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0x4 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x6 "SDFM_SDFLT1CMPH1,High-level Threshold Register for Ch1." hexmask.word 0x6 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x8 "SDFM_SDFLT1CMPL1,Low-level Threshold Register for Ch1." hexmask.word 0x8 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCPARM1,Comparator Filter Parameter Register for Ch1." bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0xA 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xA 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0xA 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x2C++0x7 line.long 0x0 "SDFM_SDDATA1,Data Filter Data Register (16 or 32bit) for Ch1." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO1,Filter Data FIFO Output(32b) for Ch1." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x34++0x1 line.word 0x0 "SDFM_SDCDATA1,Comparator Filter Data Register (16b) for Ch1." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x36++0x15 line.word 0x0 "SDFM_SDFLT1CMPH2,Second high level threhold for CH1." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT1CMPHZ,High-level (Z) Threshold Register for Ch1." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL1,FIFO Control Register for Ch1." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC1,SD Filter Sync control for Ch1." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT1CMPL2,Second low level threhold for CH1." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCTLPARM2,Control Parameter Register for Ch2." bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD2 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "SDFM_SDDFPARM2,Data Filter Parameter Register for Ch2." bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "SDFM_SDDPARM2,Data Parameter Register for Ch2." hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x10 "SDFM_SDFLT2CMPH1,High-level Threshold Register for Ch2." hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "SDFM_SDFLT2CMPL1,Low-level Threshold Register for Ch2." hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "SDFM_SDCPARM2,Comparator Filter Parameter Register for Ch2." bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x4C++0x7 line.long 0x0 "SDFM_SDDATA2,Data Filter Data Register (16 or 32bit) for Ch2." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO2,Filter Data FIFO Output(32b) for Ch2." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x54++0x1 line.word 0x0 "SDFM_SDCDATA2,Comparator Filter Data Register (16b) for Ch2." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x56++0x15 line.word 0x0 "SDFM_SDFLT2CMPH2,Second high level threhold for CH2." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT2CMPHZ,High-level (Z) Threshold Register for Ch2." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL2,FIFO Control Register for Ch2." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC2,SD Filter Sync control for Ch2." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT2CMPL2,Second low level threhold for CH2." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCTLPARM3,Control Parameter Register for Ch3." bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD3 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "SDFM_SDDFPARM3,Data Filter Parameter Register for Ch3." bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "SDFM_SDDPARM3,Data Parameter Register for Ch3." hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x10 "SDFM_SDFLT3CMPH1,High-level Threshold Register for Ch3." hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "SDFM_SDFLT3CMPL1,Low-level Threshold Register for Ch3." hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "SDFM_SDCPARM3,Comparator Filter Parameter Register for Ch3." bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x6C++0x7 line.long 0x0 "SDFM_SDDATA3,Data Filter Data Register (16 or 32bit) for Ch3." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO3,Filter Data FIFO Output(32b) for Ch3." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x74++0x1 line.word 0x0 "SDFM_SDCDATA3,Comparator Filter Data Register (16b) for Ch3." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x76++0x15 line.word 0x0 "SDFM_SDFLT3CMPH2,Second high level threhold for CH3." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT3CMPHZ,High-level (Z) Threshold Register for Ch3." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL3,FIFO Control Register for Ch3." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC3,SD Filter Sync control for Ch3." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT3CMPL2,Second low level threhold for CH3." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "SDFM_SDCTLPARM4,Control Parameter Register for Ch4." bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1:SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1:SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD4 Clock source select. 0:Clock source to SDFM filter is its channel clock. 1:Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0:Mode0:Modulator clock running at 1x data rate 1:Reserved 2:Reserved 3:Reserved" "0: Mode0:Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "SDFM_SDDFPARM4,Data Filter Parameter Register for Ch4." bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "SDFM_SDDPARM4,Data Parameter Register for Ch4." hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0:Data stored in16b2's complement 1:Data stored in32b2's complement" "0: Data stored in16b2's complement,1: Data stored in32b2's complement" line.word 0x10 "SDFM_SDFLT4CMPH1,High-level Threshold Register for Ch4." hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "SDFM_SDFLT4CMPL1,Low-level Threshold Register for Ch4." hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "SDFM_SDCPARM4,Comparator Filter Parameter Register for Ch4." bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01:COMPL1 OR COMPH1 10:COMPL2 11:COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0:Disable comparator filter 1:Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01:COMPL1 OR COMPH1 10:COMPH2 11:COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level [Z] Threshold crossing output enable 0:Disable Higher level Threshold [Z] crossing 1:Enable Higher level Threhold [Z] crossing" "0: Disable Higher level Threshold [Z] crossing,1: Enable Higher level Threhold [Z] crossing" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0:Disable modulator failure interrupt and its flag 1:Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00:Comparator filter runs with a sincfast structure 01:Comparator filter runs with a Sinc1 structure 10:Comparator filter runs with a Sinc2 structure 11:Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0:Disable CEVT2 interrupt 1:Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0:Disable CEVT1 interrupt 1:Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x8C++0x7 line.long 0x0 "SDFM_SDDATA4,Data Filter Data Register (16 or 32bit) for Ch4." hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order16bin32bmode" line.long 0x4 "SDFM_SDDATFIFO4,Filter Data FIFO Output(32b) for Ch4." hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order16bin32bmode 16-bit Data in16bmode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order16bin32bmode" rgroup.word 0x94++0x1 line.word 0x0 "SDFM_SDCDATA4,Comparator Filter Data Register (16b) for Ch4." hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output -16bonly" group.word 0x96++0x9 line.word 0x0 "SDFM_SDFLT4CMPH2,Second high level threhold for CH4." hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "SDFM_SDFLT4CMPHZ,High-level (Z) Threshold Register for Ch4." hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold [Z] for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "SDFM_SDFIFOCTL4,FIFO Control Register for Ch4." bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0:SDFIFO Overflow condition will not generate an interrupt 1:SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt [DRINT] source select 0 = AF1 [Select non-FIFO data-ready interrupt] 1 = SDFFINT1 [Select FIFO data-ready interrupt]" "0: AF1 [Select non-FIFO data-ready interrupt],1: SDFFINT1 [Select FIFO data-ready interrupt]" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status [SDFFST] '= FIFO level [SDFFIL ]" line.word 0x6 "SDFM_SDSYNC4,SD Filter Sync control for Ch4." bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually [using..,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG" "0: Write of 0 has no effect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "SDFM_SDFLT4CMPL2,Second low level threhold for CH4." hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." group.word 0xC0++0x9 line.word 0x0 "SDFM_SDCOMP1CTL,SD Comparator event filter1 Control Register." bitfld.word 0x0 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x0 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x2 "SDFM_SDCOMP1EVT2FLTCTL,COMPL/CEVT2 Digital filter1 Control Register." bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "SDFM_SDCOMP1EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter1 Clock Control Register." hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x6 "SDFM_SDCOMP1EVT1FLTCTL,COMPH/CEVT1 Digital filter1 Control Register." bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "SDFM_SDCOMP1EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter1 Clock Control Register." hexmask.word 0x8 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xCE++0xB line.word 0x0 "SDFM_SDCOMP1LOCK,SD compartor event filter1 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP1EVT1/2FLTTCTL and COMP1FILCLKCTL registers. 0 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP1CTL,Lock write-access to the SDCOMP1CTL register. 0 SDCOMP1CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP1CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "SDFM_SDCOMP2CTL,SD Comparator event filter2 Control Register." bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "SDFM_SDCOMP2EVT2FLTCTL,COMPL/CEVT2 Digital filter2 Control Register." bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "SDFM_SDCOMP2EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter2 Clock Control Register." hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "SDFM_SDCOMP2EVT1FLTCTL,COMPH/CEVT1 Digital filter2 Control Register." bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "SDFM_SDCOMP2EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter2 Clock Control Register." hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xDE++0xB line.word 0x0 "SDFM_SDCOMP2LOCK,SD compartor event filter2 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP2EVT1/2FLTTCTL and COMP2FILCLKCTL registers. 0 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP2CTL,Lock write-access to the SDCOMP2CTL register. 0 SDCOMP2CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP2CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "SDFM_SDCOMP3CTL,SD Comparator event filter3 Control Register." bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "SDFM_SDCOMP3EVT2FLTCTL,COMPL/CEVT2 Digital filter3 Control Register." bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "SDFM_SDCOMP3EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter3 Clock Control Register." hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "SDFM_SDCOMP3EVT1FLTCTL,COMPH/CEVT1 Digital filter3 Control Register." bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "SDFM_SDCOMP3EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter3 Clock Control Register." hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xEE++0xB line.word 0x0 "SDFM_SDCOMP3LOCK,SD compartor event filter3 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP3EVT1/2FLTTCTL and COMP3FILCLKCTL registers. 0 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP3CTL,Lock write-access to the SDCOMP3CTL register. 0 SDCOMP3CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP3CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "SDFM_SDCOMP4CTL,SD Comparator event filter4 Control Register." bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "SDFM_SDCOMP4EVT2FLTCTL,COMPL/CEVT2 Digital filter4 Control Register." bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "SDFM_SDCOMP4EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter4 Clock Control Register." hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "SDFM_SDCOMP4EVT1FLTCTL,COMPH/CEVT1 Digital filter4 Control Register." bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "SDFM_SDCOMP4EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter4 Clock Control Register." hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xFE++0x1 line.word 0x0 "SDFM_SDCOMP4LOCK,SD compartor event filter4 Lock Register." bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP4EVT1/2FLTTCTL and COMP4FILCLKCTL registers. 0 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP4CTL,Lock write-access to the SDCOMP4CTL register. 0 SDCOMP4CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP4CTL register is locked. Only a system reset can clear this bit." "0,1" tree.end tree "SOC_TIMESYNC" base ad:0x0 tree "SOC_TIMESYNC_XBAR0" base ad:0x52E00000 rgroup.long 0x0++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR0_INTR_ROUTER_CFG_PID,Identification register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,Rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR0_INTR_ROUTER_CFG_MUXCNTL_j,Interrupt mux control register." bitfld.long 0x0 16. "INT_ENABLE,Interrupt j Output Enable." "0,1" hexmask.long.byte 0x0 0.--4. 1. "MUX_CNTL,Mux Control for Interrupt j." tree.end tree "SOC_TIMESYNC_XBAR1" base ad:0x52E04000 rgroup.long 0x0++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR1_INTR_ROUTER_CFG_PID,Identification register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,Rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR1_INTR_ROUTER_CFG_MUXCNTL_j,Interrupt mux control register." bitfld.long 0x0 16. "INT_ENABLE,Interrupt j Output Enable." "0,1" hexmask.long.byte 0x0 0.--3. 1. "MUX_CNTL,Mux Control for Interrupt j." tree.end tree.end tree "SPINLOCK0" base ad:0x50E00000 rgroup.long 0x0++0x3 line.long 0x0 "SPINLOCK_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "SPINLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock." bitfld.long 0x0 1. "SOFT_RESET,Module Software ResetThe bit is automatically reset by the hardware. During reads it always returns 0It has the same effect as the hardware resetWriting a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the locks" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPINLOCK_SYSTATUS,Provides information about the Spinlock module." hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32.e.g. For 256 spin locks this will return the number 0x08" bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 224 - 255 are in the Not Taken stateRead1 : At least one of the lock registers 224 -.." "0,1" bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 192 - 223 are in the Not Taken stateRead1 : At least one of the lock registers 192 -.." "0,1" bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 160 - 191 are in the Not Taken stateRead1 : At least one of the lock registers 160 -.." "0,1" bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 128 - 159 are in the Not Taken stateRead1 : At least one of the lock registers 128 -.." "0,1" bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 96 - 127 are in the Not Taken stateRead1 : At least one of the lock registers 96 - 127.." "0,1" bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 64 - 95 are in the Not Taken stateRead1 : At least one of the lock registers 64 - 95 are.." "0,1" bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 32 - 63 are in the Not Taken stateRead1 : At least one of the lock registers 32 - 63 are.." "0,1" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31.If no lock registers are implemented in this range then this flag always reads as 0Read0 : All lock registers 0 - 31 are in the Not Taken stateRead1 : At least one of the lock registers 0 - 31 are in.." "0,1" group.long 0x800++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_j,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'." bitfld.long 0x0 0. "TAKEN,Lock StatusRead0 : Lock was previously free. The reader now has been granted the lock.Read1 : Lock was previously taken. The reader has not been granted the lock and must retry.Write0 : Free the lock by setting TAKEN to zero.Write1 : No effect" "0,1" tree.end tree "TOP" base ad:0x0 tree "TOP_CTRL" base ad:0x50D80000 rgroup.long 0x10++0x2B line.long 0x0 "TOP_CTRL_EFUSE_DIEID0,EFUSE_DIEID0." hexmask.long 0x0 0.--31. 1. "EFUSE_DIEID0_VAL,EFUSE DieID[31:0]" line.long 0x4 "TOP_CTRL_EFUSE_DIEID1,EFUSE_DIEID1." hexmask.long 0x4 0.--31. 1. "EFUSE_DIEID1_VAL,EFUSE DieID[63:32]" line.long 0x8 "TOP_CTRL_EFUSE_DIEID2,EFUSE_DIEID2." hexmask.long 0x8 0.--31. 1. "EFUSE_DIEID2_VAL,EFUSE DieID[95:64]" line.long 0xC "TOP_CTRL_EFUSE_DIEID3,EFUSE_DIEID3." hexmask.long 0xC 0.--31. 1. "EFUSE_DIEID3_VAL,EFUSE DieID[127:96]" line.long 0x10 "TOP_CTRL_EFUSE_UID0,EFUSE_UID0." hexmask.long 0x10 0.--31. 1. "EFUSE_UID0_VAL,EFUSE UID[31:0]- Unique ID" line.long 0x14 "TOP_CTRL_EFUSE_UID1,EFUSE_UID1." hexmask.long 0x14 0.--31. 1. "EFUSE_UID1_VAL,EFUSE UID[63:32]- Unique ID" line.long 0x18 "TOP_CTRL_EFUSE_UID2,EFUSE_UID2." hexmask.long 0x18 0.--31. 1. "EFUSE_UID2_VAL,EFUSE UID[95:64]- Unique ID" line.long 0x1C "TOP_CTRL_EFUSE_UID3,EFUSE_UID3." hexmask.long.tbyte 0x1C 0.--23. 1. "EFUSE_UID3_VAL,EFUSE UID[120:96]- Unique ID" line.long 0x20 "TOP_CTRL_EFUSE_DEVICE_TYPE,EFUSE_DEVICE_TYPE." hexmask.long.word 0x20 0.--15. 1. "EFUSE_DEVICE_TYPE_VAL,EFUSE Device Type : 0x5 - Test Device 0x3 - General Purpose Device 0x9 - EMU Device 0xA - High Secure" line.long 0x24 "TOP_CTRL_EFUSE_FROM0_CHECKSUM,EFUSE_FROM0_CHECKSUM." hexmask.long 0x24 0.--31. 1. "EFUSE_FROM0_CHECKSUM_VAL,32 bit FROM0 Checksum" line.long 0x28 "TOP_CTRL_EFUSE_JTAG_USERCODE_ID,EFUSE_JTAG_USERCODE_ID." hexmask.long 0x28 0.--31. 1. "EFUSE_JTAG_USERCODE_ID_VAL,EFUSE JTAG_USER_CODE_ID[31:0]. Denotes part variant" rgroup.long 0x428++0x3 line.long 0x0 "TOP_CTRL_EFUSE1_ROW_12,EFUSE Row." bitfld.long 0x0 24. "EFUSE1_ROW_12_EPWM_FEATURE_DISABLE,Customer protected features inside PWM IP 1'b0 - All features enabled1'b1 - Customer defined features are protected" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "EFUSE1_ROW_12_CANFD_DIS,CANFD disables. Bit positions correspond to CAN instance. 1'b0 - CAN is enabled1'b1 - CAN is disabled" newline hexmask.long.byte 0x0 12.--19. 1. "EFUSE1_ROW_12_PRU_ICSS_HW_DIS,ICSSM IP feature configuration0x00:EtherCAT is available0x03:EtherCAT is disabled" newline bitfld.long 0x0 11. "EFUSE1_ROW_12_PRU_ICSS_DIS,ICSSM IP disable1'b0 - ICSSM enabled1'b1 - ICSSM disabled" "0,1" newline bitfld.long 0x0 10. "EFUSE1_ROW_12_TWOX_CTRL_PERIP_DISABLE,2x control IPs enabled1'b0 - 1x control IPs available (Standard Analog Configuration)1'b1 - (i.e.all) 2x control IPs available (Enhanced Analog Configuration) Refer to device datasheet for more details on the.." "0,1" newline bitfld.long 0x0 9. "EFUSE1_ROW_12_R5SS_FREQ,R5SS Freq1'b0 - 400 MHz1'b1 - 200 MHz" "0,1" newline bitfld.long 0x0 8. "EFUSE1_ROW_12_R5SS1_DISABLE,R5SS1 Disabled" "0,1" newline bitfld.long 0x0 7. "EFUSE1_ROW_12_R5SS1_DUAL_CORE_DISABLE,Force Lock step" "0,1" newline bitfld.long 0x0 6. "EFUSE1_ROW_12_R5SS1_FORCE_DUAL_CORE,Force Dual core" "0,1" newline bitfld.long 0x0 5. "EFUSE1_ROW_12_R5SS0_DUAL_CORE_DISABLE,Force Lock step" "0,1" newline bitfld.long 0x0 4. "EFUSE1_ROW_12_R5SS0_FORCE_DUAL_CORE,Force Dual core" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "EFUSE1_ROW_12_L2_MEM_SIZE,Decides memory size0000L2-3.0 MB0001L2-2.5 MB0010L2-2.0 MB0011L2-1.5 MB0100L2-1.0 MB0101L2-0.5 MBOthers-Reserved" rgroup.long 0x500++0x7 line.long 0x0 "TOP_CTRL_MAC_ID0,Ethernet MAC address lower 32-bits." hexmask.long 0x0 0.--31. 1. "MAC_ID0_MACID_LO,48-bit Ethernet MAC_ID field [can be used by SW through MMR read] - MAC ID low [32bits]" line.long 0x4 "TOP_CTRL_MAC_ID1,Ethernet MAC address upper 16-bits." hexmask.long.word 0x4 0.--15. 1. "MAC_ID1_MACID_HI,48-bit Ethernet MAC_ID field [can be used by SW through MMR read] - MAC ID high [16bits]" group.long 0x880++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_LDO_TRIM" hexmask.long.byte 0x0 24.--29. 1. "EFUSE_OVERRIDE_LDO_TRIM_LDO_TRIM_OFFSET,LDO Fine trim around program point" newline hexmask.long.byte 0x0 16.--19. 1. "EFUSE_OVERRIDE_LDO_TRIM_LDO_PROG,LDO programming controls. Adjusts nominal LDO output voltage" newline bitfld.long 0x0 0.--2. "EFUSE_OVERRIDE_LDO_TRIM_OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0,1,2,3,4,5,6,7" group.long 0xC00++0xB line.long 0x0 "TOP_CTRL_ADC_REFBUF0_CTRL,This register is used to enable or disable ADC Reference buffer 0" bitfld.long 0x0 0.--2. "ADC_REFBUF0_CTRL_ENABLE,Enables adc reference 0 mask hhv before enable000:Disable111 : Enable" "0,1,2,3,4,5,6,7" line.long 0x4 "TOP_CTRL_ADC_REFBUF1_CTRL,This register is used to enable or disable ADC Reference buffer 1" bitfld.long 0x4 0.--2. "ADC_REFBUF1_CTRL_ENABLE,Enables adc reference 0 mask hhv before enable000:Disable111 : Enable" "0,1,2,3,4,5,6,7" line.long 0x8 "TOP_CTRL_ADC_REF_COMP_CTRL,This register is used to enable or disable the voltage monitors which measure if the ADC reference voltage is good or not." bitfld.long 0x8 12.--14. "ADC_REF_COMP_CTRL_ADCR01_REFOK_EN,Enables reference comparators [ROK2]. This monitors adc5 & adc6 refernce" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8.--10. "ADC_REF_COMP_CTRL_ADC34_REFOK_EN,Enables reference comparators [ROK1]. This monitors adc3 & adc4 refernc" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "ADC_REF_COMP_CTRL_ADC12_REFOK_EN,Enables reference comparators [ROK0B]. This monitors adc1 & adc2 refernce" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "ADC_REF_COMP_CTRL_ADC0_REFOK_EN,Enables reference comparators [ROK0]. This monitors adc0 refernce" "0,1,2,3,4,5,6,7" rgroup.long 0xC0C++0x3 line.long 0x0 "TOP_CTRL_ADC_REF_GOOD_STATUS,This register shows the status of ADC reference voltages as measured by the ADC Reference OK voltage monitors." bitfld.long 0x0 7. "ADC_REF_GOOD_STATUS_ADCR01_REF_UV_GOOD,Under Voltage check OK1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 6. "ADC_REF_GOOD_STATUS_ADCR01_REF_OV_GOOD,Over voltage check OK1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" newline bitfld.long 0x0 5. "ADC_REF_GOOD_STATUS_ADC12_REF_UV_GOOD,Under Voltage check OK1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 4. "ADC_REF_GOOD_STATUS_ADC12_REF_OV_GOOD,Over voltage check OK1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" newline bitfld.long 0x0 3. "ADC_REF_GOOD_STATUS_ADC0_REF_UV_GOOD,Under Voltage check OK1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 2. "ADC_REF_GOOD_STATUS_ADC0_REF_OV_GOOD,Over voltage check OK1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" newline bitfld.long 0x0 1. "ADC_REF_GOOD_STATUS_ADC34_REF_UV_GOOD,Under Voltage check OK1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 0. "ADC_REF_GOOD_STATUS_ADC34_REF_OV_GOOD,Over voltage check OK1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" group.long 0xC10++0x3 line.long 0x0 "TOP_CTRL_VMON_CTRL,This register is used to enable or disable the power supply voltage monitors present on the device." bitfld.long 0x0 24.--26. "VMON_CTRL_CMP8_EN,Enable for VMON comparator 8 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "VMON_CTRL_CMP7_EN,Enable for VMON comparator 7 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "VMON_CTRL_CMP5_EN,Enable for VMON comparator 5 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "VMON_CTRL_CMP3_EN,Enable for VMON comparator 3 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "VMON_CTRL_CMP2_EN,Enable for VMON comparator 2 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "VMON_CTRL_CMP1_EN,Enable for VMON comparator 1 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "VMON_CTRL_CMP0_EN,Enable for VMON comparator 0 Configure it to 3'000 to disable it." "0,1,2,3,4,5,6,7" rgroup.long 0xC14++0x7 line.long 0x0 "TOP_CTRL_VMON_STAT,This register shows the status output from the voltage monitors present on the device." bitfld.long 0x0 10. "VMON_STAT_CMP8_UV_OK,VMON status register for comparator 8. 1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 9. "VMON_STAT_CMP7_UV_OK,VMON status register for comparator 7.1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 8. "VMON_STAT_CMP5_UV_OK,VMON status register for comparator 5. 1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 7. "VMON_STAT_CMP5_OV_OK,VMON status register for comparator 5." "0,1" newline bitfld.long 0x0 6. "VMON_STAT_CMP3_UV_OK,VMON status register for comparator 3.1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 5. "VMON_STAT_CMP3_OV_OK,VMON status register for comparator 3.1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" newline bitfld.long 0x0 4. "VMON_STAT_CMP2_UV_OK,VMON status register for comparator 2. 1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 3. "VMON_STAT_CMP2_OV_OK,VMON status register for comparator 2. 1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" newline bitfld.long 0x0 2. "VMON_STAT_CMP1_UV_OK,VMON status register for comparator 1. 1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" newline bitfld.long 0x0 1. "VMON_STAT_CMP1_OV_OK,VMON status register for comparator 1. 1'b1 - Comparator output is ok for over voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for over voltage condition" "0,1" newline bitfld.long 0x0 0. "VMON_STAT_CMP0_UV_OK,VMON status register for comparator 0. 1'b1 - Comparator output is ok for under voltage condition.1'b0 - Comparator output is 1'b0 as threshold condition is not meeting for under voltage condition" "0,1" line.long 0x4 "TOP_CTRL_PMU_COARSE_STAT,This register shows the status of coarse voltage monitors present in the device." bitfld.long 0x4 3. "PMU_COARSE_STAT_BG_RDY,Bandgap coarse detection status signals." "0,1" newline bitfld.long 0x4 2. "PMU_COARSE_STAT_LDO_RDY,LDO coarse detection status signals." "0,1" newline bitfld.long 0x4 1. "PMU_COARSE_STAT_VCORE_RDY,vcore coarse detection status signals." "0,1" newline bitfld.long 0x4 0. "PMU_COARSE_STAT_VSUP18_RDY,vdda18 coarse detection status signals." "0,1" group.long 0xC20++0x7 line.long 0x0 "TOP_CTRL_MASK_VMON_ERROR_ESM_H,This register is used to select the voltage monitors whose Error staus should triggering the ESM High Interrupt." bitfld.long 0x0 18. "MASK_VMON_ERROR_ESM_H_ADCR01_REF_UV_MASK,ADCR01 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 17. "MASK_VMON_ERROR_ESM_H_ADCR01_REF_OV_MASK,ADCR01 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 16. "MASK_VMON_ERROR_ESM_H_ADC12_REF_UV_MASK,ADC34 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 15. "MASK_VMON_ERROR_ESM_H_ADC12_REF_OV_MASK,ADC34 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 14. "MASK_VMON_ERROR_ESM_H_ADC0_REF_UV_MASK,ADC12 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 13. "MASK_VMON_ERROR_ESM_H_ADC0_REF_OV_MASK,ADC12 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 12. "MASK_VMON_ERROR_ESM_H_ADC34_REF_UV_MASK,ADC0 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 11. "MASK_VMON_ERROR_ESM_H_ADC34_REF_OV_MASK,ADC0 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 10. "MASK_VMON_ERROR_ESM_H_CMP8_UV_ERR_MASK,CMP8 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 9. "MASK_VMON_ERROR_ESM_H_CMP7_UV_ERR_MASK,CMP7 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 8. "MASK_VMON_ERROR_ESM_H_CMP5_UV_ERR_MASK,CMP5 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 7. "MASK_VMON_ERROR_ESM_H_CMP5_OV_ERR_MASK,CMP5 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 6. "MASK_VMON_ERROR_ESM_H_CMP3_UV_ERR_MASK,CMP3 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 5. "MASK_VMON_ERROR_ESM_H_CMP3_OV_ERR_MASK,CMP3 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 4. "MASK_VMON_ERROR_ESM_H_CMP2_UV_ERR_MASK,CMP2 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 3. "MASK_VMON_ERROR_ESM_H_CMP2_OV_ERR_MASK,CMP2 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 2. "MASK_VMON_ERROR_ESM_H_CMP1_UV_ERR_NASK,CMP1 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 1. "MASK_VMON_ERROR_ESM_H_CMP1_OV_ERR_MASK,CMP1 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x0 0. "MASK_VMON_ERROR_ESM_H_CMP0_UV_ERR_MASK,CMP0 UV VMON Error Mask to ESM Interrupt" "0,1" line.long 0x4 "TOP_CTRL_MASK_VMON_ERROR_ESM_L,This register is used to select the voltage monitors whose Error staus should triggering the ESM Low Interrupt." bitfld.long 0x4 18. "MASK_VMON_ERROR_ESM_L_ADCR01_REF_UV_MASK,ADCR01 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 17. "MASK_VMON_ERROR_ESM_L_ADCR01_REF_OV_MASK,ADCR01 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 16. "MASK_VMON_ERROR_ESM_L_ADC12_REF_UV_MASK,ADC34 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 15. "MASK_VMON_ERROR_ESM_L_ADC12_REF_OV_MASK,ADC34 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 14. "MASK_VMON_ERROR_ESM_L_ADC0_REF_UV_MASK,ADC12 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 13. "MASK_VMON_ERROR_ESM_L_ADC0_REF_OV_MASK,ADC12 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 12. "MASK_VMON_ERROR_ESM_L_ADC34_REF_UV_MASK,ADC0 REF UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 11. "MASK_VMON_ERROR_ESM_L_ADC34_REF_OV_MASK,ADC0 REF OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 10. "MASK_VMON_ERROR_ESM_L_CMP8_UV_ERR_MASK,CMP8 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 9. "MASK_VMON_ERROR_ESM_L_CMP7_UV_ERR_MASK,CMP7 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 8. "MASK_VMON_ERROR_ESM_L_CMP5_UV_ERR_MASK,CMP5 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 7. "MASK_VMON_ERROR_ESM_L_CMP5_OV_ERR_MASK,CMP5 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 6. "MASK_VMON_ERROR_ESM_L_CMP3_UV_ERR_MASK,CMP3 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 5. "MASK_VMON_ERROR_ESM_L_CMP3_OV_ERR_MASK,CMP3 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 4. "MASK_VMON_ERROR_ESM_L_CMP2_UV_ERR_MASK,CMP2 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 3. "MASK_VMON_ERROR_ESM_L_CMP2_OV_ERR_MASK,CMP2 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 2. "MASK_VMON_ERROR_ESM_L_CMP1_UV_ERR_NASK,CMP1 UV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 1. "MASK_VMON_ERROR_ESM_L_CMP1_OV_ERR_MASK,CMP1 OV VMON Error Mask to ESM Interrupt" "0,1" newline bitfld.long 0x4 0. "MASK_VMON_ERROR_ESM_L_CMP0_UV_ERR_MASK,CMP0 UV VMON Error Mask to ESM Interrupt" "0,1" group.long 0xC30++0x7 line.long 0x0 "TOP_CTRL_MASK_ANA_ISO,This register is used to prevent the Coarse voltage monitor from triggering a faulty SOC reset due to a momentary supply glitch caused when enabling ADC reference buffers." bitfld.long 0x0 0.--2. "MASK_ANA_ISO_MASK,Mask the Ana ISO generating SOC reset due to a glitch on VDD OK.Used during Trim updates to the analog or during ADC Refbuf enable" "0,1,2,3,4,5,6,7" line.long 0x4 "TOP_CTRL_VMON_FILTER_CTRL,This register is used to configure the filter present on the Voltage monitor outputs." bitfld.long 0x4 0.--1. "VMON_FILTER_CTRL_SELECT_VALUE,VMON FILTER control select2'b00 : no filtering [default]2'b01 : filtering for 4.8us2'b10 : filtering for 9.6us2'b11 : filtering for 14.4us**Note: This bit will only be reset by PORz." "0,1,2,3" group.long 0xC40++0x2B line.long 0x0 "TOP_CTRL_ADC_RNG_CTRL,ADC range control in single ended mode." bitfld.long 0x0 8.--9. "ADC_RNG_CTRL_SCALED_MODE,This bit controls scaled mode for resolver adc's2'b0 --> Normal output2'b1 --> scale 04223in 04095[efectively supporting 0-3.3V in 12 bit space] [in 12bit mode only]bit8 corresponds to adc_r0bit9 corresponds to adc_r1" "0,1,2,3" newline hexmask.long.byte 0x0 0.--6. 1. "ADC_RNG_CTRL_MODE,Single-Ended Mode 0 ADC Input supports 0 to Vref*32/1. 0V corresponds to all zero code and 3.2V corresponds to all 1 or code40951 ADC Input supports Vref*1/18 to Vref*33/18. Vref*1/18 corresponds to all zero code and Vref*32/18.." line.long 0x4 "TOP_CTRL_ADC0_OSD_CHEN,ADC Channel enable for Open Short detection." hexmask.long.byte 0x4 0.--5. 1. "ADC0_OSD_CHEN_CH_OSD_EN,Controls enabling the channel for ADC when set to 1'b1. Each bit corresponds to the respective ADC channel -Bit 0 - ch0_osd_enBit 1 - ch1_osd_enBit 2 - ch2_osd_enBit 3 - ch3_osd_enBit 4 - ch4_osd_enBit 5 - ch5_osd_en" line.long 0x8 "TOP_CTRL_ADC1_OSD_CHEN,ADC Channel enable for Open Short detection." hexmask.long.byte 0x8 0.--5. 1. "ADC1_OSD_CHEN_CH_OSD_EN,Controls enabling the channel for ADC when set to 1'b1. Each bit corresponds to the respective ADC channel -Bit 0 - ch0_osd_enBit 1 - ch1_osd_enBit 2 - ch2_osd_enBit 3 - ch3_osd_enBit 4 - ch4_osd_enBit 5 - ch5_osd_en" line.long 0xC "TOP_CTRL_ADC2_OSD_CHEN,ADC Channel enable for Open Short detection." hexmask.long.byte 0xC 0.--5. 1. "ADC2_OSD_CHEN_CH_OSD_EN,Controls enabling the channel for ADC when set to 1'b1. Each bit corresponds to the respective ADC channel -Bit 0 - ch0_osd_enBit 1 - ch1_osd_enBit 2 - ch2_osd_enBit 3 - ch3_osd_enBit 4 - ch4_osd_enBit 5 - ch5_osd_en" line.long 0x10 "TOP_CTRL_ADC3_OSD_CHEN,ADC Channel enable for Open Short detection." hexmask.long.byte 0x10 0.--5. 1. "ADC3_OSD_CHEN_CH_OSD_EN,Controls enabling the channel for ADC when set to 1'b1. Each bit corresponds to the respective ADC channel -Bit 0 - ch0_osd_enBit 1 - ch1_osd_enBit 2 - ch2_osd_enBit 3 - ch3_osd_enBit 4 - ch4_osd_enBit 5 - ch5_osd_en" line.long 0x14 "TOP_CTRL_ADC4_OSD_CHEN,ADC Channel enable for Open Short detection." hexmask.long.byte 0x14 0.--5. 1. "ADC4_OSD_CHEN_CH_OSD_EN,Controls enabling the channel for ADC when set to 1'b1. Each bit corresponds to the respective ADC channel -Bit 0 - ch0_osd_enBit 1 - ch1_osd_enBit 2 - ch2_osd_enBit 3 - ch3_osd_enBit 4 - ch4_osd_enBit 5 - ch5_osd_en" line.long 0x18 "TOP_CTRL_ADC0_OSD_CTRL,ADC open short function controls." bitfld.long 0x18 0.--2. "ADC0_OSD_CTRL_FUNCTION,Controls the shorting of internal 5K 11K resistor to the ADC channel for open short detection [Default 0] value function Impedance 5K voltage 7K voltage3'b000 Zero Scale 5K || 7K vssa.." "0,1,2,3,4,5,6,7" line.long 0x1C "TOP_CTRL_ADC1_OSD_CTRL,ADC open short function controls." bitfld.long 0x1C 0.--2. "ADC1_OSD_CTRL_FUNCTION,Controls the shorting of internal 5K 11K resistor to the ADC channel for open short detection [Default 0] value function Impedance 5K voltage 7K voltage3'b000 Zero Scale 5K || 7K vssa.." "0,1,2,3,4,5,6,7" line.long 0x20 "TOP_CTRL_ADC2_OSD_CTRL,ADC open short function controls." bitfld.long 0x20 0.--2. "ADC2_OSD_CTRL_FUNCTION,Controls the shorting of internal 5K 11K resistor to the ADC channel for open short detection [Default 0] value function Impedance 5K voltage 7K voltage3'b000 Zero Scale 5K || 7K vssa.." "0,1,2,3,4,5,6,7" line.long 0x24 "TOP_CTRL_ADC3_OSD_CTRL,ADC open short function controls." bitfld.long 0x24 0.--2. "ADC3_OSD_CTRL_FUNCTION,Controls the shorting of internal 5K 11K resistor to the ADC channel for open short detection [Default 0] value function Impedance 5K voltage 7K voltage3'b000 Zero Scale 5K || 7K vssa.." "0,1,2,3,4,5,6,7" line.long 0x28 "TOP_CTRL_ADC4_OSD_CTRL,ADC open short function controls." bitfld.long 0x28 0.--2. "ADC4_OSD_CTRL_FUNCTION,Controls the shorting of internal 5K 11K resistor to the ADC channel for open short detection [Default 0] value function Impedance 5K voltage 7K voltage3'b000 Zero Scale 5K || 7K vssa.." "0,1,2,3,4,5,6,7" group.long 0xC80++0x17 line.long 0x0 "TOP_CTRL_ADC_LOOPBACK_CTRL,Controls loopback safety functionality from DAC output to ADC inputs." bitfld.long 0x0 0. "ADC_LOOPBACK_CTRL_ADC_LOOPBACK_EN,Controls ADC loopback 1'b1: loopback enabled 1'b0: loopback disabled[default]" "0: loopback disabled[default],1: loopback enabled" line.long 0x4 "TOP_CTRL_CMPSSA_LOOPBACK_CTRL,Controls loopback safety functionality from DAC output to ADC inputs." bitfld.long 0x4 25. "CMPSSA_LOOPBACK_CTRL_CMPSSH9_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 24. "CMPSSA_LOOPBACK_CTRL_CMPSSH8_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 23. "CMPSSA_LOOPBACK_CTRL_CMPSSH7_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 22. "CMPSSA_LOOPBACK_CTRL_CMPSSH6_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 21. "CMPSSA_LOOPBACK_CTRL_CMPSSH5_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 20. "CMPSSA_LOOPBACK_CTRL_CMPSSH4_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 19. "CMPSSA_LOOPBACK_CTRL_CMPSSH3_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 18. "CMPSSA_LOOPBACK_CTRL_CMPSSH2_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 17. "CMPSSA_LOOPBACK_CTRL_CMPSSH1_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 16. "CMPSSA_LOOPBACK_CTRL_CMPSSH0_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 9. "CMPSSA_LOOPBACK_CTRL_CMPSSL9_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 8. "CMPSSA_LOOPBACK_CTRL_CMPSSL8_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 7. "CMPSSA_LOOPBACK_CTRL_CMPSSL7_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 6. "CMPSSA_LOOPBACK_CTRL_CMPSSL6_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 5. "CMPSSA_LOOPBACK_CTRL_CMPSSL5_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 4. "CMPSSA_LOOPBACK_CTRL_CMPSSL4_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 3. "CMPSSA_LOOPBACK_CTRL_CMPSSL3_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 2. "CMPSSA_LOOPBACK_CTRL_CMPSSL2_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 1. "CMPSSA_LOOPBACK_CTRL_CMPSSL1_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x4 0. "CMPSSA_LOOPBACK_CTRL_CMPSSL0_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" line.long 0x8 "TOP_CTRL_CMPSSB_LOOPBACK_CTRL,Controls loopback safety functionality from DAC output to ADC inputs." bitfld.long 0x8 25. "CMPSSB_LOOPBACK_CTRL_CMPSSH9_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 24. "CMPSSB_LOOPBACK_CTRL_CMPSSH8_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 23. "CMPSSB_LOOPBACK_CTRL_CMPSSH7_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 22. "CMPSSB_LOOPBACK_CTRL_CMPSSH6_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 21. "CMPSSB_LOOPBACK_CTRL_CMPSSH5_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 20. "CMPSSB_LOOPBACK_CTRL_CMPSSH4_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 19. "CMPSSB_LOOPBACK_CTRL_CMPSSH3_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 18. "CMPSSB_LOOPBACK_CTRL_CMPSSH2_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 17. "CMPSSB_LOOPBACK_CTRL_CMPSSH1_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 16. "CMPSSB_LOOPBACK_CTRL_CMPSSH0_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 9. "CMPSSB_LOOPBACK_CTRL_CMPSSL9_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 8. "CMPSSB_LOOPBACK_CTRL_CMPSSL8_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 7. "CMPSSB_LOOPBACK_CTRL_CMPSSL7_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 6. "CMPSSB_LOOPBACK_CTRL_CMPSSL6_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 5. "CMPSSB_LOOPBACK_CTRL_CMPSSL5_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 4. "CMPSSB_LOOPBACK_CTRL_CMPSSL4_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 3. "CMPSSB_LOOPBACK_CTRL_CMPSSL3_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 2. "CMPSSB_LOOPBACK_CTRL_CMPSSL2_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 1. "CMPSSB_LOOPBACK_CTRL_CMPSSL1_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" newline bitfld.long 0x8 0. "CMPSSB_LOOPBACK_CTRL_CMPSSL0_LOOPBACK_EN,Controls CMPSS loopback enable1'b1 : loopback enabled 1'b0 : loopback disabled[default]" "0: loopback disabled[default],?" line.long 0xC "TOP_CTRL_ADCR01_OSD_CHEN,ADCR Channel enable for Open Short detection." hexmask.long.byte 0xC 0.--7. 1. "ADCR01_OSD_CHEN_CH_OSD_EN,Controls enabling the channel for ADC when set to 1'b1. Each bit corresponds to the respective ADC channel -Bit 0 - ch0_osd_enBit 1 - ch1_osd_enBit 2 - ch2_osd_enBit 3 - ch3_osd_enBit 4 - ch4_osd_enBit 5 - ch5_osd_en" line.long 0x10 "TOP_CTRL_ADCR01_OSD_CTRL,ADCR open short function controls." bitfld.long 0x10 0.--2. "ADCR01_OSD_CTRL_FUNCTION,Controls the shorting of internal 5K 11K resistor to the ADC channel for open short detection [Default 0] value function Impedance 5K voltage 7K voltage3'b000 Zero Scale 5K || 7K vssa.." "0,1,2,3,4,5,6,7" line.long 0x14 "TOP_CTRL_ADC_REFBUF2_CTRL,This register is used to enable or disable ADC Reference buffer 2" bitfld.long 0x14 0.--2. "ADC_REFBUF2_CTRL_ENABLE,Enables adc reference 0 mask hhv before enable000:Disable111 : Enable" "0,1,2,3,4,5,6,7" group.long 0xD00++0x3 line.long 0x0 "TOP_CTRL_TSENSE_CFG,This register is used to enableand configure the Teperature sensors present in the device ." bitfld.long 0x0 28. "TSENSE_CFG_TMPSOFF,BandGap on/off control 1'b1 : off 1'b0 : on**Note: This bit will only be reset by PORz." "0: on**Note: This bit will only be reset by PORz,1: off" newline bitfld.long 0x0 24. "TSENSE_CFG_BGROFF,BandGap on/off control 1'b1 : off 1'b0 : on**Note: This bit will only be reset by PORz." "0: on**Note: This bit will only be reset by PORz,1: off" newline bitfld.long 0x0 20. "TSENSE_CFG_AIPOFF,1'b1 : iddq mode select 1'b0 : normal mode**Note: This bit will only be reset by PORz." "0: normal mode**Note: This bit will only be reset..,1: iddq mode select" newline bitfld.long 0x0 16. "TSENSE_CFG_SNSR_MX_HIZ,Sensor mux hiz control1'b0 : normal operation. Mux will select either one of the anlaog sensor 1'b1 : mux will be high impedence**Note: This bit will only be reset by PORz." "?,1: mux will be high impedence**Note: This bit will.." newline hexmask.long.byte 0x0 8.--13. 1. "TSENSE_CFG_DELAY,Number of wait clock cycles between each TMPS Readout. Configure a Non zero value as delay value since configuring 0 is not allowed**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x0 4.--7. 1. "TSENSE_CFG_SENSOR_SEL,Sensor Selection sensor enable bits for each sensor 1'b0 : sensor disable 1'b1 : sensor enablebit3: temp_sensor3bit2: temp_sensor2bit1: temp_sensor1bit0: temp_sensor0**Note: This bit will only be reset by PORz." newline bitfld.long 0x0 0. "TSENSE_CFG_ENABLE,Temperature controller enable**Note: This bit will only be reset by PORz." "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "TOP_CTRL_TSENSE_STATUS,This register shows the status of Temperature comparator events which are unmasked." bitfld.long 0x0 6. "TSENSE_STATUS_S1_HOT,temperature Sensor 1 hot event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x0 5. "TSENSE_STATUS_S1_COLD,temperature Sensor 1 cold event detect1'b0 : event not occured1'b1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x0 4. "TSENSE_STATUS_S1_LOW_THRHLD,temperature Sensor 1 low threshold event detect1'b0 : event not occured1'b1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x0 2. "TSENSE_STATUS_S0_HOT,temperature Sensor 0 hot event detect1'b0 : event not occured1'b1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x0 1. "TSENSE_STATUS_S0_COLD,temperature Sensor 0 cold event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x0 0. "TSENSE_STATUS_S0_LOW_THRHLD,temperature Sensor 0 low threshold event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" line.long 0x4 "TOP_CTRL_TSENSE_STATUS_RAW,This register shows the status of all Temperature comparators events including masked events." bitfld.long 0x4 6. "TSENSE_STATUS_RAW_S1_HOT,temperature Sensor 1 hot event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 5. "TSENSE_STATUS_RAW_S1_COLD,temperature Sensor 1 cold event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 4. "TSENSE_STATUS_RAW_S1_LOW_THRHLD,temperature Sensor 1 low threshold event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 2. "TSENSE_STATUS_RAW_S0_HOT,temperature Sensor 0 hot event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 1. "TSENSE_STATUS_RAW_S0_COLD,temperature Sensor 0 cold event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 0. "TSENSE_STATUS_RAW_S0_LOW_THRHLD,temperature Sensor 0 low threshold event detect0 : event not occured1 : event occurred**Note: This bit will only be reset by PORz." "0,1" group.long 0xD14++0x7 line.long 0x0 "TOP_CTRL_TSENSE0_ALERT,This register is used to configure the temperature thresholds for Temp Sensor 0 for generating Alert Interrupts." hexmask.long.byte 0x0 16.--23. 1. "TSENSE0_ALERT_ALERT_THRHLD_COLD,cold threshold/low temp threshold**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x0 0.--7. 1. "TSENSE0_ALERT_ALERT_THRHLD_HOT,Hot threshold/high temp threshold**Note: This bit will only be reset by PORz." line.long 0x4 "TOP_CTRL_TSENSE0_CNTL,This register is used to control and configure Temperature sensor 0" bitfld.long 0x4 24. "TSENSE0_CNTL_MASK_LOW_THRHLD,mask low threshold comparator output**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 20. "TSENSE0_CNTL_MASK_HOT,Mask hot comparator output**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 16. "TSENSE0_CNTL_MASK_COLD,mask cold comparator output**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 8. "TSENSE0_CNTL_ACCU_CLEAR,Accumulator clear**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 4. "TSENSE0_CNTL_FIFO_FREEZE,fifo freeze**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x4 0. "TSENSE0_CNTL_FIFO_CLEAR,fifo clear**Note: This bit will only be reset by PORz." "0,1" rgroup.long 0xD1C++0x17 line.long 0x0 "TOP_CTRL_TSENSE0_RESULT,This register shows the most recent temperature readout and status of any ongoing Temperature measurement from Temperature Sensor 0" bitfld.long 0x0 16. "TSENSE0_RESULT_ECOZ,Conversion in Progress.1'b1 : Conversion on going1'b0 : conversion completed**Note: This bit will only be reset by PORz." "?,1: Conversion on going1'b0 : conversion.." newline hexmask.long.byte 0x0 0.--7. 1. "TSENSE0_RESULT_DTEMP,Temp Code readout**Note: This bit will only be reset by PORz." line.long 0x4 "TOP_CTRL_TSENSE0_DATA0,Temp Sensor 0 Result FIFO Register 0" hexmask.long.tbyte 0x4 8.--31. 1. "TSENSE0_DATA0_TAG,Tag for temperature sesnor 0 Data 0 measured**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x4 0.--7. 1. "TSENSE0_DATA0_DATA,Temperature Sensor0 FIFO data 0**Note: This bit will only be reset by PORz." line.long 0x8 "TOP_CTRL_TSENSE0_DATA1,Temp Sensor 0 Result FIFO Register 1" hexmask.long.tbyte 0x8 8.--31. 1. "TSENSE0_DATA1_TAG,Tag for temperature sesnor 0 Data 1 measured**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x8 0.--7. 1. "TSENSE0_DATA1_DATA,Temperature Sensor0 FIFO data 1**Note: This bit will only be reset by PORz." line.long 0xC "TOP_CTRL_TSENSE0_DATA2,Temp Sensor 0 Result FIFO Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "TSENSE0_DATA2_TAG,Tag for temperature sesnor 0 Data 2 measured**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0xC 0.--7. 1. "TSENSE0_DATA2_DATA,Temperature Sensor 0 FIFO data 2**Note: This bit will only be reset by PORz." line.long 0x10 "TOP_CTRL_TSENSE0_DATA3,Temp Sensor 0 Result FIFO Register 3" hexmask.long.tbyte 0x10 8.--31. 1. "TSENSE0_DATA3_TAG,Tag for temperature sesnor 0 Data 3 measured**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x10 0.--7. 1. "TSENSE0_DATA3_DATA,Temperature Sensor 0 FIFO data 3**Note: This bit will only be reset by PORz." line.long 0x14 "TOP_CTRL_TSENSE0_ACCU,Temp Sensor 0 Result Accumulator Register." hexmask.long 0x14 0.--31. 1. "TSENSE0_ACCU_CUMUL,cumulative sum of past DTEMPs**Note: This bit will only be reset by PORz." group.long 0xD40++0xB line.long 0x0 "TOP_CTRL_TSENSE1_TSHUT,This register is used to override the factory specified Tshut temperature with an application specific Tshut temperature for Temperature sensor 1" bitfld.long 0x0 29.--31. "TSENSE1_TSHUT_EFUSE_OVERRIDE,Efuse override3'b000 -- Value from EFUSE is used as tshut hot and tshut cold thresholds3'b111 - Overide value takes effect**Note: This bit will only be reset by PORz." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--23. 1. "TSENSE1_TSHUT_TSHUT_THRHLD_HOT,tshut hot threshold. Reads efuse value untill overwritten with override = 111**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x0 0.--7. 1. "TSENSE1_TSHUT_TSHUT_THRSHLD_COLD,tshut cold threshold. Reads efuse value untill overwritten with override = 111**Note: This bit will only be reset by PORz." line.long 0x4 "TOP_CTRL_TSENSE1_ALERT,This register is used to configure the temperature thresholds for Temp Sensor 1 for generating Alert Interrupts." hexmask.long.byte 0x4 16.--23. 1. "TSENSE1_ALERT_ALERT_THRHLD_COLD,cold threshold/low temp threshold**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x4 0.--7. 1. "TSENSE1_ALERT_ALERT_THRHLD_HOT,Hot threshold/high temp threshold**Note: This bit will only be reset by PORz." line.long 0x8 "TOP_CTRL_TSENSE1_CNTL,This register is used to control and configure Temperature sensor 1" bitfld.long 0x8 24. "TSENSE1_CNTL_MASK_LOW_THRHLD,mask low threshold comparator output**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x8 20. "TSENSE1_CNTL_MASK_HOT,Mask hot comparator output**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x8 16. "TSENSE1_CNTL_MASK_COLD,mask cold comparator output**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x8 8. "TSENSE1_CNTL_ACCU_CLEAR,Accumulator clear**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x8 4. "TSENSE1_CNTL_FIFO_FREEZE,fifo freeze**Note: This bit will only be reset by PORz." "0,1" newline bitfld.long 0x8 0. "TSENSE1_CNTL_FIFO_CLEAR,fifo clear**Note: This bit will only be reset by PORz." "0,1" rgroup.long 0xD4C++0x17 line.long 0x0 "TOP_CTRL_TSENSE1_RESULT,This register shows the most recent temperature readout and status of any ongoing Temperature measurement from Temperature Sensor 1" bitfld.long 0x0 16. "TSENSE1_RESULT_ECOZ,Conversion in Progress.1'b1 : Conversion on going1'b0 : conversion completed**Note: This bit will only be reset by PORz." "?,1: Conversion on going1'b0 : conversion.." newline hexmask.long.byte 0x0 0.--7. 1. "TSENSE1_RESULT_DTEMP,Temp Code readout**Note: This bit will only be reset by PORz." line.long 0x4 "TOP_CTRL_TSENSE1_DATA0,Temp Sensor 1 Result FIFO Register 0" hexmask.long.tbyte 0x4 8.--31. 1. "TSENSE1_DATA0_TAG,Tag for temperature sesnor 1 Data 0 measured**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x4 0.--7. 1. "TSENSE1_DATA0_DATA,Temperature sensor 1 FIFO Data 0**Note: This bit will only be reset by PORz." line.long 0x8 "TOP_CTRL_TSENSE1_DATA1,Temp Sensor 1 Result FIFO Register 1" hexmask.long.tbyte 0x8 8.--31. 1. "TSENSE1_DATA1_TAG,Temperature sensor 1 FIFO Data 1**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x8 0.--7. 1. "TSENSE1_DATA1_DATA,Temperature sensor 1 FIFO Data 1**Note: This bit will only be reset by PORz." line.long 0xC "TOP_CTRL_TSENSE1_DATA2,Temp Sensor 1 Result FIFO Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "TSENSE1_DATA2_TAG,Temperature sensor 1 FIFO Data 2**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0xC 0.--7. 1. "TSENSE1_DATA2_DATA,Temperature sensor 1 FIFO Data 2**Note: This bit will only be reset by PORz." line.long 0x10 "TOP_CTRL_TSENSE1_DATA3,Temp Sensor 1 Result FIFO Register 3" hexmask.long.tbyte 0x10 8.--31. 1. "TSENSE1_DATA3_TAG,Temperature sensor 1 FIFO Data 3**Note: This bit will only be reset by PORz." newline hexmask.long.byte 0x10 0.--7. 1. "TSENSE1_DATA3_DATA,Temperature sensor 1 FIFO Data 3**Note: This bit will only be reset by PORz." line.long 0x14 "TOP_CTRL_TSENSE1_ACCU,Temp Sensor 1 Result Accumulator Register." hexmask.long 0x14 0.--31. 1. "TSENSE1_ACCU_CUMUL,cumulative sum of past DTEMPs**Note: This bit will only be reset by PORz." rgroup.long 0xD7C++0x3 line.long 0x0 "TOP_CTRL_TSENSE2_RESULT,This register shows the most recent temperature readout and status of any ongoing Temperature measurement from Temperature Sensor 2" bitfld.long 0x0 16. "TSENSE2_RESULT_ECOZ,Conversion in Progress.1'b1 : Conversion on going1'b0 : conversion completed**Note: This bit will only be reset by PORz." "?,1: Conversion on going1'b0 : conversion.." newline hexmask.long.byte 0x0 0.--7. 1. "TSENSE2_RESULT_DTEMP,Temp Code readout**Note: This bit will only be reset by PORz." rgroup.long 0xDAC++0x3 line.long 0x0 "TOP_CTRL_TSENSE3_RESULT,This register shows the most recent temperature readout and status of any ongoing Temperature measurement from Temperature Sensor 3" bitfld.long 0x0 16. "TSENSE3_RESULT_ECOZ,Conversion in Progress.1'b1 : Conversion on going1'b0 : conversion completed**Note: This bit will only be reset by PORz." "?,1: Conversion on going1'b0 : conversion.." newline hexmask.long.byte 0x0 0.--7. 1. "TSENSE3_RESULT_DTEMP,Temp Code readout**Note: This bit will only be reset by PORz." group.long 0xFD0++0xF line.long 0x0 "TOP_CTRL_HW_SPARE_RW0,HW_SPARE_RW0." hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0_HW_SPARE_RW0,Reserved for HW R&D" line.long 0x4 "TOP_CTRL_HW_SPARE_RW1,HW_SPARE_RW1." hexmask.long 0x4 0.--31. 1. "HW_SPARE_RW1_HW_SPARE_RW1,Reserved for HW R&D" line.long 0x8 "TOP_CTRL_HW_SPARE_RW2,HW_SPARE_RW2." hexmask.long 0x8 0.--31. 1. "HW_SPARE_RW2_HW_SPARE_RW2,Reserved for HW R&D" line.long 0xC "TOP_CTRL_HW_SPARE_RW3,HW_SPARE_RW3." hexmask.long 0xC 0.--31. 1. "HW_SPARE_RW3_HW_SPARE_RW3,Reserved for HW R&D" rgroup.long 0xFE0++0xF line.long 0x0 "TOP_CTRL_HW_SPARE_RO0,HW_SPARE_RO0." hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO0_HW_SPARE_RO0,Reserved for HW R&D" line.long 0x4 "TOP_CTRL_HW_SPARE_RO1,HW_SPARE_RO1." hexmask.long 0x4 0.--31. 1. "HW_SPARE_RO1_HW_SPARE_RO1,Reserved for HW R&D" line.long 0x8 "TOP_CTRL_HW_SPARE_RO2,HW_SPARE_RO2." hexmask.long 0x8 0.--31. 1. "HW_SPARE_RO2_HW_SPARE_RO2,Reserved for HW R&D" line.long 0xC "TOP_CTRL_HW_SPARE_RO3,HW_SPARE_RO3." hexmask.long 0xC 0.--31. 1. "HW_SPARE_RO3_HW_SPARE_RO3,Reserved for HW R&D" group.long 0xFF0++0x7 line.long 0x0 "TOP_CTRL_HW_SPARE_WPH,HW_SPARE_WPH." hexmask.long 0x0 0.--31. 1. "HW_SPARE_WPH_HW_SPARE_WPH,Reserved for HW R&D" line.long 0x4 "TOP_CTRL_HW_SPARE_REC,HW_SPARE_REC." bitfld.long 0x4 31. "HW_SPARE_REC_HW_SPARE_REC31,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 30. "HW_SPARE_REC_HW_SPARE_REC30,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 29. "HW_SPARE_REC_HW_SPARE_REC29,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 28. "HW_SPARE_REC_HW_SPARE_REC28,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 27. "HW_SPARE_REC_HW_SPARE_REC27,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 26. "HW_SPARE_REC_HW_SPARE_REC26,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 25. "HW_SPARE_REC_HW_SPARE_REC25,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 24. "HW_SPARE_REC_HW_SPARE_REC24,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 23. "HW_SPARE_REC_HW_SPARE_REC23,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 22. "HW_SPARE_REC_HW_SPARE_REC22,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 21. "HW_SPARE_REC_HW_SPARE_REC21,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 20. "HW_SPARE_REC_HW_SPARE_REC20,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 19. "HW_SPARE_REC_HW_SPARE_REC19,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 18. "HW_SPARE_REC_HW_SPARE_REC18,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 17. "HW_SPARE_REC_HW_SPARE_REC17,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 16. "HW_SPARE_REC_HW_SPARE_REC16,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 15. "HW_SPARE_REC_HW_SPARE_REC15,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 14. "HW_SPARE_REC_HW_SPARE_REC14,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 13. "HW_SPARE_REC_HW_SPARE_REC13,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 12. "HW_SPARE_REC_HW_SPARE_REC12,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 11. "HW_SPARE_REC_HW_SPARE_REC11,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 10. "HW_SPARE_REC_HW_SPARE_REC10,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 9. "HW_SPARE_REC_HW_SPARE_REC9,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 8. "HW_SPARE_REC_HW_SPARE_REC8,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 7. "HW_SPARE_REC_HW_SPARE_REC7,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 6. "HW_SPARE_REC_HW_SPARE_REC6,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 5. "HW_SPARE_REC_HW_SPARE_REC5,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 4. "HW_SPARE_REC_HW_SPARE_REC4,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 3. "HW_SPARE_REC_HW_SPARE_REC3,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 2. "HW_SPARE_REC_HW_SPARE_REC2,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 1. "HW_SPARE_REC_HW_SPARE_REC1,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 0. "HW_SPARE_REC_HW_SPARE_REC0,Reserved for HW R&D" "0,1" group.long 0x1008++0x1B line.long 0x0 "TOP_CTRL_LOCK0_KICK0,- KICK0 component." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "TOP_CTRL_LOCK0_KICK1,- KICK1 component." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "TOP_CTRL_INTR_RAW_STATUS,Interrupt Raw Status/Set Register." bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "TOP_CTRL_INTR_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear register." bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "TOP_CTRL_INTR_ENABLE,Interrupt Enable register." bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "TOP_CTRL_INTR_ENABLE_CLEAR,Interrupt Enable Clear register." bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "TOP_CTRL_EOI,EOI register." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "TOP_CTRL_FAULT_ADDRESS,Fault Address register." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "TOP_CTRL_FAULT_TYPE_STATUS,Fault Type Status register." bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." line.long 0x8 "TOP_CTRL_FAULT_ATTR_STATUS,Fault Attribute Status register." hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "TOP_CTRL_FAULT_CLEAR,Fault Clear register." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree "TOP_RCM" base ad:0x53200000 group.long 0x4++0x7 line.long 0x0 "TOP_RCM_WARM_RESET_CONFIG,Warm Reset Config options." bitfld.long 0x0 28.--30. "WARM_RESET_CONFIG_WDOG3_RST_EN,Enable/Disable WATCHDOG3 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog Write 3'b111 enable corresponding Watchdog" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "WARM_RESET_CONFIG_WDOG2_RST_EN,Enable/Disable WATCHDOG2 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog Write 3'b111 enable corresponding Watchdog" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WARM_RESET_CONFIG_WDOG1_RST_EN,Enable/Disable WATCHDOG1 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog Write 3'b111 enable corresponding Watchdog" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "WARM_RESET_CONFIG_WDOG0_RST_EN,Enable/Disable WATCHDOG0 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog Write 3'b111 enable corresponding Watchdog" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WARM_RESET_CONFIG_TSENSE1_RST_EN,Enable/Disable TEMPSENSE1 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable temperature sensor 1 Write 3'b111 to enable temperature sensor 1 **Note: This bit will only be reset by PORz." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "WARM_RESET_CONFIG_TSENSE0_RST_EN,Enable/Disable TEMPSENSE0 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable temperature sensor 0 Write 3'b111 to enable temperature sensor 0 **Note: This bit will only be reset by PORz." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WARM_RESET_CONFIG_DEBUGSS_RST_EN,Enable/Disable DEBUGSS triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable debugger control on Warm ResetWrite 3'b111 enable debugger control on Warm Reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "WARM_RESET_CONFIG_PAD_BYPASS,Bypass the Warm reset from Pad InputData should be loaded as multibit. Write 3'b000 : Pad Warm Reset pin has control over warm resetWrite 3'b111 : Pad warm reset pin has no control on warm reset**Note: This bit will only be.." "0,1,2,3,4,5,6,7" line.long 0x4 "TOP_RCM_WARM_RESET_REQ,Warm Reset Config options." bitfld.long 0x4 0.--2. "WARM_RESET_REQ_SW_RST,Data should be loaded as multibit. Write 3'b000 to assert warm reset from SWWrite 3'b111 to deassert warm reset from SW if this is the only source of warm reset" "0,1,2,3,4,5,6,7" rgroup.long 0xC++0x3 line.long 0x0 "TOP_RCM_WARM_RST_CAUSE,Warm Reset Cause Register." hexmask.long.tbyte 0x0 0.--23. 1. "WARM_RST_CAUSE_CAUSE,Warm Reset Cause register 24'h000041 - POR reset 24'h000042 - Warm reset due to MSS_WDT0 24'h000044 - Warm reset due to MSS_WDT1.." group.long 0x10++0xF line.long 0x0 "TOP_RCM_WARM_RST_CAUSE_CLR,Warm Reset Cause Register Clear." bitfld.long 0x0 0.--2. "WARM_RST_CAUSE_CLR_CLEAR,Write pulse bit field to 3'b111: Data should be loaded as multibit. Warm Reset Cause register Clear" "0,1,2,3,4,5,6,7" line.long 0x4 "TOP_RCM_RCOSC32K_CTRL,RC OSC 32KHz clock control." bitfld.long 0x4 0.--2. "RCOSC32K_CTRL_STOPOSC,Stop 32KHz RCOSC. Write 3'b111 to stop clock" "0,1,2,3,4,5,6,7" line.long 0x8 "TOP_RCM_LIMP_MODE_EN,Control to enabled limp mode." bitfld.long 0x8 8.--10. "LIMP_MODE_EN_COREPLL_LOSS_EN,Enable for core pll phase lock loss to generate Limp mode3'b000: will not generate Limp mode [multibit 000]3'b111 : will generate Limp mode [multibit 111]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "LIMP_MODE_EN_XTALCLK_LOSS_EN,Enable for crystal_clock_loss to generate Limp mode3'b000: will not generate Limp mode [multibit 000]3'b111 : will generate Limp mode [multibit 111]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "LIMP_MODE_EN_DCC0_ERROR_EN,Enable DCC0 Error to generate Limp mode 3'b000: DCC0 Error will not generate Limp mode [multibit 000]3'b111 : DCC0 Error will generate Limp mode [multibit 111]" "0,1,2,3,4,5,6,7" line.long 0xC "TOP_RCM_PLL_REF_CLK_SRC_SEL,CORE PLL and PERI PLL reference clock select." bitfld.long 0xC 4.--6. "PLL_REF_CLK_SRC_SEL_PLL_PERI_REF_CLK_SRC_SEL,Mux selct for PERI PLL REF clockWrite 3'b111 : to select external reference clock as PLL reference clockWrite 3'b000 : to select on-die clock as PLL reference clock" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "PLL_REF_CLK_SRC_SEL_PLL_CORE_REF_CLK_SRC_SEL,Mux selct for CORE PLL REF clockWrite 3'b111 : to select external reference clock as PLL reference clockWrite 3'b000 : to select on-die clock as PLL reference clock" "0,1,2,3,4,5,6,7" rgroup.long 0x24++0x7 line.long 0x0 "TOP_RCM_SOP_MODE_VALUE,Sense on Power mode value." hexmask.long 0x0 0.--31. 1. "SOP_MODE_VALUE_VAL,Bootmode (SOP_MODE) values and their corresponding mapping SOP3 SOP2 SOP1 SOP0 Bootmode 0 0 0 0 OSPI Functional Mode[4S] 0.." line.long 0x4 "TOP_RCM_CLK_LOSS_STATUS,Coarse detection clock loss status for RC and Crystal." bitfld.long 0x4 8. "CLK_LOSS_STATUS_RC_GOOD_BOOT,Clock status of RC clock at boot. Reset value will reflect the actual status1 --> clock present at boot0 --> clock not present at boot" "0,1" newline bitfld.long 0x4 4. "CLK_LOSS_STATUS_RC_CLOCK_LOSS,Coarse detection clock loss status for RC clock. Reset value will reflect the actual status1 --> clock lost0 --> clock good" "0,1" newline bitfld.long 0x4 0. "CLK_LOSS_STATUS_CRYSTAL_CLOCK_LOSS,Coarse detection clock loss status for Crystal clock. Reset value will reflect the actual status1 --> clock lost0 --> clock good" "0,1" group.long 0x30++0x17 line.long 0x0 "TOP_RCM_WARM_RSTTIME1,programing Output delay: time between internal warm reset source assert to warm reset pad deassert." hexmask.long.word 0x0 0.--11. 1. "WARM_RSTTIME1_DELAY,Program sufficient delay using this bitfield to keep the WARMRSTn pad active for any external devices relying on the reset signal. Refer to Reset Details Section in TRM for more details.Data should be loaded as multibit. For example:.." line.long 0x4 "TOP_RCM_WARM_RSTTIME2,programing input Rise delay : time between warm reset pad deassert to chip warm reset deassert." hexmask.long.word 0x4 0.--11. 1. "WARM_RSTTIME2_DELAY,Program the deassertion delay with this bitfield to control internal system reset deassertion which is relative to the deassertion of WARMRSTn pad.Data should be loaded as multibit. For example: if value of 0x5 should be selected.." line.long 0x8 "TOP_RCM_WARM_RSTTIME3,programing Input Fall delay : time between warm reset pad assert to chip warm reset assert." hexmask.long.word 0x8 0.--11. 1. "WARM_RSTTIME3_DELAY,The glitch filter logic will filter any input pad signal which is LOW for any time less than the delay programmed with this bit.This parameter also programmes the delay from external Warmrestn assertion to Internal system warm.." line.long 0xC "TOP_RCM_WARM_RESET_CONFIG_OV" bitfld.long 0xC 9.--11. "WARM_RESET_CONFIG_OV_VMON_CMP5_OV_RST_EN,Enable/Disable VMON Overvoltage CMP5 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_ov rst_en Write 3'b111 to enable vmon_ov rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 6.--8. "WARM_RESET_CONFIG_OV_VMON_CMP3_OV_RST_EN,Enable/Disable VMON Overvoltage CMP3 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_ov rst_en Write 3'b111 to enable vmon_ov rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 3.--5. "WARM_RESET_CONFIG_OV_VMON_CMP2_OV_RST_EN,Enable/Disable VMON Overvoltage CMP2 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_ov rst_en Write 3'b111 to enable vmon_ov rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "WARM_RESET_CONFIG_OV_VMON_CMP1_OV_RST_EN,Enable/Disable VMON Overvoltage CMP1 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_ov rst_en Write 3'b111 to enable vmon_ov rst_en**Note: This bit will only be reset by PORz." "0,1,2,3,4,5,6,7" line.long 0x10 "TOP_RCM_WARM_RESET_CONFIG_UV" bitfld.long 0x10 18.--20. "WARM_RESET_CONFIG_UV_VMON_CMP8_UV_RST_EN,Enable/Disable VMON Undervoltage CMP8 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "WARM_RESET_CONFIG_UV_VMON_CMP7_UV_RST_EN,Enable/Disable VMON Undervoltage CMP7 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "WARM_RESET_CONFIG_UV_VMON_CMP5_UV_RST_EN,Enable/Disable VMON Undervoltage CMP5 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "WARM_RESET_CONFIG_UV_VMON_CMP3_UV_RST_EN,Enable/Disable VMON Undervoltage CMP3 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "WARM_RESET_CONFIG_UV_VMON_CMP2_UV_RST_EN,Enable/Disable VMON Undervoltage CMP2 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "WARM_RESET_CONFIG_UV_VMON_CMP1_UV_RST_EN,Enable/Disable VMON Undervoltage CMP1 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "WARM_RESET_CONFIG_UV_VMON_CMP0_UV_RST_EN,Enable/Disable VMON Undervoltage CMP0 triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable vmon_uv rst_en Write 3'b111 to enable vmon_uv rst_en **Note: This bit will only be reset by.." "0,1,2,3,4,5,6,7" line.long 0x14 "TOP_RCM_WARM_RESET_CONFIG_MISC" bitfld.long 0x14 3.--5. "WARM_RESET_CONFIG_MISC_CLK_LOSS_SYS_CLK_RST_EN,Enable/Disable Clock loss on SYS_CLK triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable clk_loss on sys_clk rst_en Write 3'b111 to enable clk_loss on sys_clk rst_en" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "WARM_RESET_CONFIG_MISC_ESM_RST_EN,Enable/Disable ESM triggering Warm ResetData should be loaded as multibit. Write 3'b000 to disable esm rst_en Write 3'b111 to enable esm rst_en" "0,1,2,3,4,5,6,7" group.long 0x400++0x23 line.long 0x0 "TOP_RCM_PLL_CORE_PWRCTRL,Power control for Core PLL." bitfld.long 0x0 5. "PLL_CORE_PWRCTRL_PONIN,ON/OFF control of the weak power switch digital. For functionalmode it should be 1'b1" "0,1" newline bitfld.long 0x0 4. "PLL_CORE_PWRCTRL_PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1'b1" "0,1" newline bitfld.long 0x0 3. "PLL_CORE_PWRCTRL_RET,Save/Restore control for Retention mode. For functional mode itshould be 1'b0" "0,1" newline bitfld.long 0x0 2. "PLL_CORE_PWRCTRL_ISORET,Save/Restore control for Isolation of output pins For functional modeit should be 1'b0" "0,1" newline bitfld.long 0x0 1. "PLL_CORE_PWRCTRL_ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functionalmode it should be 1'b0" "0,1" newline bitfld.long 0x0 0. "PLL_CORE_PWRCTRL_OFFMODE,Used to switch OFF the logic on VDDA. For functional mode itshould be 1'b0" "0,1" line.long 0x4 "TOP_RCM_PLL_CORE_CLKCTRL,Clock control for Core PLL." bitfld.long 0x4 31. "PLL_CORE_CLKCTRL_CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK. Cycleslip could be caused if loop is not able to track input clock. Default = 1'b0 recommended" "0,1" newline bitfld.long 0x4 30. "PLL_CORE_CLKCTRL_ENSSC,Controls Clock SpReading. SSC is not supported. Should be set to 0x0 to disable clock spReading." "0,1" newline bitfld.long 0x4 29. "PLL_CORE_CLKCTRL_CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO0x0 : synchronously disables CLKDCOLDO0x1 : synchronously enables CLKDCOLDO" "0,1" newline bitfld.long 0x4 23. "PLL_CORE_CLKCTRL_IDLE,Sets PLL to Idle mode0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go toActive and Locked0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go toIdle Bypass low powe" "0,1" newline bitfld.long 0x4 22. "PLL_CORE_CLKCTRL_BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In generalthis input is expected to be tied to static low. For the output clocks ofthe module that do not have an internal bypass mux viz.CLKDCOLDO and CLKOUTLDO a bypass.." "0,1" newline bitfld.long 0x4 21. "PLL_CORE_CLKCTRL_STBYRET,Standby retention control0x0 : prepares ADPLLLJ for relock when out of retention byremoving the gating on all internal clocks.0x1 : prepares ADPLLLJ for retention by gating all the internalclocks." "?,1: prepares ADPLLLJ for retention by gating all the.." newline bitfld.long 0x4 20. "PLL_CORE_CLKCTRL_CLKOUTEN,CLKOUT enable or disable0x0 : synchronously disables CLKOUT0x1 : synchronously enables CLKOUT" "0,1" newline bitfld.long 0x4 19. "PLL_CORE_CLKCTRL_CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO,1: synchronously enables CLKOUTLDO" newline bitfld.long 0x4 18. "PLL_CORE_CLKCTRL_ULOWCLKEN,Select CLKOUT source in bypass0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/[N2+1]0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "0,1" newline bitfld.long 0x4 17. "PLL_CORE_CLKCTRL_CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1" newline bitfld.long 0x4 16. "PLL_CORE_CLKCTRL_M2PWDNZ,M2 divider power down mode0x0: Asynchronous power down for M2 divider0x1 : M2 divider is functional" "0,1" newline bitfld.long 0x4 14. "PLL_CORE_CLKCTRL_STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode,1: Stopmode" newline bitfld.long 0x4 10.--12. "PLL_CORE_CLKCTRL_SELFREQDCO,DCO Clock [DCOCLK = CLKINP * [M/[N+1]]] frequency rangeselector.0x0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz to1000MHz0x3: Reserved0x4: HS1: DCOCLK range is from1000MHz to2000MHz0x5: Reserved" "0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?" newline bitfld.long 0x4 8. "PLL_CORE_CLKCTRL_RELAXED_LOCK,Decides when FREQLOCK asserted0x0: FREQLOCK asserted when DC frequency error less than 1%0x1: FREQLOCK asserted when DC frequency error less than 2%" "0,1" newline bitfld.long 0x4 1. "PLL_CORE_CLKCTRL_SSCTYPE,SSC Type - This should be configured as 1'b0. The module supports spread spectrum clocking [SSC] on its output clocks." "0,1" newline bitfld.long 0x4 0. "PLL_CORE_CLKCTRL_TINTZ,PLL core soft reset. TINITZ activation [Low] gives softreset to ADPLLLJ. TINITZ does not reset the entire digital control logic; it forces the FSM into RESET State so that ADPLLLJ could restart." "0,1" line.long 0x8 "TOP_RCM_PLL_CORE_TENABLE,Trigger enable for core PLL." bitfld.long 0x8 0. "PLL_CORE_TENABLE_TENABLE,Signal TENABLE loads REGM REGN REGSD and SELFREQDCO data. M N. SD and SELFREQDCO latch [active rise edge]" "0,1" line.long 0xC "TOP_RCM_PLL_CORE_TENABLEDIV,Load Trigger for divider control value for Core PLL." bitfld.long 0xC 0. "PLL_CORE_TENABLEDIV_TENABLEDIV,TENABLEDIV rising edge loads the values of M2REG and N2REG into ADPLLLJ register. TENABLEDIV could be activated anytime when the DPLL digital is in power-up condition. M2 and N2 latch [active rise edge]" "0,1" line.long 0x10 "TOP_RCM_PLL_CORE_M2NDIV,M2N config register for core PLL." hexmask.long.byte 0x10 16.--22. 1. "PLL_CORE_M2NDIV_M2,Post-divider is REGM2" newline hexmask.long.byte 0x10 0.--7. 1. "PLL_CORE_M2NDIV_N,Pre-divider is REGN+1" line.long 0x14 "TOP_RCM_PLL_CORE_MN2DIV,MN2 config register for core PLL." hexmask.long.byte 0x14 16.--19. 1. "PLL_CORE_MN2DIV_N2,Bypass divider is REGN2+1" newline hexmask.long.word 0x14 0.--11. 1. "PLL_CORE_MN2DIV_M,Feedback Multiplier is REGM" line.long 0x18 "TOP_RCM_PLL_CORE_FRACDIV,Fractionsl divider and Sigma Delta config register for Core PLL." hexmask.long.byte 0x18 24.--31. 1. "PLL_CORE_FRACDIV_REGSD,Sigma-Delta DividerShould be set by s/w to provide optimum jitter performance.DPLL_SD_DIV = CEILING [[DPLL_MULT/[DPLL_DIV+1]] * CLKINP/ 250] where CLKINP is the input clock of the DPLL in MHz" newline hexmask.long.tbyte 0x18 0.--17. 1. "PLL_CORE_FRACDIV_FRACTIONALM,Fractional part of the M divider.The 18bit FractionalM value is loaded into DPLL on the rising edge of TENABLE signal .To enable Integer only division FractionalM should be set to 18'b0." line.long 0x1C "TOP_RCM_PLL_CORE_BWCTRL,Loop bandwidth control for Core PLL." bitfld.long 0x1C 1.--2. "PLL_CORE_BWCTRL_BWCONTROL,Change Loop Bandwidth" "0,1,2,3" newline bitfld.long 0x1C 0. "PLL_CORE_BWCTRL_BW_INCR_DECRZ,Direction of Loop Bandwidth0x0 : decrease BW0x1 : increase BW" "0,1" line.long 0x20 "TOP_RCM_PLL_CORE_FRACCTRL,Spread Specturm control for Core PLL - Not Supported." bitfld.long 0x20 31. "PLL_CORE_FRACCTRL_DOWNSPREAD,Controls frequency spread0x0 : enables both side frequency spread about the programmed frequency.0x1 : enables low frequency spread only" "?,1: enables low frequency spread only" newline bitfld.long 0x20 28.--30. "PLL_CORE_FRACCTRL_MODFREQDIVIDEREXPONENT,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 21.--27. 1. "PLL_CORE_FRACCTRL_MODFREQDIVIDERMANTISSA,Mantissa of the REFCLK divider to define the modulation frequency" newline bitfld.long 0x20 18.--20. "PLL_CORE_FRACCTRL_DELTAMSTEPINTEGER,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x20 0.--17. 1. "PLL_CORE_FRACCTRL_DELTAMSTEPFRACTION,The fraction part of Frequency Spread control" rgroup.long 0x424++0x3 line.long 0x0 "TOP_RCM_PLL_CORE_STATUS,Core PLL status regiser." bitfld.long 0x0 31. "PLL_CORE_STATUS_PONOUT,Status of the weak power-switch0x0 : indicates the/OFF status of the weak power-switch in digital toSOC.0x1 : ndicates the ON status of the weak power-switch in digital toSOC." "?,1: ndicates the ON status of the weak power-switch.." newline bitfld.long 0x0 30. "PLL_CORE_STATUS_PGOODOUT,Status of the strong power-switch0x0 : indicates the/OFF status of the strong power-switch in digital toSOC.0x1 : ndicates the ON status of the strong power-switch in digital toSOC." "?,1: ndicates the ON status of the strong.." newline bitfld.long 0x0 29. "PLL_CORE_STATUS_LDOPWDN,1'b1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT willbe un-defined in this condition" "0,1" newline bitfld.long 0x0 28. "PLL_CORE_STATUS_RECAL_BSTATUS3,Recalibration status flag. 1'b1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 27. "PLL_CORE_STATUS_RECAL_OPPIN,Recalibration status flag. 1'b1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 12. "PLL_CORE_STATUS_CLKOUTLDOENACK,Indicates the enable/disable condition of CLKOUTLDOEN0x0 = CLKOUTLDO gating completed0x1 = CLKOUTLDO enabling completed" "0,1" newline bitfld.long 0x0 11. "PLL_CORE_STATUS_CLKDCOLDOACK,Indicates the enable/disable condition of CLKDCOLDOEN0x0 = CLKDCOLDO gating completed0x1 = CLKDCOLOD enabling completed" "0,1" newline bitfld.long 0x0 10. "PLL_CORE_STATUS_PHASELOCK,Status on PHASELOCK output pin" "0,1" newline bitfld.long 0x0 9. "PLL_CORE_STATUS_FREQLOCK,Status on FREQLOCK output pin" "0,1" newline bitfld.long 0x0 8. "PLL_CORE_STATUS_BYPASSACK,Status of BYPASSACK output pin" "0,1" newline bitfld.long 0x0 7. "PLL_CORE_STATUS_STBYRETACK,Standby and retention status0x0: indicates to SOC that all internal clocks in ADPLLLJ are activeand it is starting the relock process.0x1: indicates to SOC that all internal clocks in ADPLLLJ are gatedand it is ready for.." "?,1: indicates to SOC that all internal clocks in.." newline bitfld.long 0x0 6. "PLL_CORE_STATUS_LOSSREF,Reference input loss is indicated by 1'b0." "0,1" newline bitfld.long 0x0 5. "PLL_CORE_STATUS_CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN0x0 = CLKOUT gating completed0x1 = CLKOUT enabling completed" "0,1" newline bitfld.long 0x0 4. "PLL_CORE_STATUS_LOCK2,ADPLL internal loop lock status" "0,1" newline bitfld.long 0x0 3. "PLL_CORE_STATUS_M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1[depending on current value] once CLKOUT frequency change hascompleted." "0,1" newline bitfld.long 0x0 2. "PLL_CORE_STATUS_SSCACK,Spread Spectrum status0x0 : Spread-spectrum Clocking is disabled on output clocks0x1 : Spread-spectrum Clocking is enabled on output clocks" "0,1" newline bitfld.long 0x0 1. "PLL_CORE_STATUS_HIGHJITTER,1'b1 indicates jitter. After PHASELOCK is asserted high theHIGHJITTER flag is asserted high if phase error between REFCLKand FBCLK greater than 24%." "0,1" newline bitfld.long 0x0 0. "PLL_CORE_STATUS_BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1" group.long 0x428++0x1B line.long 0x0 "TOP_RCM_PLL_CORE_HSDIVIDER,Core PLL high speed divider config." rbitfld.long 0x0 17. "PLL_CORE_HSDIVIDER_LDOPWDNACK,LDO Power Down Ack" "0,1" newline rbitfld.long 0x0 16. "PLL_CORE_HSDIVIDER_BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1" newline bitfld.long 0x0 2. "PLL_CORE_HSDIVIDER_TENABLEDIV,TENABLEDIV rising edge loads the values of M2REG and N2REG into ADPLLLJ register. TENABLEDIV could be activated anytime when the DPLL digital is in power-up condition. M2 and N2 latch [active rise edge]" "0,1" newline bitfld.long 0x0 1. "PLL_CORE_HSDIVIDER_LDOPWDN,1'b1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT willbe un-defined in this condition" "0,1" newline bitfld.long 0x0 0. "PLL_CORE_HSDIVIDER_BYPASS,HSDIVIDER Bypass. Set it to 1'b1 to bypass the HSDIVIDER." "0,1" line.long 0x4 "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0,Core PLL high speed divider clock 0 control." bitfld.long 0x4 12. "PLL_CORE_HSDIVIDER_CLKOUT0_PWDN,Power down for HSDIVIDER CLKOUT0 divider and hence CLKOUT0 output0h[R/W] = CLKOUT0 divider active1h[R/W] = CLKOUT0 divider is powered down" "0,1" newline rbitfld.long 0x4 9. "PLL_CORE_HSDIVIDER_CLKOUT0_STATUS,HSDIVIDER CLKOUT0 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0x4 8. "PLL_CORE_HSDIVIDER_CLKOUT0_GATE_CTRL,Control gating of HSDIVIDER CLKOUT00h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0x4 5. "PLL_CORE_HSDIVIDER_CLKOUT0_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "PLL_CORE_HSDIVIDER_CLKOUT0_DIV,DPLL post-divider factor HSDIVIDER CLKOUT0 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" line.long 0x8 "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT1,Core PLL high speed divider clock 1 control." bitfld.long 0x8 12. "PLL_CORE_HSDIVIDER_CLKOUT1_PWDN,Power down for HSDIVIDER CLKOUT1 divider and hence CLKOUT1 output0h[R/W] = CLKOUT1 divider active1h[R/W] = CLKOUT1 divider is powered down" "0,1" newline rbitfld.long 0x8 9. "PLL_CORE_HSDIVIDER_CLKOUT1_STATUS,HSDIVIDER CLKOUT1 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0x8 8. "PLL_CORE_HSDIVIDER_CLKOUT1_GATE_CTRL,Control gating of HSDIVIDER CLKOUT10h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0x8 5. "PLL_CORE_HSDIVIDER_CLKOUT1_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "PLL_CORE_HSDIVIDER_CLKOUT1_DIV,DPLL post-divider factor HSDIVIDER CLKOUT1 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" line.long 0xC "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT2,Core PLL high speed divider clock 2 control." bitfld.long 0xC 12. "PLL_CORE_HSDIVIDER_CLKOUT2_PWDN,Power down for HSDIVIDER CLKOUT2 divider and hence CLKOUT2 output0h[R/W] = CLKOUT2 divider active1h[R/W] = CLKOUT2 divider is powered down" "0,1" newline rbitfld.long 0xC 9. "PLL_CORE_HSDIVIDER_CLKOUT2_STATUS,HSDIVIDER CLKOUT2 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0xC 8. "PLL_CORE_HSDIVIDER_CLKOUT2_GATE_CTRL,Control gating of HSDIVIDER CLKOUT20h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0xC 5. "PLL_CORE_HSDIVIDER_CLKOUT2_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "PLL_CORE_HSDIVIDER_CLKOUT2_DIV,DPLL post-divider factor HSDIVIDER CLKOUT2 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" line.long 0x10 "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT3,Core PLL high speed divider clock 3 control." bitfld.long 0x10 12. "PLL_CORE_HSDIVIDER_CLKOUT3_PWDN,Power down for HSDIVIDER CLKOUT3 divider and hence CLKOUT3 output0h[R/W] = CLKOUT3 divider active1h[R/W] = CLKOUT3 divider is powered down" "0,1" newline rbitfld.long 0x10 9. "PLL_CORE_HSDIVIDER_CLKOUT3_STATUS,HSDIVIDER CLKOUT3 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0x10 8. "PLL_CORE_HSDIVIDER_CLKOUT3_GATE_CTRL,Control gating of HSDIVIDER CLKOUT30h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0x10 5. "PLL_CORE_HSDIVIDER_CLKOUT3_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "PLL_CORE_HSDIVIDER_CLKOUT3_DIV,DPLL post-divider factor HSDIVIDER CLKOUT3 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" line.long 0x14 "TOP_RCM_PLL_CORE_RSTCTRL,Core PLL reset control." bitfld.long 0x14 0.--2. "PLL_CORE_RSTCTRL_ASSERT,SW Reset override for the PLLWrite 3'b111 : Override is enabled and Reset is asserted" "0,1,2,3,4,5,6,7" line.long 0x18 "TOP_RCM_PLL_CORE_HSDIVIDER_RSTCTRL,Core PLL high speed divider reset control." bitfld.long 0x18 0.--2. "PLL_CORE_HSDIVIDER_RSTCTRL_ASSERT,SW Reset override for the HSDIVIDERWrite 3'b111 : Override is enabled and Reset is asserted" "0,1,2,3,4,5,6,7" group.long 0x500++0x3 line.long 0x0 "TOP_RCM_R5SS_CLK_SRC_SEL,Clock Source select register for MSS CortexR5 clock." hexmask.long.word 0x0 0.--11. 1. "R5SS_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for MSS Coretex R5 and System bus Clock.Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Use the.." rgroup.long 0x504++0x3 line.long 0x0 "TOP_RCM_R5SS_CLK_STATUS,Clock Status register for MSS Root clock for CortexR5 and SYS clock." hexmask.long.byte 0x0 0.--7. 1. "R5SS_CLK_STATUS_CLKINUSE,Status shows the source clock slected for Root clock for CortexR5 and Sysclk" group.long 0x510++0x17 line.long 0x0 "TOP_RCM_R5SS0_CLK_DIV_SEL,Clock Divider register for Respective R5SS clock ." bitfld.long 0x0 0.--2. "R5SS0_CLK_DIV_SEL_CLKSRCSEL,Writing 3'b000 Sets R5 clock = R5SS Root clockWriting 3'b111 Sets R5 Clock = SYSCLK" "0,1,2,3,4,5,6,7" line.long 0x4 "TOP_RCM_R5SS1_CLK_DIV_SEL,Clock Divider register for Respective R5SS clock ." bitfld.long 0x4 0.--2. "R5SS1_CLK_DIV_SEL_CLKSRCSEL,Writing 3'b000 Sets R5 clock = R5SS Root clockWriting 3'b111 Sets R5 Clock = SYSCLK" "0,1,2,3,4,5,6,7" line.long 0x8 "TOP_RCM_R5SS0_CLK_GATE,Clock Gating register for Respective R5SS clock." bitfld.long 0x8 0.--2. "R5SS0_CLK_GATE_GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5.Data should be loaded as multibit. Write 3'b000 : Clock is ungated [multibit 000]Write 3'b111 : Clock is gated [multibit 111]" "0,1,2,3,4,5,6,7" line.long 0xC "TOP_RCM_R5SS1_CLK_GATE,Clock Gating register for Respective R5SS clock." bitfld.long 0xC 0.--2. "R5SS1_CLK_GATE_GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5.Data should be loaded as multibit. Write 3'b000 : Clock is ungated [multibit 000]Write 3'b111 : Clock is gated [multibit 111]" "0,1,2,3,4,5,6,7" line.long 0x10 "TOP_RCM_SYS_CLK_DIV_VAL,Clock Divider register for System Clock." hexmask.long.word 0x10 0.--11. 1. "SYS_CLK_DIV_VAL_CLKDIV,Divider value for CLKOUT selected clock..To set the divider value of [n+1] configure the register to '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be configured.." line.long 0x14 "TOP_RCM_SYS_CLK_GATE,Clock Gating register for System Clock." bitfld.long 0x14 0.--2. "SYS_CLK_GATE_GATED,Only for debug- Functionality not guaranteed Clock gating config for System ClockData should be loaded as multibit. Write 3'b000 : Clock is ungated [multibit 000]Write 3'b111 : Clock is gated [multibit 111]" "0,1,2,3,4,5,6,7" rgroup.long 0x528++0x3 line.long 0x0 "TOP_RCM_SYS_CLK_STATUS,Clock Status register for System Clock." hexmask.long.byte 0x0 8.--15. 1. "SYS_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for Sys Clock" group.long 0x800++0x23 line.long 0x0 "TOP_RCM_PLL_PER_PWRCTRL,Power control for peripheral PLL." bitfld.long 0x0 5. "PLL_PER_PWRCTRL_PONIN,ON/OFF control of the weak power switch digital. For functionalmode it should be 1" "0,1" newline bitfld.long 0x0 4. "PLL_PER_PWRCTRL_PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1" "0,1" newline bitfld.long 0x0 3. "PLL_PER_PWRCTRL_RET,Save/Restore control for Retention mode. For functional mode itshould be 0" "0,1" newline bitfld.long 0x0 2. "PLL_PER_PWRCTRL_ISORET,Save/Restore control for Isolation of output pins For functional modeit should be 1'b0" "0,1" newline bitfld.long 0x0 1. "PLL_PER_PWRCTRL_ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functionalmode it should be 1'b0" "0,1" newline bitfld.long 0x0 0. "PLL_PER_PWRCTRL_OFFMODE,Used to switch OFF the logic on VDDA. For functional mode itshould be 0" "0,1" line.long 0x4 "TOP_RCM_PLL_PER_CLKCTRL,Clock control for Peripheral PLL." bitfld.long 0x4 31. "PLL_PER_CLKCTRL_CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK. Cycleslip could be caused if loop is not able to track input clock. Default = 1'b0 recommended" "0,1" newline bitfld.long 0x4 30. "PLL_PER_CLKCTRL_ENSSC,Controls Clock SpReading. SSC is not supported. Should be set to 0x0 to disable clock spReading." "0,1" newline bitfld.long 0x4 29. "PLL_PER_CLKCTRL_CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO0x0 : synchronously disables CLKDCOLDO0x1 : synchronously enables CLKDCOLDO" "0,1" newline bitfld.long 0x4 23. "PLL_PER_CLKCTRL_IDLE,Sets PLL to Idle mode0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go toActive and Locked0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go toIdle Bypass low powe" "0,1" newline bitfld.long 0x4 22. "PLL_PER_CLKCTRL_BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In generalthis input is expected to be tied to static low. For the output clocks ofthe module that do not have an internal bypass mux viz.CLKDCOLDO and CLKOUTLDO a bypass.." "0,1" newline bitfld.long 0x4 21. "PLL_PER_CLKCTRL_STBYRET,Standby retention control0x0 : prepares ADPLLLJ for relock when out of retention byremoving the gating on all internal clocks.0x1 : prepares ADPLLLJ for retention by gating all the internalclocks." "?,1: prepares ADPLLLJ for retention by gating all the.." newline bitfld.long 0x4 20. "PLL_PER_CLKCTRL_CLKOUTEN,CLKOUT enable or disable0x0 : synchronously disables CLKOUT0x1 : synchronously enables CLKOUT" "0,1" newline bitfld.long 0x4 19. "PLL_PER_CLKCTRL_CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO,1: synchronously enables CLKOUTLDO" newline bitfld.long 0x4 18. "PLL_PER_CLKCTRL_ULOWCLKEN,Select CLKOUT source in bypass0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/[N2+1]0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "0,1" newline bitfld.long 0x4 17. "PLL_PER_CLKCTRL_CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1" newline bitfld.long 0x4 16. "PLL_PER_CLKCTRL_M2PWDNZ,M2 divider power down mode0x0: Asynchronous power down for M2 divider0x1 : M2 divider is functional" "0,1" newline bitfld.long 0x4 14. "PLL_PER_CLKCTRL_STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode,1: Stopmode" newline bitfld.long 0x4 10.--12. "PLL_PER_CLKCTRL_SELFREQDCO,DCO Clock [DCOCLK = CLKINP * [M/[N+1]]] frequency rangeselector.0x0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz to1000MHz0x3: Reserved0x4: HS1: DCOCLK range is from1000MHz to2000MHz0x5: Reserved" "0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?" newline bitfld.long 0x4 8. "PLL_PER_CLKCTRL_RELAXED_LOCK,Decides when FREQLOCK asserted0x0: FREQLOCK asserted when DC frequency error less than 1%0x1: FREQLOCK asserted when DC frequency error less than 2%" "0,1" newline bitfld.long 0x4 1. "PLL_PER_CLKCTRL_SSCTYPE,SSC Type - This should be configured as 1'b0. The module supports spread spectrum clocking [SSC] on its output clocks." "0,1" newline bitfld.long 0x4 0. "PLL_PER_CLKCTRL_TINTZ,PLL core soft reset. TINITZ activation [Low] gives softreset to ADPLLLJ. TINITZ does not reset the entire digital control logic; it forces the FSM into RESET State so that ADPLLLJ could restart." "0,1" line.long 0x8 "TOP_RCM_PLL_PER_TENABLE,Trigger enable for Peripheral PLL." bitfld.long 0x8 0. "PLL_PER_TENABLE_TENABLE,Signal TENABLE loads REGM REGN REGSD and SELFREQDCO data. M N. SD and SELFREQDCO latch [active rise edge]" "0,1" line.long 0xC "TOP_RCM_PLL_PER_TENABLEDIV,Load Trigger for divider control value for peripheral PLL." bitfld.long 0xC 0. "PLL_PER_TENABLEDIV_TENABLEDIV,TENABLEDIV rising edge loads the values of M2REG and N2REG into ADPLLLJ register. TENABLEDIV could be activated anytime when the DPLL digital is in power-up condition. M2 and N2 latch [active rise edge]" "0,1" line.long 0x10 "TOP_RCM_PLL_PER_M2NDIV,M2N config register for peripheral PLL." hexmask.long.byte 0x10 16.--22. 1. "PLL_PER_M2NDIV_M2,Post-divider is REGM2" newline hexmask.long.byte 0x10 0.--7. 1. "PLL_PER_M2NDIV_N,Pre-divider is REGN+1" line.long 0x14 "TOP_RCM_PLL_PER_MN2DIV,MN2 config register for peripheral PLL." hexmask.long.byte 0x14 16.--19. 1. "PLL_PER_MN2DIV_N2,Bypass divider is REGN2+1" newline hexmask.long.word 0x14 0.--11. 1. "PLL_PER_MN2DIV_M,Feedback Multiplier is REGM" line.long 0x18 "TOP_RCM_PLL_PER_FRACDIV,Fractionsl divider and Sigma Delta config register for peripheral PLL." hexmask.long.byte 0x18 24.--31. 1. "PLL_PER_FRACDIV_REGSD,Sigma-Delta DividerShould be set by s/w to provide optimum jitter performance.DPLL_SD_DIV = CEILING [[DPLL_MULT/[DPLL_DIV+1]] * CLKINP/ 250] where CLKINP is the input clock of the DPLL in MHz" newline hexmask.long.tbyte 0x18 0.--17. 1. "PLL_PER_FRACDIV_FRACTIONALM,Fractional part of the M divider.The 18bit FractionalM value is loaded into DPLL on the rising edge of TENABLE signal .To enable Integer only division FractionalM should be set to 18'b0." line.long 0x1C "TOP_RCM_PLL_PER_BWCTRL,Loop bandwidth control for peripheral PLL." bitfld.long 0x1C 1.--2. "PLL_PER_BWCTRL_BWCONTROL,Change Loop Bandwidth" "0,1,2,3" newline bitfld.long 0x1C 0. "PLL_PER_BWCTRL_BW_INCR_DECRZ,Direction of Loop Bandwidth0x0 : decrease BW0x1 : increase BW" "0,1" line.long 0x20 "TOP_RCM_PLL_PER_FRACCTRL,Spread Specturm control for peripheral PLL - Not Supported." bitfld.long 0x20 31. "PLL_PER_FRACCTRL_DOWNSPREAD,Controls frequency spread0x0 : enables both side frequency spread about the programmed frequency.0x1 : enables low frequency spread only" "?,1: enables low frequency spread only" newline bitfld.long 0x20 28.--30. "PLL_PER_FRACCTRL_MODFREQDIVIDEREXPONENT,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 21.--27. 1. "PLL_PER_FRACCTRL_MODFREQDIVIDERMANTISSA,Mantissa of the REFCLK divider to define the modulation frequency" newline bitfld.long 0x20 18.--20. "PLL_PER_FRACCTRL_DELTAMSTEPINTEGER,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x20 0.--17. 1. "PLL_PER_FRACCTRL_DELTAMSTEPFRACTION,The fraction part of Frequency Spread control" rgroup.long 0x824++0x3 line.long 0x0 "TOP_RCM_PLL_PER_STATUS,Peripheral PLL status regiser." bitfld.long 0x0 31. "PLL_PER_STATUS_PONOUT,Status of the weak power-switch0x0 : indicates the/OFF status of the weak power-switch in digital toSOC.0x1 : ndicates the ON status of the weak power-switch in digital toSOC." "?,1: ndicates the ON status of the weak power-switch.." newline bitfld.long 0x0 30. "PLL_PER_STATUS_PGOODOUT,Status of the strong power-switch0x0 : indicates the/OFF status of the strong power-switch in digital toSOC.0x1 : ndicates the ON status of the strong power-switch in digital toSOC." "?,1: ndicates the ON status of the strong.." newline bitfld.long 0x0 29. "PLL_PER_STATUS_LDOPWDN,1'b1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT willbe un-defined in this condition" "0,1" newline bitfld.long 0x0 28. "PLL_PER_STATUS_RECAL_BSTATUS3,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 27. "PLL_PER_STATUS_RECAL_OPPIN,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 12. "PLL_PER_STATUS_CLKOUTLDOENACK,Indicates the enable/disable condition of CLKOUTLDOEN0x0 = CLKOUTLDO gating completed0x1 = CLKOUTLDO enabling completed" "0,1" newline bitfld.long 0x0 11. "PLL_PER_STATUS_CLKDCOLDOACK,Indicates the enable/disable condition of CLKDCOLDOEN0x0 = CLKDCOLDO gating completed0x1 = CLKDCOLDO enabling completed" "0,1" newline bitfld.long 0x0 10. "PLL_PER_STATUS_PHASELOCK,Status on PHASELOCK output pin" "0,1" newline bitfld.long 0x0 9. "PLL_PER_STATUS_FREQLOCK,Status on FREQLOCK output pin" "0,1" newline bitfld.long 0x0 8. "PLL_PER_STATUS_BYPASSACK,Status of BYPASSACK output pin" "0,1" newline bitfld.long 0x0 7. "PLL_PER_STATUS_STBYRETACK,Standby and retention status0x0: indicates to SOC that all internal clocks in ADPLLLJ are activeand it is starting the relock process.0x1: indicates to SOC that all internal clocks in ADPLLLJ are gatedand it is ready for.." "?,1: indicates to SOC that all internal clocks in.." newline bitfld.long 0x0 6. "PLL_PER_STATUS_LOSSREF,Reference input loss is indicated by 1'b0." "0,1" newline bitfld.long 0x0 5. "PLL_PER_STATUS_CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN0x0 = CLKOUT gating completed0x1 = CLKOUT enabling completed" "0,1" newline bitfld.long 0x0 4. "PLL_PER_STATUS_LOCK2,ADPLL internal loop lock status" "0,1" newline bitfld.long 0x0 3. "PLL_PER_STATUS_M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1[depending on current value] once CLKOUT frequency change hascompleted." "0,1" newline bitfld.long 0x0 2. "PLL_PER_STATUS_SSCACK,Spread Spectrum status0x0 : Spread-spectrum Clocking is disabled on output clocks0x1 : Spread-spectrum Clocking is enabled on output clocks" "0,1" newline bitfld.long 0x0 1. "PLL_PER_STATUS_HIGHJITTER,1'b1 indicates jitter. After PHASELOCK is asserted high theHIGHJITTER flag is asserted high if phase error between REFCLKand FBCLK greater than 24%." "0,1" newline bitfld.long 0x0 0. "PLL_PER_STATUS_BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1" group.long 0x828++0xF line.long 0x0 "TOP_RCM_PLL_PER_HSDIVIDER,Peripheral PLL high speed divider config." rbitfld.long 0x0 17. "PLL_PER_HSDIVIDER_LDOPWDNACK,LDO Power Down Ack" "0,1" newline rbitfld.long 0x0 16. "PLL_PER_HSDIVIDER_BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1" newline bitfld.long 0x0 2. "PLL_PER_HSDIVIDER_TENABLEDIV,TENABLEDIV rising edge loads the values of M2REG and N2REG into ADPLLLJ register. TENABLEDIV could be activated anytime when the DPLL digital is in power-up condition. M2 and N2 latch [active rise edge]" "0,1" newline bitfld.long 0x0 1. "PLL_PER_HSDIVIDER_LDOPWDN,1'b1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT willbe un-defined in this condition" "0,1" newline bitfld.long 0x0 0. "PLL_PER_HSDIVIDER_BYPASS,HSDIVIDER Bypass" "0,1" line.long 0x4 "TOP_RCM_PLL_PER_HSDIVIDER_CLKOUT0,Peripheral PLL high speed divider clock 0 control." bitfld.long 0x4 12. "PLL_PER_HSDIVIDER_CLKOUT0_PWDN,Power down for HSDIVIDER CLKOUT0 divider and hence CLKOUT0 output0h[R/W] = CLKOUT0 divider active1h[R/W] = CLKOUT0 divider is powered down" "0,1" newline rbitfld.long 0x4 9. "PLL_PER_HSDIVIDER_CLKOUT0_STATUS,HSDIVIDER CLKOUT0 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0x4 8. "PLL_PER_HSDIVIDER_CLKOUT0_GATE_CTRL,Control gating of HSDIVIDER CLKOUT00h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0x4 5. "PLL_PER_HSDIVIDER_CLKOUT0_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "PLL_PER_HSDIVIDER_CLKOUT0_DIV,DPLL post-divider factor HSDIVIDER CLKOUT0 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" line.long 0x8 "TOP_RCM_PLL_PER_HSDIVIDER_CLKOUT1,Peripheral PLL high speed divider clock 1 control." bitfld.long 0x8 12. "PLL_PER_HSDIVIDER_CLKOUT1_PWDN,Power down for HSDIVIDER CLKOUT1 divider and hence CLKOUT1 output0h[R/W] = CLKOUT1 divider active1h[R/W] = CLKOUT1 divider is powered down" "0,1" newline rbitfld.long 0x8 9. "PLL_PER_HSDIVIDER_CLKOUT1_STATUS,HSDIVIDER CLKOUT1 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0x8 8. "PLL_PER_HSDIVIDER_CLKOUT1_GATE_CTRL,Control gating of HSDIVIDER CLKOUT10h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0x8 5. "PLL_PER_HSDIVIDER_CLKOUT1_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "PLL_PER_HSDIVIDER_CLKOUT1_DIV,DPLL post-divider factor HSDIVIDER CLKOUT1 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" line.long 0xC "TOP_RCM_PLL_PER_HSDIVIDER_CLKOUT2,Peripheral PLL high speed divider clock 2 control." bitfld.long 0xC 12. "PLL_PER_HSDIVIDER_CLKOUT2_PWDN,Power down for HSDIVIDER CLKOUT2 divider and hence CLKOUT2 output0h[R/W] = CLKOUT2 divider active1h[R/W] = CLKOUT2 divider is powered down" "0,1" newline rbitfld.long 0xC 9. "PLL_PER_HSDIVIDER_CLKOUT2_STATUS,HSDIVIDER CLKOUT2 status0h[R] = The clock output is gated1h[R] = The clock output is enabled" "0,1" newline bitfld.long 0xC 8. "PLL_PER_HSDIVIDER_CLKOUT2_GATE_CTRL,Control gating of HSDIVIDER CLKOUT20h[R/W] = Automatically gate this clock when there is nodependency for it1h[R/W] = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.long 0xC 5. "PLL_PER_HSDIVIDER_CLKOUT2_DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "PLL_PER_HSDIVIDER_CLKOUT2_DIV,DPLL post-divider factor HSDIVIDER CLKOUT2 for internal clock generation.Divide values from 1 to 31.0h[R/W] = Reserved" group.long 0x83C++0x7 line.long 0x0 "TOP_RCM_PLL_PER_RSTCTRL,Peripheral PLL reset control." bitfld.long 0x0 0.--2. "PLL_PER_RSTCTRL_ASSERT,SW Reset override for the PLLWrite 3'b111 : Override is enabled and Reset is asserted" "0,1,2,3,4,5,6,7" line.long 0x4 "TOP_RCM_PLL_PER_HSDIVIDER_RSTCTRL,Peripheral PLL high speed divider reset control." bitfld.long 0x4 0.--2. "PLL_PER_HSDIVIDER_RSTCTRL_ASSERT,SW Reset override for the HSDIVIDERWrite 3'b111 : Override is enabled and Reset is asserted" "0,1,2,3,4,5,6,7" group.long 0xC00++0x17 line.long 0x0 "TOP_RCM_CLKOUT0_CLK_SRC_SEL,Clock Source select register for CLKOUT clock." hexmask.long.word 0x0 0.--11. 1. "CLKOUT0_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for MSS CLKOUT .Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Use the following values to.." line.long 0x4 "TOP_RCM_CLKOUT1_CLK_SRC_SEL,Clock Source select register for CLKOUT clock." hexmask.long.word 0x4 0.--11. 1. "CLKOUT1_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for MSS CLKOUT .Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Use the following values to.." line.long 0x8 "TOP_RCM_CLKOUT0_DIV_VAL,Clock Divider register for CLKOUT clock." hexmask.long.word 0x8 0.--11. 1. "CLKOUT0_DIV_VAL_CLKDIV,Divider value for CLKOUT selected clock..To set the divider value of [n+1] configure the register to '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be configured.." line.long 0xC "TOP_RCM_CLKOUT1_DIV_VAL,Clock Divider register for CLKOUT clock." hexmask.long.word 0xC 0.--11. 1. "CLKOUT1_DIV_VAL_CLKDIV,Divider value for CLKOUT selected clock..To set the divider value of [n+1] configure the register to '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be configured.." line.long 0x10 "TOP_RCM_CLKOUT0_CLK_GATE,Clock Gating register for CLKOUT clock." bitfld.long 0x10 0.--2. "CLKOUT0_CLK_GATE_GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS CLKOUTData should be loaded as multibit. Write 3'b000 : Clock is ungated [multibit 000]Write 3'b111 : Clock is gated [multibit 111]" "0,1,2,3,4,5,6,7" line.long 0x14 "TOP_RCM_CLKOUT1_CLK_GATE,Clock Gating register for CLKOUT clock." bitfld.long 0x14 0.--2. "CLKOUT1_CLK_GATE_GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS CLKOUTData should be loaded as multibit. Write 3'b000 : Clock is ungated [multibit 000]Write 3'b111 : Clock is gated [multibit 111]" "0,1,2,3,4,5,6,7" rgroup.long 0xC18++0x7 line.long 0x0 "TOP_RCM_CLKOUT0_CLK_STATUS,Clock Status register for CLKOUT clock." hexmask.long.byte 0x0 8.--15. 1. "CLKOUT0_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for CLKOUT Clock" newline hexmask.long.byte 0x0 0.--7. 1. "CLKOUT0_CLK_STATUS_CLKINUSE,Status shows the source clock slected for CLKOUT Clock" line.long 0x4 "TOP_RCM_CLKOUT1_CLK_STATUS,Clock Status register for CLKOUT clock." hexmask.long.byte 0x4 8.--15. 1. "CLKOUT1_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for CLKOUT Clock" newline hexmask.long.byte 0x4 0.--7. 1. "CLKOUT1_CLK_STATUS_CLKINUSE,Status shows the source clock slected for CLKOUT Clock" group.long 0xC20++0xB line.long 0x0 "TOP_RCM_TRCCLKOUT_CLK_SRC_SEL,Clock Source select register for TRC clkout." hexmask.long.word 0x0 0.--11. 1. "TRCCLKOUT_CLK_SRC_SEL_CLKSRCSEL,Select line for selecting source clock for TRC ClkoutData should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Use the following values to.." line.long 0x4 "TOP_RCM_TRCCLKOUT_DIV_VAL,Clock Divider register for TRC clkout." hexmask.long.word 0x4 0.--11. 1. "TRCCLKOUT_DIV_VAL_CLKDIV,Divider value for CLKOUT selected clock..To set the divider value of [n+1] configure the register to '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be.." line.long 0x8 "TOP_RCM_TRCCLKOUT_CLK_GATE,Clock Gating register for TRC clkout." bitfld.long 0x8 0.--2. "TRCCLKOUT_CLK_GATE_GATED,Clock gatring config for TRC ClkoutData should be loaded as multibit. Write 3'b000 : Clock is ungated [multibit 000]Write 3'b111 : Clock is gated [multibit 111]" "0,1,2,3,4,5,6,7" rgroup.long 0xC2C++0x3 line.long 0x0 "TOP_RCM_TRCCLKOUT_CLK_STATUS,Clock Status register for TRC clkout." hexmask.long.byte 0x0 8.--15. 1. "TRCCLKOUT_CLK_STATUS_CURRDIVIDER,Status shows the current divider value choosen for PMIC Clkout Clock" newline hexmask.long.byte 0x0 0.--7. 1. "TRCCLKOUT_CLK_STATUS_CLKINUSE,Status shows the source clock slected for PMIC Clkout Clock" group.long 0x1008++0x1B line.long 0x0 "TOP_RCM_LOCK0_KICK0,- KICK0 component." hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "TOP_RCM_LOCK0_KICK1,- KICK1 component." hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "TOP_RCM_INTR_RAW_STATUS,Interrupt Raw Status/Set Register." bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "TOP_RCM_INTR_ENABLED_STATUS_CLEAR,Interrupt Enabled Status/Clear register." bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "TOP_RCM_INTR_ENABLE,Interrupt Enable register." bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "TOP_RCM_INTR_ENABLE_CLEAR,Interrupt Enable Clear register." bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "TOP_RCM_EOI,EOI register." hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "TOP_RCM_FAULT_ADDRESS,Fault Address register." hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "TOP_RCM_FAULT_TYPE_STATUS,Fault Type Status register." bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." line.long 0x8 "TOP_RCM_FAULT_ATTR_STATUS,Fault Attribute Status register." hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "TOP_RCM_FAULT_CLEAR,Fault Clear register." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree.end tree "UART" base ad:0x0 tree "UART0" base ad:0x52300000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,Divisor Latches Low Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.long 0x4++0x3 line.long 0x0 "UART_DLH,Divisor Latches High Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Disables the receive stop interrupt.1 Enables the receive stop interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT,0 Disables the received EOF interrupt.1 Enables the received EOF interrupt." "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Disables the receiver line status interrupt.1 Enables the receiver line status interrupt." "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT,0 Disables the status FIFO trigger level interrupt.1 Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT,0 Disables the last byte of frame in RX FIFO interrupt.1 Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT,0 Disables the CTS* interrupt1 Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,0 Disables the RTS* interrupt1 Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,0 Disables the XOFF interrupt1 Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,0 Disables sleep mode1 Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,0 Disables the modem status register interrupt1 Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,0 Disables the receiver line status interrupt1 Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt1 Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt and time out interrupt.1 Enables the RHR interrupt and time out interrupt." "0,1" line.long 0x4 "UART_EFR,Enhanced Feature Register." bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit.0:Normal operation.1:Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit.0:Normal operation.1:Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE transmission.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation.1:Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit.0:Disables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7.1:Enables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables Writing to IER bits 4-7,1: Enables Writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" wgroup.long 0x8++0x3 line.long 0x0 "UART_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.." bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] =0000br#00: 8 charactersbr#01:16 charactersbr#10:56 charactersbr#11:60 charactersIf SCR[7] = 0 and TLR[7:4] !=0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] =0000br#00: 8 spacesbr#01:16 spacesbr#10:32 spacesbr#11:56 spacesIf SCR[6] = 0 and TLR[3:0] !=0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,0 No change1 Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,0 No change1 Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs.1 : Enables the transmit and receive FIFOs.The transmit and receive holding registers are 64-bytes FIFOs." "?,1: Enables the transmit and receive FIFOs" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Receive stop interrupt inactive1 Receive stop interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT,0 Received EOF interrupt inactive1 Received EOF interrupt active" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Receiver line status interrupt inactive1 Receiver line status interrupt active" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT,0 Status FIFO trigger level interrupt inactive1 Status FIFO trigger level interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT,0 Last byte of frame in RX FIFO interrupt inactive1 Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,0 Modem Interrupt. Priority=41 THR interrupt. Priority=32 RHR interrupt. Priority=23 Receiver line status error. Priority=36 Rx timeout. Priority=28 Xoff/Special character. Priority=516 CTS RTS DSR change.." newline bitfld.long 0x0 0. "IT_PENDING,0 An interrupt is pending1 No interrupt is pending" "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1." bitfld.long 0x0 7. "DIV_EN,0 Normal operating condition1 Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 Normal operating condition.1 Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,0 Odd parity is generated (if LCR[3] = 1)1 Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,0 No parity1 A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 1 stop bits (word length = 5 6 7 8)1 1.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1,2,3" line.long 0x4 "UART_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0 No action1 Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x4 5. "XON_EN,0 Disable 'XON any' function1 Enable 'XON any' function" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0 Normal operating mode1 Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the receive input internally" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH,0 In loopback forces DCD* input high and IRQ outputs to inactive state.1 In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0 In loopback forces RI* input high.1 In loopback forces RI* input low." "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 Force RTS* output to inactive (high).1 Force RTS* output to active (low)." "0,1" newline bitfld.long 0x4 0. "DTR,0 Force DTR* output to inactive (high).1 Force DTR* output to active (low)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,XON1/ADDR1 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,IR CIR mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 0 Reception is on going or waiting for a new frame1 Reception is completed" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,IR-IRDA mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,0 Status FIFO not full1 Status FIFO full" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE,0 The RX FIFO (RHR) does not contain the last byte of the frame to be read1 The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only set when the last byte of a frame is available to.." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,0 No frame-too-long error in frame1 Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH.." "0,1" newline bitfld.long 0x0 3. "ABORT,0 No abort pattern error in frame1 Abort pattern is received. SIR & MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.long 0x0 2. "CRC,0 No CRC error in frame1 CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E,0 Status FIFO not empty1 Status FIFO empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART" bitfld.long 0x0 7. "RX_FIFO_STS,0 Normal operation1 At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,0 Transmitter hold (TX FIFO) and shift registers are not empty.1 Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,0 Transmit hold register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,0 No break condition1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,0 No framing error in data being read from RX FIFO.1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,0 No parity error in data being read from RX FIFO.1 Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,0 No overrun error1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Line Status Register 0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,XON2/ADDR2 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,1 Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,1 Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission Control Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,XOFF1 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "UART_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger Level Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,XOFF2 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "UART_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 Frame-length method1 Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 Manual SIP mode: SIP is generated with the control of ACREG[3]1 Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 Starts the Infrared transmission as soon as a value is written to THR1 Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any transmission there must.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=11 TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,0 IrDA/CIR sleep mode disabled1 IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0 UART 16x mode1 SIR mode2 UART 16x auto-baud3 UART 13x mode4 MIR mode5 FIR mode6 CIR mode7 Disable (default state)" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the.." bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode1 Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not effect the RX path in UART Modem modes. 0 inversion is performed1 No inversion is performed" "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles1 Pulse width of 4 from 12 cycles2 Pulse width of 5 from 12 cycles3 Pulse width of 6.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode1 UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0 1 entry1 4 entries2 7 entries3 8 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : 0 the last bit of the frame has been transmitted successfully without error.1 an underrun has occurred. The last bit of.." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read.." bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,1 Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,1 Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,1 Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "UART_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x3 line.long 0x0 "UART_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" wgroup.long 0x30++0x3 line.long 0x0 "UART_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode. If only one start flag is required. this will always be 0xC0. If n start flags are.." bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 0xFF1 0xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART Autobauding Status Register." bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 =>9600bauds. 01000 =>4800bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "UART_ACREG,IR-IrDA and IR-CIR modes only." bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select: 0 3/16 of baud-rate pulse width1 1.6us" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high1 SD pin is set to low" "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX,0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).1 Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 Long stop bits cannot be transmitted TX.." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action1.." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "UART_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." bitfld.long 0x4 7. "RX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.1 Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x4 5. "DSR_IT,0 DISABLES DSR* INTERRUPT.1 ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].1 Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0 Normal mode for THR interrupt (See UART mode interrupts table).1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)1 DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)2 DMA mode 2 (UART_nDMA_REQ[0] in RX)3 DMA mode 3 (UART_nDMA_REQ[0] in TX)" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL,0 The DMA_MODE is set with FCR[3]1 The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0x8 "UART_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0 The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2])1 The DMA counter will be reset if corresponding FIFO is reset (via FCR[1] or FCR[2])" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,0 No falling edge event on RX CTS* and DSR*1 A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,0 TX FIFO is not full1 TX FIFO is full." "0,1" line.long 0xC "UART_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must take into account the BOF character. therefore to only sent one BOF with no XBOF this.." hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returnedNotes: UART / IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART / IRDA with SIR. MIR and FIR.." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged unconditionally1 No-idle. An idle request is never acknowledged.2 Smart idle. Acknowledgement to an.." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 Wake up is disabled1 Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode1 The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 Clock is running1 Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal Module Reset is ongoing1 Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to.." bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0 Event is not allowed to wake up the system1 EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" line.long 0x4 "UART_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual.." rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO." hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO." hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0 Enables the RHR interrupt.1 Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 TXFIFO_EMPTY interrupt not pending.1 TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 RXFIFO_EMPTY interrupt not pending.1 RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit value selector." hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused." hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused." hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3." bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation1 Disables CIR RX demodulation" "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0 disabled (no override)1 reserved2 Synchronous mode with external clock3 Synchronous mode with generated clock4 ISO 7816 mode T=05 ISO 7816 mode T=16 reserved7.." "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 timeout after at least one character has been received1 periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO7816C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO7816C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO7816reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)1 data in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 Little Endian (LSB First)1 Big Endian (MSB First)" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 Transmitter is shut down1 Transmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 Receiver is shut down1 Receiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows Writing the full 9bit RHR" line.long 0x4 "UART_MAR,Multidrop Address Register." hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register." hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? Writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register." hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART1" base ad:0x52301000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,Divisor Latches Low Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.long 0x4++0x3 line.long 0x0 "UART_DLH,Divisor Latches High Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Disables the receive stop interrupt.1 Enables the receive stop interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT,0 Disables the received EOF interrupt.1 Enables the received EOF interrupt." "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Disables the receiver line status interrupt.1 Enables the receiver line status interrupt." "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT,0 Disables the status FIFO trigger level interrupt.1 Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT,0 Disables the last byte of frame in RX FIFO interrupt.1 Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT,0 Disables the CTS* interrupt1 Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,0 Disables the RTS* interrupt1 Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,0 Disables the XOFF interrupt1 Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,0 Disables sleep mode1 Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,0 Disables the modem status register interrupt1 Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,0 Disables the receiver line status interrupt1 Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt1 Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt and time out interrupt.1 Enables the RHR interrupt and time out interrupt." "0,1" line.long 0x4 "UART_EFR,Enhanced Feature Register." bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit.0:Normal operation.1:Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit.0:Normal operation.1:Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE transmission.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation.1:Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit.0:Disables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7.1:Enables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables Writing to IER bits 4-7,1: Enables Writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" wgroup.long 0x8++0x3 line.long 0x0 "UART_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.." bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] =0000br#00: 8 charactersbr#01:16 charactersbr#10:56 charactersbr#11:60 charactersIf SCR[7] = 0 and TLR[7:4] !=0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] =0000br#00: 8 spacesbr#01:16 spacesbr#10:32 spacesbr#11:56 spacesIf SCR[6] = 0 and TLR[3:0] !=0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,0 No change1 Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,0 No change1 Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs.1 : Enables the transmit and receive FIFOs.The transmit and receive holding registers are 64-bytes FIFOs." "?,1: Enables the transmit and receive FIFOs" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Receive stop interrupt inactive1 Receive stop interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT,0 Received EOF interrupt inactive1 Received EOF interrupt active" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Receiver line status interrupt inactive1 Receiver line status interrupt active" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT,0 Status FIFO trigger level interrupt inactive1 Status FIFO trigger level interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT,0 Last byte of frame in RX FIFO interrupt inactive1 Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,0 Modem Interrupt. Priority=41 THR interrupt. Priority=32 RHR interrupt. Priority=23 Receiver line status error. Priority=36 Rx timeout. Priority=28 Xoff/Special character. Priority=516 CTS RTS DSR change.." newline bitfld.long 0x0 0. "IT_PENDING,0 An interrupt is pending1 No interrupt is pending" "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1." bitfld.long 0x0 7. "DIV_EN,0 Normal operating condition1 Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 Normal operating condition.1 Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,0 Odd parity is generated (if LCR[3] = 1)1 Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,0 No parity1 A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 1 stop bits (word length = 5 6 7 8)1 1.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1,2,3" line.long 0x4 "UART_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0 No action1 Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x4 5. "XON_EN,0 Disable 'XON any' function1 Enable 'XON any' function" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0 Normal operating mode1 Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the receive input internally" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH,0 In loopback forces DCD* input high and IRQ outputs to inactive state.1 In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0 In loopback forces RI* input high.1 In loopback forces RI* input low." "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 Force RTS* output to inactive (high).1 Force RTS* output to active (low)." "0,1" newline bitfld.long 0x4 0. "DTR,0 Force DTR* output to inactive (high).1 Force DTR* output to active (low)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,XON1/ADDR1 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,IR CIR mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 0 Reception is on going or waiting for a new frame1 Reception is completed" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,IR-IRDA mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,0 Status FIFO not full1 Status FIFO full" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE,0 The RX FIFO (RHR) does not contain the last byte of the frame to be read1 The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only set when the last byte of a frame is available to.." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,0 No frame-too-long error in frame1 Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH.." "0,1" newline bitfld.long 0x0 3. "ABORT,0 No abort pattern error in frame1 Abort pattern is received. SIR & MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.long 0x0 2. "CRC,0 No CRC error in frame1 CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E,0 Status FIFO not empty1 Status FIFO empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART" bitfld.long 0x0 7. "RX_FIFO_STS,0 Normal operation1 At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,0 Transmitter hold (TX FIFO) and shift registers are not empty.1 Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,0 Transmit hold register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,0 No break condition1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,0 No framing error in data being read from RX FIFO.1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,0 No parity error in data being read from RX FIFO.1 Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,0 No overrun error1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Line Status Register 0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,XON2/ADDR2 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,1 Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,1 Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission Control Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,XOFF1 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "UART_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger Level Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,XOFF2 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "UART_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 Frame-length method1 Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 Manual SIP mode: SIP is generated with the control of ACREG[3]1 Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 Starts the Infrared transmission as soon as a value is written to THR1 Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any transmission there must.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=11 TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,0 IrDA/CIR sleep mode disabled1 IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0 UART 16x mode1 SIR mode2 UART 16x auto-baud3 UART 13x mode4 MIR mode5 FIR mode6 CIR mode7 Disable (default state)" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the.." bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode1 Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not effect the RX path in UART Modem modes. 0 inversion is performed1 No inversion is performed" "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles1 Pulse width of 4 from 12 cycles2 Pulse width of 5 from 12 cycles3 Pulse width of 6.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode1 UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0 1 entry1 4 entries2 7 entries3 8 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : 0 the last bit of the frame has been transmitted successfully without error.1 an underrun has occurred. The last bit of.." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read.." bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,1 Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,1 Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,1 Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "UART_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x3 line.long 0x0 "UART_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" wgroup.long 0x30++0x3 line.long 0x0 "UART_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode. If only one start flag is required. this will always be 0xC0. If n start flags are.." bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 0xFF1 0xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART Autobauding Status Register." bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 =>9600bauds. 01000 =>4800bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "UART_ACREG,IR-IrDA and IR-CIR modes only." bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select: 0 3/16 of baud-rate pulse width1 1.6us" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high1 SD pin is set to low" "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX,0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).1 Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 Long stop bits cannot be transmitted TX.." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action1.." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "UART_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." bitfld.long 0x4 7. "RX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.1 Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x4 5. "DSR_IT,0 DISABLES DSR* INTERRUPT.1 ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].1 Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0 Normal mode for THR interrupt (See UART mode interrupts table).1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)1 DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)2 DMA mode 2 (UART_nDMA_REQ[0] in RX)3 DMA mode 3 (UART_nDMA_REQ[0] in TX)" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL,0 The DMA_MODE is set with FCR[3]1 The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0x8 "UART_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0 The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2])1 The DMA counter will be reset if corresponding FIFO is reset (via FCR[1] or FCR[2])" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,0 No falling edge event on RX CTS* and DSR*1 A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,0 TX FIFO is not full1 TX FIFO is full." "0,1" line.long 0xC "UART_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must take into account the BOF character. therefore to only sent one BOF with no XBOF this.." hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returnedNotes: UART / IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART / IRDA with SIR. MIR and FIR.." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged unconditionally1 No-idle. An idle request is never acknowledged.2 Smart idle. Acknowledgement to an.." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 Wake up is disabled1 Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode1 The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 Clock is running1 Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal Module Reset is ongoing1 Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to.." bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0 Event is not allowed to wake up the system1 EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" line.long 0x4 "UART_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual.." rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO." hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO." hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0 Enables the RHR interrupt.1 Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 TXFIFO_EMPTY interrupt not pending.1 TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 RXFIFO_EMPTY interrupt not pending.1 RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit value selector." hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused." hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused." hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3." bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation1 Disables CIR RX demodulation" "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0 disabled (no override)1 reserved2 Synchronous mode with external clock3 Synchronous mode with generated clock4 ISO 7816 mode T=05 ISO 7816 mode T=16 reserved7.." "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 timeout after at least one character has been received1 periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO7816C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO7816C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO7816reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)1 data in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 Little Endian (LSB First)1 Big Endian (MSB First)" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 Transmitter is shut down1 Transmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 Receiver is shut down1 Receiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows Writing the full 9bit RHR" line.long 0x4 "UART_MAR,Multidrop Address Register." hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register." hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? Writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register." hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART2" base ad:0x52302000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,Divisor Latches Low Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.long 0x4++0x3 line.long 0x0 "UART_DLH,Divisor Latches High Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Disables the receive stop interrupt.1 Enables the receive stop interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT,0 Disables the received EOF interrupt.1 Enables the received EOF interrupt." "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Disables the receiver line status interrupt.1 Enables the receiver line status interrupt." "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT,0 Disables the status FIFO trigger level interrupt.1 Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT,0 Disables the last byte of frame in RX FIFO interrupt.1 Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT,0 Disables the CTS* interrupt1 Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,0 Disables the RTS* interrupt1 Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,0 Disables the XOFF interrupt1 Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,0 Disables sleep mode1 Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,0 Disables the modem status register interrupt1 Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,0 Disables the receiver line status interrupt1 Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt1 Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt and time out interrupt.1 Enables the RHR interrupt and time out interrupt." "0,1" line.long 0x4 "UART_EFR,Enhanced Feature Register." bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit.0:Normal operation.1:Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit.0:Normal operation.1:Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE transmission.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation.1:Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit.0:Disables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7.1:Enables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables Writing to IER bits 4-7,1: Enables Writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" wgroup.long 0x8++0x3 line.long 0x0 "UART_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.." bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] =0000br#00: 8 charactersbr#01:16 charactersbr#10:56 charactersbr#11:60 charactersIf SCR[7] = 0 and TLR[7:4] !=0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] =0000br#00: 8 spacesbr#01:16 spacesbr#10:32 spacesbr#11:56 spacesIf SCR[6] = 0 and TLR[3:0] !=0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,0 No change1 Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,0 No change1 Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs.1 : Enables the transmit and receive FIFOs.The transmit and receive holding registers are 64-bytes FIFOs." "?,1: Enables the transmit and receive FIFOs" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Receive stop interrupt inactive1 Receive stop interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT,0 Received EOF interrupt inactive1 Received EOF interrupt active" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Receiver line status interrupt inactive1 Receiver line status interrupt active" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT,0 Status FIFO trigger level interrupt inactive1 Status FIFO trigger level interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT,0 Last byte of frame in RX FIFO interrupt inactive1 Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,0 Modem Interrupt. Priority=41 THR interrupt. Priority=32 RHR interrupt. Priority=23 Receiver line status error. Priority=36 Rx timeout. Priority=28 Xoff/Special character. Priority=516 CTS RTS DSR change.." newline bitfld.long 0x0 0. "IT_PENDING,0 An interrupt is pending1 No interrupt is pending" "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1." bitfld.long 0x0 7. "DIV_EN,0 Normal operating condition1 Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 Normal operating condition.1 Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,0 Odd parity is generated (if LCR[3] = 1)1 Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,0 No parity1 A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 1 stop bits (word length = 5 6 7 8)1 1.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1,2,3" line.long 0x4 "UART_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0 No action1 Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x4 5. "XON_EN,0 Disable 'XON any' function1 Enable 'XON any' function" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0 Normal operating mode1 Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the receive input internally" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH,0 In loopback forces DCD* input high and IRQ outputs to inactive state.1 In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0 In loopback forces RI* input high.1 In loopback forces RI* input low." "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 Force RTS* output to inactive (high).1 Force RTS* output to active (low)." "0,1" newline bitfld.long 0x4 0. "DTR,0 Force DTR* output to inactive (high).1 Force DTR* output to active (low)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,XON1/ADDR1 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,IR CIR mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 0 Reception is on going or waiting for a new frame1 Reception is completed" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,IR-IRDA mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,0 Status FIFO not full1 Status FIFO full" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE,0 The RX FIFO (RHR) does not contain the last byte of the frame to be read1 The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only set when the last byte of a frame is available to.." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,0 No frame-too-long error in frame1 Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH.." "0,1" newline bitfld.long 0x0 3. "ABORT,0 No abort pattern error in frame1 Abort pattern is received. SIR & MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.long 0x0 2. "CRC,0 No CRC error in frame1 CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E,0 Status FIFO not empty1 Status FIFO empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART" bitfld.long 0x0 7. "RX_FIFO_STS,0 Normal operation1 At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,0 Transmitter hold (TX FIFO) and shift registers are not empty.1 Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,0 Transmit hold register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,0 No break condition1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,0 No framing error in data being read from RX FIFO.1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,0 No parity error in data being read from RX FIFO.1 Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,0 No overrun error1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Line Status Register 0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,XON2/ADDR2 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,1 Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,1 Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission Control Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,XOFF1 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "UART_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger Level Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,XOFF2 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "UART_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 Frame-length method1 Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 Manual SIP mode: SIP is generated with the control of ACREG[3]1 Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 Starts the Infrared transmission as soon as a value is written to THR1 Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any transmission there must.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=11 TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,0 IrDA/CIR sleep mode disabled1 IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0 UART 16x mode1 SIR mode2 UART 16x auto-baud3 UART 13x mode4 MIR mode5 FIR mode6 CIR mode7 Disable (default state)" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the.." bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode1 Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not effect the RX path in UART Modem modes. 0 inversion is performed1 No inversion is performed" "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles1 Pulse width of 4 from 12 cycles2 Pulse width of 5 from 12 cycles3 Pulse width of 6.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode1 UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0 1 entry1 4 entries2 7 entries3 8 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : 0 the last bit of the frame has been transmitted successfully without error.1 an underrun has occurred. The last bit of.." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read.." bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,1 Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,1 Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,1 Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "UART_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x3 line.long 0x0 "UART_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" wgroup.long 0x30++0x3 line.long 0x0 "UART_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode. If only one start flag is required. this will always be 0xC0. If n start flags are.." bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 0xFF1 0xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART Autobauding Status Register." bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 =>9600bauds. 01000 =>4800bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "UART_ACREG,IR-IrDA and IR-CIR modes only." bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select: 0 3/16 of baud-rate pulse width1 1.6us" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high1 SD pin is set to low" "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX,0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).1 Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 Long stop bits cannot be transmitted TX.." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action1.." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "UART_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." bitfld.long 0x4 7. "RX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.1 Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x4 5. "DSR_IT,0 DISABLES DSR* INTERRUPT.1 ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].1 Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0 Normal mode for THR interrupt (See UART mode interrupts table).1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)1 DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)2 DMA mode 2 (UART_nDMA_REQ[0] in RX)3 DMA mode 3 (UART_nDMA_REQ[0] in TX)" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL,0 The DMA_MODE is set with FCR[3]1 The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0x8 "UART_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0 The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2])1 The DMA counter will be reset if corresponding FIFO is reset (via FCR[1] or FCR[2])" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,0 No falling edge event on RX CTS* and DSR*1 A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,0 TX FIFO is not full1 TX FIFO is full." "0,1" line.long 0xC "UART_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must take into account the BOF character. therefore to only sent one BOF with no XBOF this.." hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returnedNotes: UART / IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART / IRDA with SIR. MIR and FIR.." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged unconditionally1 No-idle. An idle request is never acknowledged.2 Smart idle. Acknowledgement to an.." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 Wake up is disabled1 Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode1 The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 Clock is running1 Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal Module Reset is ongoing1 Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to.." bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0 Event is not allowed to wake up the system1 EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" line.long 0x4 "UART_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual.." rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO." hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO." hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0 Enables the RHR interrupt.1 Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 TXFIFO_EMPTY interrupt not pending.1 TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 RXFIFO_EMPTY interrupt not pending.1 RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit value selector." hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused." hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused." hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3." bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation1 Disables CIR RX demodulation" "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0 disabled (no override)1 reserved2 Synchronous mode with external clock3 Synchronous mode with generated clock4 ISO 7816 mode T=05 ISO 7816 mode T=16 reserved7.." "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 timeout after at least one character has been received1 periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO7816C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO7816C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO7816reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)1 data in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 Little Endian (LSB First)1 Big Endian (MSB First)" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 Transmitter is shut down1 Transmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 Receiver is shut down1 Receiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows Writing the full 9bit RHR" line.long 0x4 "UART_MAR,Multidrop Address Register." hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register." hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? Writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register." hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART3" base ad:0x52303000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,Divisor Latches Low Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.long 0x4++0x3 line.long 0x0 "UART_DLH,Divisor Latches High Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Disables the receive stop interrupt.1 Enables the receive stop interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT,0 Disables the received EOF interrupt.1 Enables the received EOF interrupt." "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Disables the receiver line status interrupt.1 Enables the receiver line status interrupt." "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT,0 Disables the status FIFO trigger level interrupt.1 Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT,0 Disables the last byte of frame in RX FIFO interrupt.1 Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT,0 Disables the CTS* interrupt1 Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,0 Disables the RTS* interrupt1 Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,0 Disables the XOFF interrupt1 Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,0 Disables sleep mode1 Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,0 Disables the modem status register interrupt1 Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,0 Disables the receiver line status interrupt1 Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt1 Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt and time out interrupt.1 Enables the RHR interrupt and time out interrupt." "0,1" line.long 0x4 "UART_EFR,Enhanced Feature Register." bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit.0:Normal operation.1:Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit.0:Normal operation.1:Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE transmission.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation.1:Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit.0:Disables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7.1:Enables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables Writing to IER bits 4-7,1: Enables Writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" wgroup.long 0x8++0x3 line.long 0x0 "UART_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.." bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] =0000br#00: 8 charactersbr#01:16 charactersbr#10:56 charactersbr#11:60 charactersIf SCR[7] = 0 and TLR[7:4] !=0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] =0000br#00: 8 spacesbr#01:16 spacesbr#10:32 spacesbr#11:56 spacesIf SCR[6] = 0 and TLR[3:0] !=0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,0 No change1 Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,0 No change1 Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs.1 : Enables the transmit and receive FIFOs.The transmit and receive holding registers are 64-bytes FIFOs." "?,1: Enables the transmit and receive FIFOs" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Receive stop interrupt inactive1 Receive stop interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT,0 Received EOF interrupt inactive1 Received EOF interrupt active" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Receiver line status interrupt inactive1 Receiver line status interrupt active" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT,0 Status FIFO trigger level interrupt inactive1 Status FIFO trigger level interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT,0 Last byte of frame in RX FIFO interrupt inactive1 Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,0 Modem Interrupt. Priority=41 THR interrupt. Priority=32 RHR interrupt. Priority=23 Receiver line status error. Priority=36 Rx timeout. Priority=28 Xoff/Special character. Priority=516 CTS RTS DSR change.." newline bitfld.long 0x0 0. "IT_PENDING,0 An interrupt is pending1 No interrupt is pending" "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1." bitfld.long 0x0 7. "DIV_EN,0 Normal operating condition1 Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 Normal operating condition.1 Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,0 Odd parity is generated (if LCR[3] = 1)1 Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,0 No parity1 A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 1 stop bits (word length = 5 6 7 8)1 1.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1,2,3" line.long 0x4 "UART_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0 No action1 Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x4 5. "XON_EN,0 Disable 'XON any' function1 Enable 'XON any' function" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0 Normal operating mode1 Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the receive input internally" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH,0 In loopback forces DCD* input high and IRQ outputs to inactive state.1 In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0 In loopback forces RI* input high.1 In loopback forces RI* input low." "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 Force RTS* output to inactive (high).1 Force RTS* output to active (low)." "0,1" newline bitfld.long 0x4 0. "DTR,0 Force DTR* output to inactive (high).1 Force DTR* output to active (low)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,XON1/ADDR1 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,IR CIR mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 0 Reception is on going or waiting for a new frame1 Reception is completed" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,IR-IRDA mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,0 Status FIFO not full1 Status FIFO full" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE,0 The RX FIFO (RHR) does not contain the last byte of the frame to be read1 The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only set when the last byte of a frame is available to.." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,0 No frame-too-long error in frame1 Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH.." "0,1" newline bitfld.long 0x0 3. "ABORT,0 No abort pattern error in frame1 Abort pattern is received. SIR & MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.long 0x0 2. "CRC,0 No CRC error in frame1 CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E,0 Status FIFO not empty1 Status FIFO empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART" bitfld.long 0x0 7. "RX_FIFO_STS,0 Normal operation1 At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,0 Transmitter hold (TX FIFO) and shift registers are not empty.1 Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,0 Transmit hold register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,0 No break condition1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,0 No framing error in data being read from RX FIFO.1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,0 No parity error in data being read from RX FIFO.1 Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,0 No overrun error1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Line Status Register 0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,XON2/ADDR2 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,1 Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,1 Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission Control Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,XOFF1 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "UART_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger Level Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,XOFF2 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "UART_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 Frame-length method1 Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 Manual SIP mode: SIP is generated with the control of ACREG[3]1 Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 Starts the Infrared transmission as soon as a value is written to THR1 Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any transmission there must.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=11 TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,0 IrDA/CIR sleep mode disabled1 IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0 UART 16x mode1 SIR mode2 UART 16x auto-baud3 UART 13x mode4 MIR mode5 FIR mode6 CIR mode7 Disable (default state)" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the.." bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode1 Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not effect the RX path in UART Modem modes. 0 inversion is performed1 No inversion is performed" "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles1 Pulse width of 4 from 12 cycles2 Pulse width of 5 from 12 cycles3 Pulse width of 6.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode1 UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0 1 entry1 4 entries2 7 entries3 8 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : 0 the last bit of the frame has been transmitted successfully without error.1 an underrun has occurred. The last bit of.." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read.." bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,1 Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,1 Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,1 Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "UART_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x3 line.long 0x0 "UART_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" wgroup.long 0x30++0x3 line.long 0x0 "UART_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode. If only one start flag is required. this will always be 0xC0. If n start flags are.." bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 0xFF1 0xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART Autobauding Status Register." bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 =>9600bauds. 01000 =>4800bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "UART_ACREG,IR-IrDA and IR-CIR modes only." bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select: 0 3/16 of baud-rate pulse width1 1.6us" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high1 SD pin is set to low" "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX,0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).1 Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 Long stop bits cannot be transmitted TX.." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action1.." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "UART_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." bitfld.long 0x4 7. "RX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.1 Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x4 5. "DSR_IT,0 DISABLES DSR* INTERRUPT.1 ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].1 Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0 Normal mode for THR interrupt (See UART mode interrupts table).1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)1 DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)2 DMA mode 2 (UART_nDMA_REQ[0] in RX)3 DMA mode 3 (UART_nDMA_REQ[0] in TX)" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL,0 The DMA_MODE is set with FCR[3]1 The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0x8 "UART_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0 The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2])1 The DMA counter will be reset if corresponding FIFO is reset (via FCR[1] or FCR[2])" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,0 No falling edge event on RX CTS* and DSR*1 A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,0 TX FIFO is not full1 TX FIFO is full." "0,1" line.long 0xC "UART_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must take into account the BOF character. therefore to only sent one BOF with no XBOF this.." hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returnedNotes: UART / IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART / IRDA with SIR. MIR and FIR.." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged unconditionally1 No-idle. An idle request is never acknowledged.2 Smart idle. Acknowledgement to an.." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 Wake up is disabled1 Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode1 The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 Clock is running1 Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal Module Reset is ongoing1 Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to.." bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0 Event is not allowed to wake up the system1 EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" line.long 0x4 "UART_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual.." rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO." hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO." hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0 Enables the RHR interrupt.1 Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 TXFIFO_EMPTY interrupt not pending.1 TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 RXFIFO_EMPTY interrupt not pending.1 RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit value selector." hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused." hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused." hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3." bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation1 Disables CIR RX demodulation" "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0 disabled (no override)1 reserved2 Synchronous mode with external clock3 Synchronous mode with generated clock4 ISO 7816 mode T=05 ISO 7816 mode T=16 reserved7.." "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 timeout after at least one character has been received1 periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO7816C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO7816C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO7816reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)1 data in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 Little Endian (LSB First)1 Big Endian (MSB First)" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 Transmitter is shut down1 Transmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 Receiver is shut down1 Receiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows Writing the full 9bit RHR" line.long 0x4 "UART_MAR,Multidrop Address Register." hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register." hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? Writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register." hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART4" base ad:0x52304000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,Divisor Latches Low Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.long 0x4++0x3 line.long 0x0 "UART_DLH,Divisor Latches High Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Disables the receive stop interrupt.1 Enables the receive stop interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT,0 Disables the received EOF interrupt.1 Enables the received EOF interrupt." "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Disables the receiver line status interrupt.1 Enables the receiver line status interrupt." "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT,0 Disables the status FIFO trigger level interrupt.1 Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT,0 Disables the last byte of frame in RX FIFO interrupt.1 Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT,0 Disables the CTS* interrupt1 Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,0 Disables the RTS* interrupt1 Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,0 Disables the XOFF interrupt1 Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,0 Disables sleep mode1 Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,0 Disables the modem status register interrupt1 Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,0 Disables the receiver line status interrupt1 Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt1 Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt and time out interrupt.1 Enables the RHR interrupt and time out interrupt." "0,1" line.long 0x4 "UART_EFR,Enhanced Feature Register." bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit.0:Normal operation.1:Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit.0:Normal operation.1:Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE transmission.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation.1:Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit.0:Disables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7.1:Enables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables Writing to IER bits 4-7,1: Enables Writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" wgroup.long 0x8++0x3 line.long 0x0 "UART_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.." bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] =0000br#00: 8 charactersbr#01:16 charactersbr#10:56 charactersbr#11:60 charactersIf SCR[7] = 0 and TLR[7:4] !=0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] =0000br#00: 8 spacesbr#01:16 spacesbr#10:32 spacesbr#11:56 spacesIf SCR[6] = 0 and TLR[3:0] !=0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,0 No change1 Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,0 No change1 Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs.1 : Enables the transmit and receive FIFOs.The transmit and receive holding registers are 64-bytes FIFOs." "?,1: Enables the transmit and receive FIFOs" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Receive stop interrupt inactive1 Receive stop interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT,0 Received EOF interrupt inactive1 Received EOF interrupt active" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Receiver line status interrupt inactive1 Receiver line status interrupt active" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT,0 Status FIFO trigger level interrupt inactive1 Status FIFO trigger level interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT,0 Last byte of frame in RX FIFO interrupt inactive1 Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,0 Modem Interrupt. Priority=41 THR interrupt. Priority=32 RHR interrupt. Priority=23 Receiver line status error. Priority=36 Rx timeout. Priority=28 Xoff/Special character. Priority=516 CTS RTS DSR change.." newline bitfld.long 0x0 0. "IT_PENDING,0 An interrupt is pending1 No interrupt is pending" "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1." bitfld.long 0x0 7. "DIV_EN,0 Normal operating condition1 Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 Normal operating condition.1 Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,0 Odd parity is generated (if LCR[3] = 1)1 Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,0 No parity1 A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 1 stop bits (word length = 5 6 7 8)1 1.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1,2,3" line.long 0x4 "UART_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0 No action1 Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x4 5. "XON_EN,0 Disable 'XON any' function1 Enable 'XON any' function" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0 Normal operating mode1 Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the receive input internally" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH,0 In loopback forces DCD* input high and IRQ outputs to inactive state.1 In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0 In loopback forces RI* input high.1 In loopback forces RI* input low." "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 Force RTS* output to inactive (high).1 Force RTS* output to active (low)." "0,1" newline bitfld.long 0x4 0. "DTR,0 Force DTR* output to inactive (high).1 Force DTR* output to active (low)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,XON1/ADDR1 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,IR CIR mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 0 Reception is on going or waiting for a new frame1 Reception is completed" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,IR-IRDA mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,0 Status FIFO not full1 Status FIFO full" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE,0 The RX FIFO (RHR) does not contain the last byte of the frame to be read1 The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only set when the last byte of a frame is available to.." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,0 No frame-too-long error in frame1 Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH.." "0,1" newline bitfld.long 0x0 3. "ABORT,0 No abort pattern error in frame1 Abort pattern is received. SIR & MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.long 0x0 2. "CRC,0 No CRC error in frame1 CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E,0 Status FIFO not empty1 Status FIFO empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART" bitfld.long 0x0 7. "RX_FIFO_STS,0 Normal operation1 At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,0 Transmitter hold (TX FIFO) and shift registers are not empty.1 Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,0 Transmit hold register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,0 No break condition1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,0 No framing error in data being read from RX FIFO.1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,0 No parity error in data being read from RX FIFO.1 Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,0 No overrun error1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Line Status Register 0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,XON2/ADDR2 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,1 Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,1 Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission Control Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,XOFF1 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "UART_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger Level Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,XOFF2 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "UART_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 Frame-length method1 Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 Manual SIP mode: SIP is generated with the control of ACREG[3]1 Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 Starts the Infrared transmission as soon as a value is written to THR1 Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any transmission there must.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=11 TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,0 IrDA/CIR sleep mode disabled1 IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0 UART 16x mode1 SIR mode2 UART 16x auto-baud3 UART 13x mode4 MIR mode5 FIR mode6 CIR mode7 Disable (default state)" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the.." bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode1 Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not effect the RX path in UART Modem modes. 0 inversion is performed1 No inversion is performed" "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles1 Pulse width of 4 from 12 cycles2 Pulse width of 5 from 12 cycles3 Pulse width of 6.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode1 UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0 1 entry1 4 entries2 7 entries3 8 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : 0 the last bit of the frame has been transmitted successfully without error.1 an underrun has occurred. The last bit of.." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read.." bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,1 Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,1 Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,1 Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "UART_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x3 line.long 0x0 "UART_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" wgroup.long 0x30++0x3 line.long 0x0 "UART_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode. If only one start flag is required. this will always be 0xC0. If n start flags are.." bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 0xFF1 0xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART Autobauding Status Register." bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 =>9600bauds. 01000 =>4800bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "UART_ACREG,IR-IrDA and IR-CIR modes only." bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select: 0 3/16 of baud-rate pulse width1 1.6us" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high1 SD pin is set to low" "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX,0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).1 Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 Long stop bits cannot be transmitted TX.." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action1.." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "UART_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." bitfld.long 0x4 7. "RX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.1 Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x4 5. "DSR_IT,0 DISABLES DSR* INTERRUPT.1 ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].1 Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0 Normal mode for THR interrupt (See UART mode interrupts table).1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)1 DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)2 DMA mode 2 (UART_nDMA_REQ[0] in RX)3 DMA mode 3 (UART_nDMA_REQ[0] in TX)" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL,0 The DMA_MODE is set with FCR[3]1 The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0x8 "UART_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0 The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2])1 The DMA counter will be reset if corresponding FIFO is reset (via FCR[1] or FCR[2])" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,0 No falling edge event on RX CTS* and DSR*1 A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,0 TX FIFO is not full1 TX FIFO is full." "0,1" line.long 0xC "UART_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must take into account the BOF character. therefore to only sent one BOF with no XBOF this.." hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returnedNotes: UART / IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART / IRDA with SIR. MIR and FIR.." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged unconditionally1 No-idle. An idle request is never acknowledged.2 Smart idle. Acknowledgement to an.." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 Wake up is disabled1 Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode1 The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 Clock is running1 Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal Module Reset is ongoing1 Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to.." bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0 Event is not allowed to wake up the system1 EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" line.long 0x4 "UART_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual.." rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO." hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO." hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0 Enables the RHR interrupt.1 Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 TXFIFO_EMPTY interrupt not pending.1 TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 RXFIFO_EMPTY interrupt not pending.1 RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit value selector." hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused." hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused." hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3." bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation1 Disables CIR RX demodulation" "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0 disabled (no override)1 reserved2 Synchronous mode with external clock3 Synchronous mode with generated clock4 ISO 7816 mode T=05 ISO 7816 mode T=16 reserved7.." "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 timeout after at least one character has been received1 periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO7816C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO7816C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO7816reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)1 data in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 Little Endian (LSB First)1 Big Endian (MSB First)" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 Transmitter is shut down1 Transmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 Receiver is shut down1 Receiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows Writing the full 9bit RHR" line.long 0x4 "UART_MAR,Multidrop Address Register." hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register." hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? Writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register." hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART5" base ad:0x52305000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,Divisor Latches Low Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" wgroup.long 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.long 0x4++0x3 line.long 0x0 "UART_DLH,Divisor Latches High Register." hexmask.long.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Disables the receive stop interrupt.1 Enables the receive stop interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT,0 Disables the received EOF interrupt.1 Enables the received EOF interrupt." "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Disables the receiver line status interrupt.1 Enables the receiver line status interrupt." "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 Disables the TX status interrupt.1 Enables the TX status interrupt." "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT,0 Disables the status FIFO trigger level interrupt.1 Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT,0 Disables the RX overrun interrupt.1 Enables the RX overrun interrupt." "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT,0 Disables the last byte of frame in RX FIFO interrupt.1 Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt.1 Enables the THR interrupt." "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt.1 Enables the RHR interrupt." "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT,0 Disables the CTS* interrupt1 Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,0 Disables the RTS* interrupt1 Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,0 Disables the XOFF interrupt1 Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,0 Disables sleep mode1 Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,0 Disables the modem status register interrupt1 Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,0 Disables the receiver line status interrupt1 Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 Disables the THR interrupt1 Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 Disables the RHR interrupt and time out interrupt.1 Enables the RHR interrupt and time out interrupt." "0,1" line.long 0x4 "UART_EFR,Enhanced Feature Register." bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit.0:Normal operation.1:Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit.0:Normal operation.1:Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE transmission.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation.1:Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit.0:Disables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7.1:Enables Writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables Writing to IER bits 4-7,1: Enables Writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" wgroup.long 0x8++0x3 line.long 0x0 "UART_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.." bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] =0000br#00: 8 charactersbr#01:16 charactersbr#10:56 charactersbr#11:60 charactersIf SCR[7] = 0 and TLR[7:4] !=0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] =0000br#00: 8 spacesbr#01:16 spacesbr#10:32 spacesbr#11:56 spacesIf SCR[6] = 0 and TLR[3:0] !=0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0,1,2,3" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,0 No change1 Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,0 No change1 Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,0 Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs.1 : Enables the transmit and receive FIFOs.The transmit and receive holding registers are 64-bytes FIFOs." "?,1: Enables the transmit and receive FIFOs" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT,0 Receive stop interrupt inactive1 Receive stop interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT,0 Received EOF interrupt inactive1 Received EOF interrupt active" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT,0 Receiver line status interrupt inactive1 Receiver line status interrupt active" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT,0 TX status interrupt inactive1 TX status interrupt active" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT,0 Status FIFO trigger level interrupt inactive1 Status FIFO trigger level interrupt active" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,0 RX overrun interrupt inactive1 RX overrun interrupt active" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT,0 Last byte of frame in RX FIFO interrupt inactive1 Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.long 0x0 1. "THR_IT,0 THR interrupt inactive1 THR interrupt active" "0,1" newline bitfld.long 0x0 0. "RHR_IT,0 RHR interrupt inactive1 RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,0 Modem Interrupt. Priority=41 THR interrupt. Priority=32 RHR interrupt. Priority=23 Receiver line status error. Priority=36 Rx timeout. Priority=28 Xoff/Special character. Priority=516 CTS RTS DSR change.." newline bitfld.long 0x0 0. "IT_PENDING,0 An interrupt is pending1 No interrupt is pending" "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1." bitfld.long 0x0 7. "DIV_EN,0 Normal operating condition1 Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 Normal operating condition.1 Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,0 Odd parity is generated (if LCR[3] = 1)1 Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,0 No parity1 A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 1 stop bits (word length = 5 6 7 8)1 1.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0 5 bits1 6 bits2 7 bits3 8 bits" "0,1,2,3" line.long 0x4 "UART_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0 No action1 Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x4 5. "XON_EN,0 Disable 'XON any' function1 Enable 'XON any' function" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0 Normal operating mode1 Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the receive input internally" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH,0 In loopback forces DCD* input high and IRQ outputs to inactive state.1 In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0 In loopback forces RI* input high.1 In loopback forces RI* input low." "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 Force RTS* output to inactive (high).1 Force RTS* output to active (low)." "0,1" newline bitfld.long 0x4 0. "DTR,0 Force DTR* output to inactive (high).1 Force DTR* output to active (low)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,XON1/ADDR1 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,IR CIR mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 0 Reception is on going or waiting for a new frame1 Reception is completed" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,IR-IRDA mode line status register." bitfld.long 0x0 7. "THR_EMPTY,0 Transmit holding register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,0 Status FIFO not full1 Status FIFO full" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE,0 The RX FIFO (RHR) does not contain the last byte of the frame to be read1 The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only set when the last byte of a frame is available to.." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,0 No frame-too-long error in frame1 Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH.." "0,1" newline bitfld.long 0x0 3. "ABORT,0 No abort pattern error in frame1 Abort pattern is received. SIR & MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.long 0x0 2. "CRC,0 No CRC error in frame1 CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E,0 Status FIFO not empty1 Status FIFO empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART" bitfld.long 0x0 7. "RX_FIFO_STS,0 Normal operation1 At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,0 Transmitter hold (TX FIFO) and shift registers are not empty.1 Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,0 Transmit hold register (TX FIFO) is not empty1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,0 No break condition1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,0 No framing error in data being read from RX FIFO.1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,0 No parity error in data being read from RX FIFO.1 Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,0 No overrun error1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Line Status Register 0 No data in the receive FIFO1 At least one data character in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,XON2/ADDR2 Register." hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,1 Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,1 Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission Control Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,XOFF1 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "UART_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger Level Register." hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,XOFF2 Register." hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "UART_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 Frame-length method1 Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 Manual SIP mode: SIP is generated with the control of ACREG[3]1 Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 Starts the Infrared transmission as soon as a value is written to THR1 Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any transmission there must.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=11 TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,0 IrDA/CIR sleep mode disabled1 IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0 UART 16x mode1 SIR mode2 UART 16x auto-baud3 UART 13x mode4 MIR mode5 FIR mode6 CIR mode7 Disable (default state)" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the.." bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode1 Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not effect the RX path in UART Modem modes. 0 inversion is performed1 No inversion is performed" "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles1 Pulse width of 4 from 12 cycles2 Pulse width of 5 from 12 cycles3 Pulse width of 6.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode1 UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0 1 entry1 4 entries2 7 entries3 8 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : 0 the last bit of the frame has been transmitted successfully without error.1 an underrun has occurred. The last bit of.." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read.." bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,1 Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,1 Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,1 Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" wgroup.long 0x28++0x3 line.long 0x0 "UART_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x3 line.long 0x0 "UART_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" wgroup.long 0x30++0x3 line.long 0x0 "UART_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes. then program.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode. If only one start flag is required. this will always be 0xC0. If n start flags are.." bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 0xFF1 0xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART Autobauding Status Register." bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 =>9600bauds. 01000 =>4800bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "UART_ACREG,IR-IrDA and IR-CIR modes only." bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select: 0 3/16 of baud-rate pulse width1 1.6us" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high1 SD pin is set to low" "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX,0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).1 Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 Long stop bits cannot be transmitted TX.." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action1.." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "UART_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." bitfld.long 0x4 7. "RX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.1 Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x4 5. "DSR_IT,0 DISABLES DSR* INTERRUPT.1 ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].1 Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0 Normal mode for THR interrupt (See UART mode interrupts table).1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)1 DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)2 DMA mode 2 (UART_nDMA_REQ[0] in RX)3 DMA mode 3 (UART_nDMA_REQ[0] in TX)" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL,0 The DMA_MODE is set with FCR[3]1 The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0x8 "UART_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0 The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2])1 The DMA counter will be reset if corresponding FIFO is reset (via FCR[1] or FCR[2])" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,0 No falling edge event on RX CTS* and DSR*1 A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,0 TX FIFO is not full1 TX FIFO is full." "0,1" line.long 0xC "UART_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must take into account the BOF character. therefore to only sent one BOF with no XBOF this.." hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returnedNotes: UART / IRDA SIR only module is revision 1.x (WMU_012_1 specification). UART / IRDA with SIR. MIR and FIR.." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged unconditionally1 No-idle. An idle request is never acknowledged.2 Smart idle. Acknowledgement to an.." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 Wake up is disabled1 Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode1 The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 Clock is running1 Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring 0 Internal Module Reset is ongoing1 Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to.." bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0 Event is not allowed to wake up the system1 EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0 Event is not allowed to wake up the system1 Event can wake up the system" "0,1" line.long 0x4 "UART_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual.." rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO." hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO." hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0 Enables the RHR interrupt.1 Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 TXFIFO_EMPTY interrupt not pending.1 TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 RXFIFO_EMPTY interrupt not pending.1 RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit value selector." hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused." hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused." hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3." bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation1 Disables CIR RX demodulation" "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0 disabled (no override)1 reserved2 Synchronous mode with external clock3 Synchronous mode with generated clock4 ISO 7816 mode T=05 ISO 7816 mode T=16 reserved7.." "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 timeout after at least one character has been received1 periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO7816C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO7816C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO7816reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)1 data in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 Little Endian (LSB First)1 Big Endian (MSB First)" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 Transmitter is shut down1 Transmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 Receiver is shut down1 Receiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register." hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows Writing the full 9bit RHR" line.long 0x4 "UART_MAR,Multidrop Address Register." hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register." hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? Writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register." hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree.end tree "WDT" base ad:0x0 tree "WDT0" base ad:0x52100000 group.long 0x0++0x1B line.long 0x0 "WDT_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "WDT_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "WDT_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "WDT_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "WDT_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "WDT_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "WDT_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "WDT_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x001F_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "WDT_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "WDT1" base ad:0x52101000 group.long 0x0++0x1B line.long 0x0 "WDT_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "WDT_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "WDT_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "WDT_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "WDT_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "WDT_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "WDT_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "WDT_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x001F_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "WDT_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "WDT2" base ad:0x52102000 group.long 0x0++0x1B line.long 0x0 "WDT_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "WDT_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "WDT_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "WDT_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "WDT_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "WDT_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "WDT_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "WDT_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x001F_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "WDT_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "WDT3" base ad:0x52103000 group.long 0x0++0x1B line.long 0x0 "WDT_RTIGCTRL,Global Control Register starts / stops the counters ." hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode [read]:0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0].User and privilege mode [read]:0 = counters are stopped1 = counters are runningPrivilege mode [write]:0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT_RTITBCTRL,Timebase Control selection which source triggers free running counter 0 ." bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode [read]:0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT_RTICAPCTRL,Capture Control controls the capture source for the counters." hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode [read]:0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT_RTICOMPCTRL,Compare Control controls the source for the compare registers." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode [read]:0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT_RTIFRC0,Free Running Counter 0 current value of free running counter 0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x14 "WDT_RTIUC0,Up Counter 0 current value of prescale counter 0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT_RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT_RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 0 on.." line.long 0x4 "WDT_RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event." hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT_RTIFRC1,Free Running Counter 1 current value of free running counter 1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode [read]:current value of the counterPrivilege mode [write]:The counter can be preset by Writing.." line.long 0x4 "WDT_RTIUC1,Up Counter 1 current value of prescale counter 1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT_RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT_RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event." hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode [read]:value of Free Running Counter 1 on.." line.long 0x4 "WDT_RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event." hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT_RTICOMP0,Compare 0 compare value to be compared with the counters." hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT_RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match." hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT_RTICOMP1,Compare 1 compare value to be compared with the counters." hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT_RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match." hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT_RTICOMP2,Compare 2 compare value to be compared with the counters." hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT_RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match." hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT_RTICOMP3,Compare 3 compare value to be compared with the counters." hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT_RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match." hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT_RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit." hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode [read]:current compare valuePrivilege mode [write when.." line.long 0x24 "WDT_RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit." hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT_RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT_RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation." hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode [read]:0 = DMA request is disabled1 = DMA request is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode [read]:0 = interrupt is disabled1 = interrupt is enabledPrivilege mode [write]:0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT_RTIINTFLAG,Interrupt Flags interrupt pending bits." hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode [read]:determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode [read]:this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode [read]:determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode [write]:0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT_RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog." hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode [read]:0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged [enabled or disabled]Priviledge.." line.long 0x4 "WDT_RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode [read]:A read from this register in any CPU mode returns the current preload value.Priviledge mode [write]:The DWD preload register can be configured only when the DWD is.." line.long 0x8 "WDT_RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog." hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode [read]:0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode [read]:0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode [read]:0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode [read]:0 = AWD pin 0 > 1 threshold not exceeded1 = AWD pin 0 > 1 threshold exceededPriviledge mode [write]:0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT_RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor." hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode [write]:A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT_RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter." hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x001F_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT_RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset." hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode [read] privileged mode [write]:0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT_RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog." hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode [read] privileged mode [write]:Value written to WWDSIZE Window Size0x00000005 100% [Functionality same as the time-out digital.." line.long 0x1C "WDT_RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts." hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode [read]:0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT_RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line." hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT_RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line." hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT_RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line." hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT_RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line." hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree.end newline AUTOINDENT.OFF